Fundamentals of Logic Design - Electrical and Computer Engineering

University of California, Santa Barbara Department of Electrical and Computer Engineering 1.

Course Syllabus ECE 15A

Fundamentals of Logic Design (Required)

3 units

Catalog Description: Boolean algebra, logic of propositions, minterm and maxterm expansions, Karnaugh maps, Quine-McCluskey methods, melti-level circuits, combinational circuit design and simulation, multiplexers, decoders, programmable logic devices. Prerequisites: ECE 2A with a minimum grade of C-; open to electrical engineering, computer engineering and pre-computer engineering majors only. Text, References, and Software: C.H.Roth, Fundamentals of Logic Design, 5-th edition. Topics Covered and Course Goals: 1. Abstract concepts: a. The algebra of sets: Element and set; the combination of sets; Venn diagrams; fundamental laws; expansion, factorization and simplification; properties of set inclusion, conditional equations, solutions of equations, the number of elements in a set. Boolean algebra: AND/OR/NOT gates, Boolean expressions and truth tables, basic theorems. b. Boolean algebra: Commutative, associative and distributive laws; Boolean simplification using algebraic methods; De Morgan’s theorems; dual of a Boolean expression, XOR gate and equivalence operation; consensus theorem, algebraic simplification of Boolean expressions, proving that a Boolean equation is valid.

2. Boolean functions: a. Disjunctive normal form, truth tables, lexicographic order, conjunctive normal form, complements, minterms and maxterms. b. Canonical representations of Boolean functions, standard forms, XOR and equivalence operation; functionally complete functions.

3. Digital circuits: a. implementing Boolean functions, digital circuits, noise margins, simplification of Boolean functions and different realizations of functions, conversion of English sentences to Boolean equations, Karnaugh map method, Quine-McCluskey method, Petrick’s method; b. conversion of forms, mapping AND/OR network to NAND/NAND network, mapping AND/OR to NOR/NOR, mapping OR/AND to NOR/NOR, mapping OR/AND to NAND/NAND, multi-level logic; c. simple timing model (based on gate delays) for combinational circuits, time response in combinational networks, gate delay, propagation delay, static and dynamic hazards, eliminating 0- 1nd 1-hazards; d. mapping real-world word problems to incompletely specified functions. e. multiplexers, decoders, encoders, PAL and PLA, ROM/RAM; how to solve real-world word problems by using these components

Class/Laboratory Hours: Lecture, 3 hours; discussion, 1 hour Contribution to Criterion 5 Contributes to component (b) Contribution to Program Outcomes: Course Goals 1.a 1.b 2.a 2.b 3.a 3.b 3.c 3d 3.e

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Prepared by: M.Marek-Sadowska

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Date: 2/15/08

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