generalized multiprocessing and multiprogramming systems

GENERALIZED MULTIPROCESSING AND MULTIPROGRAMMING SYSTEMS -Status Report-

A. J. Critchlow IBM Corporation San Jose, California the job program and the relative priorities of other programs. Scheduling algorithms aim to optimize performance of the system with respect to chosen goals. 4. Allocation-is the assignment of particular facilities: core memory, tapes, disk files to a job program. 5. Interrupt and Trapping are considered synonymous. Both mean the ability, provided by hardware, to monitor particular conditions in the system during execution of all other operations and to provide an alarm signal which can interrupt a processor to obtain required action. Program interrupts or Intentional interrupts are really branching operations which sometimes use the alarm signal hardware.

1.1 DEFINITIONS In this paper, the following definitions have been followed: 1. Multiprogramming-the time-sharing of a processor by many programs operating sequentially. Many programs are available and in memory but only one program is actually being executed at a given time. Control of object programs is provided by a supervisory control program. Thruput is highest when many programs can be interleaved to use hardware most efficiently. In general, the time required to complete a selected program will be increased over single program operation. 2. Multiprocessing-independent and simultaneous processing accomplished by the use of several duplicate hardware units. Specifically, duplicate logical and arithmetic units are assumed, although systems with separate input-output channels can also be said to be multiprocessors. Note that "processors" do not include storage units while "computers" do. (Table 1.2.2) 3. Scheduling-is the determination of the sequence in which job programs will use the available facilities. Scheduling assignments are based on the availability of all required facilities, the priority of

1.2 BACKGROUND

1.2.1 Development of Multiprogramming Multiprogramming is expected to be more efficient than single-program operation because facilities are used which would be idle otherwise. It is necessary that the control cost of multiprogramming be less than the increased output of useful work if a net gain in efficiency is to be achieved. The first approach to multiprogramming was to select or match two or more programs so

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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1963

that better utilization of facilities was obtained. Scientific programs, in general, provide a heavy load on the processor and a light load on peripheral equipment. Business data processing tends to load peripherals in order to produce the sorted data and output of printed reports required. Combining these two types of operation uses facilities more effectively. Codd (1) reports timing improvements of 2 to 1 when multiprogramming mixed program sets. An added complexity is introduced, however, because both programs may need the same facility simultaneously, so one of them must wait. In more complex operations with many programs and perhaps more than one processor, the sequencing of operations becomes quite difficult. At first the programs to be run together were assembled onto one magnetic tape with sequencing information included on the tape so the two programs were, in effect, just one large program. Running programs this way is efficient if all the programs ar:e production programs which can be run on a regular schedule. When one program must be altered or deleted, it is necessary to reassemble the program tape at a considerable time cost.

When control of multiprogramming operation is turned over to an executive program and there are suitable hardware provisions for interrupt, memory protection, priority control, etc., it is possible to write each program as though it alone is being run. The multiprogramming sequencing, queuing and input-operation task is handled by the Executive program.Efficient operation requires that many programs be available ready to run so that the Scheduler or Sequencer program will have several possible choices to maximize operational efficiency. (Table 1.2.1) An example of the dynamic scheduling of many programs to run together on the same system is worked out in section 4.2.2. Communication between programs is necessary so that branching to subroutines can be accomplished. One solution is to have a "common" area of memory for subroutines used by several programs. A more flexible method utilizes a "universal" symbol which is recognized by the supervisory program. The supervisory program maintains a table of addresses for subroutines and supplies the required address when signalled by use of the "universal" symbol request.

Table 1.2.2-Classification of Functional Types System CDC 3600

Data Processor

Instruction Processor

Input-Output Processor

Switching Central

Storage Processor

Computation Module

Computation Module (overlapped memory operation)

iHousekeeping Module or Data Channel

Multiple Gates

Storage Mod. (8 prs of 16,384 wds. ea. (access overlapped)

3

& Registers on

Memory Module ( overlapped operation) (16 of 4096 wds. ea.)

4

Primary Storage, Secondary Storjage, 3rd Storage

29

Storage Module

Burroughs D-825

Computer Module

Computer Module

Input/Output Control Modules & Automatic I/O Exchange Crossbar Switch (64 devices)

~ilot-Multi-

Primary Qomputer

Secondary Computer

Format Computer Communicate (1/0 Trunk thru Primary Control) Storage

(a) Arithmetic Unit (b) General Comparator (c) Logical Unit

Program Distributor Data Distributor

Transcoder

[pIe Computer ~ystem

lGamma 60

Icentral (parts of the program 1& Coord-Umt)

Crosspoint Swjtch Matrix (4 X 16) Bus Allocator (priority basis)

Data Distributing Channel & Data Collection Channel Central Program & Co-lordmatIOn u mt

lCentral Store

'".

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Ref·

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GENERALIZED MULTIPROCESSING AND MULTIPROGRAMMING SYSTEMS

1.2.2 Growth of Multiprocessing (Table 1.2.2) By definition, the Princeton machine designed by Burks, Goldstine and von Neumann (2) in 1946, will be called a "conventional processor" or uni-processor. This was a parallel machine, with a hierarchy of memories which could be accessed sequentially. In the IBM 701, the input-output equipment was controlled directly by the processor. All timing of tape gap times, card feed delays, etc., was controlled by the computer.

Data Channels (I/O Channels) Data channels were a considerable improvement. As described in section 3:2, they made possible the simultaneous operation of peripheral equipment and the central processor.

Separate I/O Processors Next on the trail to multiprocessing is' the use of a completely separate Input-Output Processor with its own memory. Noteworthy among those in daily use is the IBM 1401 which is used with a high percentage of the 7090-94 installations. Many of these are used as offline computers with the only means of communication a reel of magnetic tape. Others are directly cable-connected and provide editing, data conversion, peripheral control and communication control functions.

Multiple Computers Multiprocessing has come to fruition with such systems as the multiple computer CDC3600 ( 3 ) and D-825 systems ( 4). These systems were designed as multiprocessors and have the flexible coupling and control provisions necessary (sections 3.0, 4.0, 5.0).

Possible Future Steps The next step may be in either of two directions or a combination of the two. Networks of processors all controlled by the same control unit have been proposed and partially designed. Solomon (5) and the Holland (6) iterative network are examples. They .appear to have advantages in large matrix or relaxation problems where many computations can be carried on in p~ralleI. As many as 2000 parallel processors have been proposed.

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Another possibility is an extension of the modular unit approach of the Gamma 60 (7) to a multiprocessor system in which specialized Add-Compare Units, Multiply Divide Units, Edit Units, Logical Operation Units, Shift Units, etc., would efficiently perform one service. Problems of loading and scheduling are critical in the success of such a system. A very large number of problems is required to produce a good statistical mix so units can be efficiently used. 2.0 GOALS OF MULTIPROGRAMMING AND MULTIPROCESSING There are two competing trends in modern data processing, the trend toward large, complex, centralized systems and the opposite trend toward small, simpler decentralized systems. Advocates of the centralized systems point to the growing need for communication between computers and the resulting ability to gather large quantities of data at one place. Then, they argue, the most efficient, most reliable, most flexible way to handle this large mass of data is by multiprogramming and multiprocessing (8, 9, 10). Decentralization advocates point to the convenience of small computers and argue that a simple computer can do a simple task more economically. Furthermore, many businesses like to control their own data and will pay a small increased cost for this privilege if necessary (11). Multiprocessing systems emphasize the characteristics of reliability, efficiency, flexibility and capability to differing extent depending on the application. A spare processor is used to provide increased reliability in military command and control applications and in the SABER commercial airline reservation system. The additional processor was used as a standby only in case of failure. More recent systems obtain increased efficiency and capability by coupling processors through disk files (12, 13) and also thru switching centrals (14). One important recent activity is the development of systems with multiple remote terminals, each "time-sharing" the centralized system (10, 15). These systems assume the existence of multiprogramming so that each termi-

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nal may operate as though the others do not exist and it alone controls the computer. In the following paragraphs some of the advantages of the large multiprocessing and multiprogramming system are described and evaluated. Note, however, that multiprogramming ability on small systems is also being actively considered (16). 2.1 INCREASED EFFICIENCY

gram. A maj or source of programming errors is I/O handling. As described in section 4.0, the programmer's task is simplified on I/O since the details are handled by the supervisory program. In addition, program loops, memory address errors, and other program errors are prevented from tying up the system.

2.2.3 Automatic Facilities

Switchover and

Recovery

Fuller use of equipment can be brought about by "time-sharing" and "space-sharing." Processors, switching equipment, input-output controls and memory address registers may be time-shared. Core memories, disk files, and to some extent, magnetic tapes and printers may be space-shared.

A price paid for multiprocessing and multiprogramming is the complexity of the system. The Executive, Scheduler and other control programs are difficult to write. When an error occurs, it may affect several programs. (It is possible for a disk head to drop down and mangle the data on many disk tracks, for example.)

2.2 INCREASED RELIABILITY

It is essential to provide backup and recovery capability in the system. In case of subsystem failure, it is relatively easy to provide for switching in another subsystem.

Multiprocessing systems provide increased reliability by: sharing of duplicate equipment, automatic switch over and recovery facilities, built-in error detection and correction, prevention of error by automatic supervisory control and performance monitoring, the use of diagnostic programs to catch marginal conditions, and improved maintenance facilities on the computer site. Many of these capabilities are available in uniprocessing systems but receive added emphasis in multiprocessing systems. In general, the large volume of operation on multiprocessing systems makes increased reliability necessary but also provides economic feasibility by sharing costs over many tasks.

2.2.1 Sharing of Duplicate Equipment An efficient centralized system can use duplicates ·of each item of equipment to share the total operational load. Good design consists of balancing the system so essential peak activities can be handled even if some part of the system fails. In normal operation the additional capacity can be. fully absorbed doing routine work. If necessary, additional work load can be brought in on communication lines to keep the system fully loaded.

2.2.2 Automatic Supervisory Control ~fany programming errors can be prevented or made harmless by a good supervisory pro-

2.3 INCREASED CAPABILITY Some tasks require high speed processors, large memory capacity, many tape units, large disk files or multiple path communications. These tasks cannot be done effectively on small systems. Sorting of large files, design automation programs, and linear programming of inventory problems are three types of business problems where large memory (16 to 32K) and many I/O units are required. Ward (18) argues that faster computation is more important than better organization or parallel computation. He mentions several problems requiring speed increases 100 times as great as present computers such as: ballistic missile and satellite launch, neutron diffusion problem in reactors (50 3 grid points), Monte Carlo problems and the weather research problem (10 5 grid points). It appears also that large, fast memories would be required for these applications. Faster computation or increased thruput capacity is possible on some problems by using multiple processors to run the same program. M. Con'vay's paper (this issue) illustrates this capability.

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GENERALIZED MULTIPROCESSING AND MULTIPROGRAMMING SYSTEMS

Multiprogramming and multiprocessing make economically feasible three new capabilities which are expected to greatly extend the usefulness of computers.

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puter control. The delay due to mailing of orders, receipts and bills is avoided and accurate records are kept of all transactions. 2.4 SIMPLIFIED OBJECT PROGRAMMING

2.3.1 On-Line Debugging Since many programs may be in the system at one time, it is possible for programmers to enjoy the luxury of console debugging without slowing the processor appreciably. Instead of time-consuming memory dumps or traces, the programmer can guide his program from error to error, correcting as he goes. Program debugging has been reported to take up to 32 j{: of processor time, so this capability is of considerable value.

2.3.2 Man-Machine Interaction Many engineers who use computers will welcome the ability to get only the data they need without the necessity for requesting in advance that all possible permutations of the data be calculated. Guidance from a knowledgeable scientist or engineer is made possible by a timesharing console. Singularities or unreal trends in the course of computation can be halted quickly so that errors do not result in a pile of v.seless paper. More significant is the use of control and display consoles to allow the computer .to assist in the design process. Calculation, data storage and display reduce the routine work of design so that greater creativity can occur (19).

2.3.3 Remote Operation and Communication The high reliability and great flexibility of a multicomputer system means that it can perform useful services to a wide group of users on a time-shared subscriber basis. Small companies or even individuals may have a typewriter-like keyboard-printer available to handle all business transactions. Airline reservations systems are well known. Not so well known are the integrated business systems which provide a network of c()mmunication lines to control and record sales and inventory transactions. Direct communication from the sales office to the warehouse provides for ordering, billing, inventory control and warehouse picking operations, all under com-

Control of a multiprogramming, multiprocessing system requires a complex supervisory program (section 4.2), which is difficult and expensive to prepare. (Similar programs are required for uniprocessor systems, but are much simpler.) In return for this complexity, which is largely assumed by the system manufacturer, the programmer's tasks become simpler in the following ways: 1. Input-output control is handled by the supervisory programs so all problems of timing, interaction, assignment and error control are eliminated from the object programmer's responsibility. 2. Addressing can be symbolic for memory and peripheral equipment. 3. If "page turning" capability is available, the programmer can write programs as though a large core memory is available rather than being restricted to small memories. 4. A large library of specialized routines can be called upon by the programmer to do specific tasks. These subroutines can be written by specialists so they perform efficiently. Calling routines for these programs are simplified because of assistance from supervisory programs. 5. Increased specialization of programmers becomes possible so that each programmer need not know all the formidable array of techniques and methods now available. Simplifications of the programmer's tasks are increasingly important as more computers are installed and the need for programmers increases. 3.0 SYSTEM CONTRO~REQUIREMENTS AND EVALUATION OF TECHNIQUES 3.1 CENTRAL SWITCHING OR MEMORY ACCESS CONTROL (Table 3.1) Requests for memory access can come from two to '·five processors, Input-Output exchanges,

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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1963

Table 3.1 Memory Access Control

Technique Example

Hardware Cost

1. Crosspoint Switch Switching interlock is provided by a crosspoint switch matrix and a bus allocator to resolve time conflicts. Queued in priority order.

Crosspoint matrix (4 computer modules to 16 possible memories). Full crosspoint would require an estimated minimum of 300,000 switch points.

D-825

5 sets of address registers, gates and line drivers.

CDC-3600

Lookahead unit has 4 sets of address and operand registers and 5 control counters.

STRETCH IBM 7030

2. Multiple Bus Connected Five-way switch built into storage module. (Processors can transmit address to storage module and request service on a first come, first served basis.) 3. Time-Shared Bus Bus control unit receives memory requests from Lookahead unit. Handles requests in priority order based on availability. Bus is time-shared on 0.2 }J>sec. cycle. Control decisions overlap address 'transmission to memory units.

Data Channels, and in some cases, directly from peripheral equipment. Many of these requests are urgent and must be handled on a priority basis.

3.1.1 Crossbar Switch The crossbar switch or cross point matrix provides multiple-wire paths from M requesting modules to N accepting modules. Each path may be on the order of 50 to 100 lines wide in order to carry full memory words (36 to 72 lines), memory addresses (12-16 lines) and control signals (6 to 20 lines) . Sometimes cables are unidirectional so that another set of 50 to 100 lines is required in the opposite direction. Crossbar switches were first developed for telephone switching and were electromechanical. The crosspoint matrix switches used in computers have been transfluxor magnetic cores (RW-400) or diode AND gates. In the D-825 (4) (Figure 3.1.1), provisions are made for modular addition of switching matrices and associated controls so that a maximum of 4 computer modules can access 16 possible memories. A minimum of 300,000 switching points would be required for a complete system

Example

so that the cost approaches or exceeds the cost of a large computer module. Tremendous flexibility is obtained in a crosspoint switch since any processor can connect to any memory in a fraction of a microsecond. Also, there are numerous ways to provide a function in case of failure in any part of the system. Duplication of the crosspoint matrix is required, however, in a system requiring maximum reliability.

3.1.2 Multiple-Bus Connected A lower cost system than the crosspoint matrix is provided by use of separate busses connecting a processor (or input-output channel) to one or more specific memories (Figure 3.1.2). The saving is due to the reduction in the number of switch points. Each computational module may have a direct connection to private storage in addition to sharing common storage. This technique is less flexible than the crosspoint matrix but may be completely adequate in a system designed for a specific range of applications. If connections are easily changed physically, it is much less expensive to set up new paths by plugging rather than by switching.

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GENERALIZED MULTIPROCESSING AND MULTIPROGRAMMING SYSTEMS

MAGNETIC TAPE TRANSPORT

MAGNETIC DRUMS (TWO PER CABINET)

MAGNETIC D!SK F!LE

113

o o

AUTOMATIC INPUT/OUTPUT EXCHANGE (MAX!MUM OF 64 DEVICES)

"'-

DATA CHANNEL

Figure 3.1.1. D825-A Multiple-Computer System for Command and Control.

3.1.3 Time-Shared Bus The lowest cost switching system, Figure 3.1.3, takes advantage of the availability of memory registers in each processor and each memory module to allow the bus system to be time-shared. Instead of connecting a processor and memory continuously, they are connected for only the time required to transfer information. This technique is especially useful if memory accesses can be pre-planned such as in sequential instruction fetches and data fetches. More than one channel can be used if the number of accesses required becomes large enough to slow down the total access time. Multiple bus channel control, priority switching requirements and the need for twoway transmission add to control complexity. A system of this type was used on the IBM 7030 (STRETCH). 3.2 I/O SWITCHING AND CONTROL In the early days of computers, the computer operated peripheral equipment directly. If a tape was to be read or written, all other activity

Figure 3.1.2. Two-computer System with Private and Common Storage (CDC-3600).

was stopped while the computer controlled the transfer of information between the tape and core memory. Memory addresses were prepared, timing of tape gaps was calculated and the remainder of the system sat idle.

3.2.1 Input-Output Channels (Data Channels) Input-output channels were a great improvement. Each channel had direct access to memSTORAGE MODULE

STORAGE MODULE

STORAGE MODULE

PROCESSOR

PROCESSOR

NO.1

NO.2

Figure 3.1.3. Time-Shared Bus Assignment.

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PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1963

ory, with its own address register and the ability to keep a count of the number of records transferred. Even these channels sometimes used the address preparation and arithmetic capabilities of the main computer. Also, since they shared the main memory, an interrupt system was required to insure priority of access to memory for peripheral information. This simple interruption to enter data into memory is quite efficient since the I/O channel "steals" only a memory cycle as needed where the complex program interrupt requires storage and retrieval of arithmetic registers, etc.

3.2.2 Asynchronous Input-Output Requirements Multiprogrammed and multiprocessor systems must operate in an uncontrollable environment, accepting information from many sources simultaneously, processing it and dispatching the processed information to many points. Earlier systems attempted to provide synchronous switching systems to cope with these problems but had no way to handle the frequent, probabilistic stacking up of control or information requests. It was found necessary to provide for queuing of requests and buffering of information flow.

3.2.3 Control Word Philosophy The STRETCH exchange has 256 words of core storage to provide an essential control function in a complex system (20) . Instead of providing hardware registers to store addresses and counts for the control of peripheral channels, the control words are stored in a fast (one :microsecond access) core memory and one set of hardware registers are timeshared in a rapid, asynchronous sequence. When a memory access request is made, the required control words are pulled from memory to the control registers and used to set up the necessary switching paths. These control words are then updated by adding one to the address, deducting one from the word count, modifying status conditions, and replaced in memory.

3.2.4. Queuing of I/O Requests Systems loading is controllable to some ex-

tent by refusing to start l1ew tasks until previous tasks are completed. Three types of queues are maintained in a multiprocessing, multi programmed system: 1. New tasks not yet started. 2. Tasks partially completed, awaiting completion of a specific peripheral operation. 3. Tasks being run on one of the system processors. In addition, there may be "standby" tasks such as diagnostics, program check runs, or billing runs which can be pulled in whenever processor loading permits. Queuing is controlled by an operating system program called the Peripheral Control Program, Input-Output Supervisor or a similar title (section 4.2.4). These programs maintain peripheral cuntrol tables containing essential information about each program and each piece of equipment. 3.2.5 I/O Processors The STRETCH exchange was really a small separate input-output processor with memory and limited instruction capability. Many variations on this approach have been tried. In the CDC-3600, a separate housekeeping module is provided which handles all inputoutpu~ functions including a number of data channels. The CDC-3600 can also use a CDC160 as a direct on-line processor handling peripheral equipment. An I/O Control Module on the Burroughs D-825 is connected to an automatic I/O exchange to provide control signals, parity checks, timing interface and data conversion. It contains a separate instruction register, decoding circuitry, data register and a data manipulation register.

It is also possible to come full circle back to using the main computer as an I/O processor. In a multi programmed system with powerful interrupt and sufficiently rapid storage and retrieval of status information, timesharing of the central processor becomes feasible. When all registers are in thin-film memory, for example, program interruption can be accomplished by merely changing the program

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GEXERALIZED :MULTIPROCESSING AND MULTIPROGRAMMING SYSTEMS

counter to a new address so that no time penalty is paid for an interrupt. 3.3 PRIORITY AND INTERRUPT CONTROL Multiprogramming and multiprocessing cannot be done effectively without the ability to establish priority between programs and to interrupt operations when events of higher priority demand attention. Older computers ran one program until it was completed, performing tests for only those occurrences which the programmer could anticipate. Since testing was costly in processor time it was done initially only to detect such items as overflows or underflows in arithmetic or .to determine whether a peripheral had completed an assigned task. Later computers had the ability to "trap" and react to an unusual occurrence by passing program control to a specified location in memory. This testing was done by separate hardware in parallel with processor operation and did not delay the object program being run unless the trapping operation actually occurred. After trapping, the program was required to search a register to find out the cause of interference and then jump to a new program to take action. This slow procedure was adequate for un iprogramming systems. In a complex system, searching of a number of interrupts is too time-consuming, so a better way was sought. Present systems provide multi-level interrupt ability so that an interrupt causes direct transfer of control to the location of the program which is to handle the interrupt. Several types of interrupt may be provided. Some types are: 1. I/O interrupts; at the completion of an assigned task by a peripheral, arrival of an -I/O request or perhaps from an operator at a console. 2. Program interrupts may occur due to arithmetic overflow, the periodic signal from an elapsed time clock or an interrupt instruction in the program itself. 3. Malfunction interrupts are those from an I/O malfunction such as a broken tape, card jam, or parity error, or major equip-

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ment malfunctions such· as memory parity, error or failure of a subsystem to respond when interrogated. Each interrupt must be accepted and eventually handled. If too many control interrupts come in and some are lost there is loss of input or output information. To prevent this, interrupts must be handled rapidly with the highest priority items handled first. Queues of interrupts are built up on each requested facility under the control of a supervisory program in the operating system. The requirements of service are taken into account- in assigning priority levels. Highest priority must go to serious malfunctions such as power failure, next to error causing malfunctions such as memory parity error, then to peripherals which must be serviced within a limited time, and finally to requests from the processor itself. Processors can always wait for memory access since no information is lost. However, no designer feels happy about forcing a high speed processor to be idle. During an I/O interrupt where a separate data channel to memory is available, the processor is not affected except in being denied access to memory. During a processor interrupt it is necessary to perform several operations in a short time. These functions, .accomplished partially by hardware and partially by program are: 1. Prevent additional interrupts at this priority level and lower priority levels. 2. Store present contents of all registers affected by this interrupt class. (This can be done with a SA VE instruction which transfers register contents to memory.) 3. Determine interrupting channel and device. (Automatic in a well designed system.) 4. Determine cause of interrupt. (Encoded on interrupt lines in some systems, program scan required in others.) 5. Determine required action. (May be prestored in memory location addressed by interrupt.)

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6. Determine urgency of interrupt, assign priority and set task in a processing queue .. (Although interrupt is high priority, action may be data dependent so that delay is tolerable.) 7. Perform action required by interrupt. 8. Test for additional interrupts at this and lower priorities and handle if they exist. (Higher priority interrupts would have caused storage of information and queuing of this interrupt request.) 9. Restore register contents and continue interrupted program.

as follows. (In the dual system a central exchange has been added to connect processors to memory.) U

= Un i-Processor System

2.04

1. Processor ( 1 ) 2. Memory (1)

1.86

3. Tape Control (1) (Handle 32 tapes)

1.0

4. Tape Units (12) (Each 0.2)

2.4

Interrupt routines are part of the Executive program. Unless the proper hardware capabilities are available, the Executive program becomes complicated and unwieldy.

5. -------------------------------Cost

In a well designed system with several processors, the total supervisory control system can be as low as 5000 words and still perform all essential functions, since hardware performs many of the time and memory consuming operations. Such systems make multiprogramming and multiprocessing feasible (9).

Processor (2)

4.08

Memory (1)

1.86

Tape Control (1)

1.0

Tape Units (20)

4.0

4.0 SYSTEM DESIGN AND OPERATION In order to meet the goals described in section 2.0 an integration of hardware, software and application knowledge is essential in order to analyze the trade-offs and compromises to be made. 4.1 SYSTEM PLANNING AND SIMULATION In system planning, a set of success criteria is required. For some types of scientific work the utmost in speed and capacity may be the goal.

Performance/Cost Ratio For the multiprocessing system the goals are efficiency, reliability, and capability. The final measure is the ratio of performance to cost. As an example of a method of calculation, assume the multiprogramming load of section 4.2.2 is typical. In addition, use some estimated figures for the ratios of input-output processor cost1 tape system costs and central switching costs· so that a set of cost figures are obtained

D = Dual Processor System

0.5 11.44

Central Exchange (1 ) (Each.5 X 106 X) . D 11.44 = 1.57 Cost ratIo = U = 7.30

Performance can be calculated on the basis of equipment usage of the two systems at the costs estimated, noting that the multiprocessor system is doing, in addition, programs Number 2 and 3 (of 4.2.2). Uniprocessor System (Programs #1, #5, #6) 1. Processor 90 % X 2.04 2. Memory

=

18

32 X 1.86 =

1.05

12 3. Tape Control 32 X 1.0 4. Tape Units 100 % X 2.4

1.84

.38

=

Performance

2.40 5.67

Uni-System Cost/Performance = ~:~~ = 77.8 % Dual-Processor System (Programs #1, #5, #6, #2, #3) -

160

1. .Processors 200 X ·1:.08

=

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3.27

GENERALIZED MULTIPROCESSING AND MULTIPROGRAMMING SYSTE,MS

28 2. Memory 32 X 1.86 3. Tape Control

20 32

1.63 .63

X 1.0

4. Tape Units 100 % X 4.0 =

4.00

160 5. Central Exchange 200 X .5

040

Performance

9.93

Performance Ratio

~

= 1.11

Dual System Cost/Performance =

Ii:!! =

86.5%

Even though an expensive processor and central exchange was added, an increase in performance was obtained in the dual system. It does not seem worthwhile, however, to add enough additional equipment to handle Program #4, although with a 16K memory instead of a 32K memory it may be close. While hand calculations of this kind are instructive it is necessary to consider many more factors in more complex ways in a real system. Analytic methods have not been satisfactory so simulation methods have been used extensively.

Simulation Smith (21) describes the use of the General Purpose Systems Simulator (GPSS) developed by Gordon (22) which was used to an.alyze a multiprocessing, multiprogramming system. Some results of simulation described by Smith (21) show 11 % increase in thruput of four 7090's connected in a multiprocessor configuration compared to four separate 7090's.

core memory may be used but there is a trend toward fixed memory (or "read only" memory). The hierarchy of control is shown in Figure 4.2.1, while detailed sequencing of control is shown in Figure 1.2.1.

4.2.1 Executive After initial loading of programs by the Loader routine, control of the system is turned over to the Executive which assigns tasks to other routines and monitors system performance. Errors of all types cause program interruption to the error routines controlled by the Executive. In addition, the Executive handles interrupts of all kinds. Each object program requests attention from the Executive and is assigned a number and a priority based on its intrinsic priority or required completion time. It is then turned over to the Scheduler for assignment of facilities.

4.2.2 Scheduler The Scheduler maintains a list of system facilities and the programs currently queued on those facilities. Each incoming program is provided with a header which contains such information as: Memory space required, number of tapes required, output requirements, estimated running time and estimated completion time. The Scheduler. examines the program requirements, checks availability of peripherals and memory and determines whether the program should start immediately or be queued awaiting some facility. Queued programs are r~checked whenever a previous program com-

Simulation can be applied to any part of the system depending on need. It must be used with caution, however, since the results are only as good as the model. 4.2 OPERATING SYSTEM OR SUPERVISORY CONTROL (Multiprogrammed System) Control of a large flexible system is provided by a Supervisory Control program or Operating System which resides permanently in a protected area of memory. Initially, magnetic

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CONTROLS 1/0 OPERATIONS MONITORS 1/0 RE-RUNS TAPE ERRORS. ASSIGNS CHANNELS AND ACCESS ARMS ON DISKS.

Figure 4.2.1. Hierachy of Control.

From the collection of the Computer History Museum (www.computerhistory.org)

118

PROCEEDINGS-FALL JOINT COMPUTER, CONFERENCE, 1963 .."

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