Grid synchronization technique without using trigonometric functions for accurate estimation of fundamental voltage parameters Md. Shamim Reza, Mihai Ciobotaru, and Vassilios G. Agelidis Australian Energy Research Institute and School of Electrical Engineering and Telecommunications The University of New South Wales, Kensington, Sydney, NSW 2052, Australia E-mail:
[email protected],
[email protected],
[email protected]
Abstract-This paper proposes a single-phase grid voltage synchronization technique combining a quadrature signal generator and a frequency estimator to avoid the use of the computationally demanding trigonometric functions of a conventional phase-locked loop. The quadrature signal generator consists of an anticonjugate decomposition process and a cascaded delayed signal cancellation (ACDSC) strategy. The technique can provide accurate estimation of the fundamental voltage amplitude, frequency and phase angle, and can also reject the negative effects caused by the presence of DC offset and harmonics. When compared with a phase-locked loop based on the ACDSC, the proposed technique avoids the evaluation of the trigonometric functions, removes the phase loop, thus does not require tuning of loop filter, and also provides comparable estimation accuracy and dynamics. Simulation and experimental results are provided to verify the performance of the proposed technique.
1
INTRODUCTION
The interface system of the distributed generation (DG) requires proper synchronization at the point of common coupling (PCC) [1]. The grid voltage phase angle is usually used for this purpose. On the other hand, a high penetration of DGs based on renewable resources, such as photovoltaic (PV) and wind energy, may cause fluctuation of the fundamental voltage amplitude and frequency, which may affect the safety and stability conditions of the grid [2, 3]. For this reason, many international grid codes have been introduced to regulate the characteristics of the DG [4, 5]. For example, German grid code defines that the reactive current supplied by a PV system has to be controlled when the magnitude of a non-faultyphase voltage rises 10% from its nominal value [5]. In addition, the PV system has to be disconnected from the grid when the frequency exceeds the range of 47.5-51.5 Hz [5]. On the other hand, the IEC standard 61727 also defines that the PV system has to be disconnected when the grid frequency exceeds ±1 Hz of the rated value [6]. Thus, the grid voltage fundamental parameters have to be monitored at the PCC of the DG in order to achieve a reliable, safe and efficient operation of the grid, and also to fulfill the grid codes requirements.
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Many digital signal processing techniques, such as discrete Fourier Transform (DFT) [7-10], Prony’s method (PM) [1113], least-squares (LS) [14, 15], Kalman filter (KF) [16-20], frequency-locked loop (FLL) [21, 22] and phase-locked loop (PLL) [23-25], have been reported in the technical literature for estimating the single-phase grid voltage fundamental amplitude, frequency and phase angle under generic grid conditions. The DFT is the basic technique for spectral analysis, however, necessitates periodic waveform [7-10]. The computational effort of the DFT can be reduced by using it recursively, but is affected by accumulation errors [10]. This shortcoming of the recursive DFT can be overcome by using additional auxiliary control methods, such as careful coding [26] or several other algorithms [10] at the cost of additional complexity and computational burden. The PM assumes a large value of the number of modal components present in the grid voltage under distorted conditions, thus requires rooting of a high-order polynomial and is computationally demanding for real-time implementation [11-13]. The LS technique needs modelling of harmonics present in the grid voltage, thus making the technique computationally demanding, and may also suffer from matrix singularities [14, 15]. The performance and stability of the KF depend on the tuning parameters [16-19]. The KF also requires high computational effort for implementation on a digital signal processor [20]. A quadrature signal generator (QSG) based on a second-order generalized integrator (SOGI) can be used to implement the FLL (SOGI-FLL) [21, 22]. The SOGI-FLL is relatively simple and computationally efficient technique for single-phase grid voltage fundamental parameters estimation. However, lower order harmonics may introduce distortions into the estimated parameters [21, 22]. However, the QSG-SOGI can be tuned at a low bandwidth to reject the negative effects caused by lower order harmonics at the expense of slower dynamics. Multiple QSG-SOGIs and a FLL can also be connected in parallel to reject harmonics effects at the expense of a high computational effort [22]. The PLL is a commonly used technique for grid synchronization applications [23-25]. A virtual orthogonal voltage system is required to implement a single-phase PLL and there is less information in single-phase systems when compared with three-phase ones [25]. The presence of DC offset and harmonics may also affect the performance of the PLL [27-29]. An optimal tuning is necessary to obtain a trade-off between good dynamics and estimation accuracy under distorted grid conditions. A pre-filter or in-loop filter can also be used to reject the negative effects caused by grid disturbances at the cost of slower dynamics [29, 30]. A cascaded delayed signal cancellation (CDSC) strategy can be combined with an anticonjugate decomposition (ACD) process (ACDSC) and a PLL to provide accurate estimation of the single-phase grid voltage fundamental parameters [31, 32]. However, the Park Transform based ACDSC-PLL requires evaluation of trigonometric functions which may increase the computational burden for implementing on real-time digital signal processors [33, 34]. A look-up table can be used to obtain the value of the trigonometric functions in real-time [35]. However, the accuracy depends on the number of elements present in the look-up table. The accuracy can be increased by including a large number of elements in the look-up table at the cost of a large size memory [35]. In addition, the ACDSCPLL requires proper tuning of proportional and integral (PI) controllers which are used as phase loop filter [32].
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The objective of this paper is to propose a single-phase grid voltage synchronization technique combining the ACDSC and a frequency estimator (ACDSC-FE). It does not require evaluation of the computationally demanding trigonometric functions for real-time implementations on a low cost digital signal processor. It can provide accurate estimation of the fundamental voltage amplitude, frequency and phase angle, and can also reject the negative effects caused by DC offset and harmonics. When compared with the ACDSC-PLL [31], the ACDSC-FE technique avoids the handling of trigonometric functions, removes the phase loop, thus does not require tuning of the loop filter (PI controllers), and also provides similar estimation accuracy and dynamics. However, both techniques require the feedback of the estimated fundamental frequency. The preliminary simulation results of the proposed ACDSC-FE technique for fundamental voltage amplitude and frequency estimation under limited operating conditions of the grid voltage were first introduced in [36]. On the other hand, based on standard requirements under a wide range variation of the fundamental frequency [37], both simulation and experimental performance comparison between the ACDSC-FE and ACDSC-PLL techniques are reported in this paper. An approximation of the arctangent function is also documented to obtain the phase angle from the generated fundamental voltage orthogonal waveforms. The rest of the paper is organized as follows: the proposed ACDSC-FE technique is presented in Section 2. Section 3 contains the simulation performance comparison between the ACDSC-FE and ACDSC-PLL techniques. The real-time experimental performances of the ACDSC-FE and ACDSC-PLL techniques are reported in Section 4. Finally, the conclusions are summarized in Section 5.
2
PROPOSED ACDSC-FE TECHNIQUE
The block diagram of the proposed ACDSC-FE technique for single-phase grid voltage fundamental amplitude, frequency and phase angle estimation is shown in Fig. 1, where v is the grid voltage, n is the sampling instant, N is the number of voltage samples in one fundamental period, fs is the sampling frequency, v1' is the estimated in-phase fundamental voltage component, qv1' is the estimated in-quadrature fundamental voltage component, Aˆ1 is the estimated fundamental voltage amplitude, fˆ is the estimated fundamental frequency, and ˆ1 is the estimated instantaneous phase angle. As it can be seen,
v n
N Anticonjugate DecompositionCascaded Delayed Signal Cancellation
f s /(.)
qv1' n v n ' 1
Quadrature Signal Generator
Frequency Estimator
fˆ n
v1' 2 n qv1' 2 n
Aˆ1 n
Arctangent Approximation Function
ˆ1 n
Fig. 1 Block diagram of the ACDSC-FE technique for single-phase grid voltage fundamental amplitude, frequency and phase angle estimation. 3 / 17
a QSG based on the ACDSC (QSG-ACDSC) generates the fundamental voltage orthogonal waveforms, which are used to estimate the fundamental voltage amplitude, frequency and phase angle. An approximation of the arctangent function is used to obtain the phase angle. The fundamental frequency is estimated by using a FE. The estimated fundamental frequency is also used to update the value of N required for the CDSC strategy.
2.1
Fundamental voltage orthogonal waveforms estimation
The ACDSC technique for the generation of the fundamental voltage orthogonal waveforms of a single-phase voltage system was described elaborately in [31] and is briefly presented in this subsection. Based on the ACD process, the singlephase voltage system can be decomposed into two space vectors, the positive-sequence and negative-sequence. Both vectors are anticonjugate since they are symmetrical about the imaginary axis. The input voltage is in-phase with the positivesequence component. The amplitudes of both vectors are half of the input voltage amplitude. The vectorial sum of both positive-sequence and negative-sequence components provides zero as a real part and original input voltage as an imaginary part. The anitconjugate pair can also be obtained back by decomposing the vectorial sum, and can be used to estimate the input voltage amplitude and phase angle. To reject the negative effects caused by DC offset and harmonics, the CDSC strategy can be integrated with the ACD process [31, 32, 38-41]. Therefore, the combination of the ACD and CDSC can produce fundamental voltage orthogonal waveforms from a single-phase grid voltage distorted by DC offset and harmonics [31], thus is named as the QSG-ACDSC in this paper. The block diagram of the QSG-ACDSC is shown in Fig 2 [31]. As it can be seen, based on the ACD process for singlephase voltage system, the inputs of the CDSC are used as v 0 and v v . The CDSC is formed by cascading multiple delayed signal cancellation (DSC) operators in series (DSCp, DSCq, DSCr, and so on, are cascaded to obtain CDSCp,q,r,…). The subscript q of DSCq indicates that the input voltages are delayed by T/q and processed to reject the negative effects caused by DC offset and harmonics, where q is a positive constant integer and called delay factor, and T is the fundamental 0 v
0
~
CDSCp,q,r,...
∕∕
v v
∕∕
2
qv1' ' v1
∕∕
N
CDSCp,q,r,... ∕∕
∕∕
DSCp
DSCq
∕∕
DSCr
∕∕
∕∕
∕∕
N v i v i
DSCq ∕∕
∕∕
∕∕
Cq Sq -S C q q Delay N /q
∕∕ 0.5
∕∕
= ∕∕
N
Fig. 2 Structure of QSG-ACDSC [31].
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v' o ' v o
period [31, 32, 38-41]. The implementation of the DSCq operator is also shown in Fig. 2. The relation between the input and output voltages of the operator DSCq can be expressed by [31] v' o n v i n Cq ' 0.5 S v n o v i n q
Sq v i n N /q Cq v i n N /q
(1)
where v' o and v' o are the output voltages, v i and v i are the input voltages of the operator DSCq, and Cq=cos(-2π/q) and Sq=sin(-2π/q). Both Cq and Sq are constants and can be estimated offline. It can be seen from (1) that the input voltages are delayed by N/q samples and multiplied with a constant matrix and then added with the input voltages to get the outputs of the operator DSCq. The value of N/q can be integer or non-integer i.e. L≤N/q
