ISSN 2322-0929 Vol.04, Issue.01, January-2016, Pages:0099-0103
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Hardware Implementation of Configurable Booth Multiplier on FPGA KISHORE SHINDE1, DR. A. K. KURESHI2 1
PG Scholar, Dept of E&TC, VACOE, Ahmednagar, Maharashtra, India, E-mail:
[email protected]. 2 Principal, Dept of E&TC, VACOE, Ahmednagar, Maharashtra, India.
Abstract: This paper presents the design and implementation of modified configurable Booth encoding multiplier for both signed and unsigned 32 bit numbers multiplication & the floating point arithmetic. Multiplication operation is a mostly used in many scientific and signal processing applications. An area efficient implementation of a high performance configurable Radix-4 Booth multiplier with 3:2 compressors is designed & implemented on FPGA. Thus it provides a flexible arithmetic capacity and a better output precision and high speed, minimum area consumption. The design also dynamically disables the switching operation of the non effective input ranges. Thus the ineffective circuits can be efficiently deactivated, thereby reducing power consumption and increasing the speed of operation. Thus the proposed design of multiplier outperforms the conventional multiplier in terms of area and speed efficiencies. The proposed design have been implemented on FPGA Spartan 6 XC6SLX9 platform providing with a comparison of resources utilized and execution speeds. Keywords: Booth Encoding Multiplier, Partial Products Generation, Signed-Unsigned Multiplication. I. INTRODUCTION In digital computing systems multiplication is an essential arithmetic operation. The multiplication operation consists of simply producing partial products and then adding these partial products the final product is obtained. Thus the speed of the multiplier depends on the number of partial product and the speed of the adder. As the multipliers are having a significant impact on the performance of the entire system, many high performance algorithms and architectures have been proposed [5]. Hence multiplier is an important element of the digital signal processing such as convolution and filtering operations. The high speed Booth multipliers and pipelined Booth multipliers are used for digital signal processing (DSP) applications such as for multimedia and communication systems. FPGAs offer high performance and very high operating speeds with limited amount of logic devices and IP cores available on the system. Their applications are more commonly observed in the field of digital signal processing, communications engineering, and also in very high speed computing systems such as super computers. This work involves an efficient FPGA implementation of floating point multiplication. Our main concerns are area, speed, power efficiency and structural flexibility. The experimental results demonstrate that the proposed multiplier can provide various configurable characteristics for multimedia and DSP systems. The remainder of this paper is organized as follows: Section II deals with the literature survey and key components used in the design of Configurable Booth Multiplier. Section III gives the system description of the sub-modules required for the implementation. Section IV gives the result analysis and demonstrates the efficiency of the designed multiplier in
terms of speed, power & area utilization. Finally a concluding remark is given in Section V. II. LITERATURE SURVEY Array multiplier is an efficient layout of a combinational multiplier. Array Multiplier gives more power consumption as well as optimum number of components required, but delay for this multiplier is larger. Thus, it is a fast multiplier but hardware complexity is high [6].Wallace Tree Multiplier was developed by Wallace In the Wallace tree method, the circuit layout is not easy although the speed of the operation is high since the circuit is quite irregular. A Braun or carry save array multiplier is a simple parallel multiplier is restricted to performing multiplication of two unsigned numbers. A major disadvantages of the Braun’s multiplier is number of components required increases quadratically with the number of bits which will make the multiplier to be inefficient. A. Booth Multiplier Booth algorithm is a powerful algorithm for signed number multiplication, which treats both positive and negative numbers uniformly [2]. Since a k-bit binary number can be interpreted as k/2-digit Radix-4 number, and so on, it can deal with more than one bit of the multiplier in each cycle by using high radix multiplication [4]. The major disadvantage of the Radix-2 algorithm was that the process required n shifts and an average of n/2 additions for an n bit multiplier. But Radix 4 encoding scheme reduces the number of partial product generation. This algorithm scans strings of three bits as follows:
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KISHORE SHINDE, DR. A. K. KURESHI Extend the sign bit 1 position if necessary to ensure that n is even. Append a 0 to the right of the LSB of the multiplier. According to the value of each vector, each Partial Products will be 0, +y, -y, +2y or -2y. It is possible to reduce the number of partial products by half, by using the technique of radix 4 Booth recoding. The basic idea is that, instead of shifting and adding for every column of the multiplier term and multiplying by 1 or 0, we only take every second column, and multiply by ±1, ±2, or 0, to obtain the same results.
system, which divides total system into several small cascade stages and adds some register to synchronize outputs of each stages. The results of the multiplication will appear in the A and Q registers. A and Q-1are initialized to 0. As control logic scans the bits of the multiplier one at a time. Now, as each bit examined, the bit to its right is also examined.
TABLE I: Radix 4 Encoding Technique
Radix-4 booth encoder performs the process of encoding the multiplicand based on multiplier bits. It will compare 3 bits at a time with overlapping technique. Grouping starts from the LSB, and the first block only uses two bits of the multiplier and assumes a zero for the third bit. III. SYSTEM DESCRIPTION Multiplication involves the generation of partial product, one of the each digit in the multiplier. These partial products are then summed to produce the final product [3].The partial products are easily defined. When the multiplier bit is 0, the partial product is 0. When the multiplier is 1, the partial product is the multiplicand. The total product is produced by summi.ng the partial products. For this operation, each successive partial product is shifted one position to the left relative to the preceding partial product. The multiplication of two n-bit binary integers, results in a product of upto 2^n bits in length. A. Booth Architecture The operation of the multiplier is as follows: Control logic reads the bits of the multiplier one at a time. If Qo (LSB)is 1 then the multiplicand is added to the A register with the result is stored in the A register, with the C bit used for overflow. Then all the bits of the C,A & Q registers are shifted to right by one bit. If Qo is 0 then no addition is performed, just the shift operation. This process is repeated for each bit of the original multiplier. The resulting 2n bits product is contained in the A & Q registers. Pipelining is a concept to reduce the delay in the critical path as shown in Fig.1. It is done by adding registers or latches in the data path .By eliminating the delay in the critical path the speed and throughput is increased. Pipelining block is constructed using registers. Registers consists of latches i.e flip flops. Pipelining is a popular technique to increase throughput of a high speed
Fig.1. Architecture of proposed booth multiplier. B. Flow Chart of Proposed Booth Multiplier The multiplier and multiplicand are placed in the M and Q resisters, respectively. There is also a 1-bit register placed logically to the right of the least significant bit (Qo) of the Q register and designated as Q -1. If the two bits are the same (1-1 or 0-0), then all of the bits of the A, Q and Q-1 registers are shifted to the right 1 bit. If the two bits differ, then the multiplicand is added to or subtracted from the A register depending on whether the two bits are 0-1 or 1-0. Following the addition or subtraction the right shift occurs as shown in Fig.2. In either case, the right shift is such that the leftmost bit of A not only is shifted but also remains in least signific and bit (LSB).
International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.01, January-2016, Pages: 0099-0103
Hardware Implementation of Configurable Booth Multiplier on FPGA Algorithm for Floating Point: Multiplication if the operand is 0, 0 is reported as result. Adding the exponent. If the exponent are stored in biased form, the exponent sum would have doubled the bias. Thus bias value must be substracted from the sum. Multiply the significands taking into accounts their signs. After the product is calculated, the result is then normalized & rounded. IV. RESULTS AND DISCUSSION For experimentation results Xilinx Spartan 6 FPGA target device XC6SLX9 is used. A Xilinx ISE 14.7 software tool used for synthesis & implementation of logic, also XPower Analyzer for power estimation. VHDL code is written to generate the required hardware and to produce the partial product for proposed booth multiplier. After the successful compilation the RTL view generated is shown in Fig.3.
Fig. 2. Flow chart of proposed booth multiplier. It is known as an arithmetic shift because it preserves the sign bit. C. Floating Point Representation The most important floating-point representation is defined in IEEE Standard 754 [IEEE 85]. This standard was developed to facilitate the portability of program from one processor to another. The format allows the representation of numbers with fractional component as well [7].The left most bit stores the sign of the number (0=positive & 1=negative). The exponent value is stored in next 8 bits. The representation is known as biased representation. A fixed value called the bias is substracted from the field to get the true exponent value. With the bias of 127, the exponent values are in the range of -127 to 128.An advantage of biased representation is that non negative floating point numbers can be treated as integers. The final portion of word (23 bits)is the significand also called as mantissa.
Fig.3.RTL view of 32×32 signed or unsigned multiplier. The simulation result of signed-unsigned numbers is shown below. When MSB bit a[31]=b[31]=1 then that numbers are signed numbers and take2’s complement form and then the final product is obtained. Fig.4 shows the simulation result of 32-bit unsigned multiplication in decimal form.
TABLE II: 32 bit Floating Point Format
Fig.4.Simulation of 32 32 bit multiplication. International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.01, January-2016, Pages: 0099-0103
KISHORE SHINDE, DR. A. K. KURESHI A. Device Utilization An configurable Booth multiplier is implemented using VHDL utilize 75 number of slice register, 278 slice LUTs, 74 LUT FF pairs and 132 number of bonded IOB used.
C. Analysis of Proposed Multiplier Table III: Performance Comparison of Proposed Booth Multiplier
Booth multiplier is an important and greatly increase the implementation support for high speed data processing using Radix4 approach. The design gives much more improvement in power & logic area consumption compared to conventional architecture. The designs of Radix-4 Booth multiplier for signed, unsigned and floating point numbers have been simulated using Xilinx ISE 14.7 tool and implemented on Spartan 6 XC6SLX9 FPGA in CSG324 package. In the end we conclude that proposed radix 4 booth multiplier works the best.
Fig.5. Area utilization of proposed booth multiplier on Spartan 6 XC6SLX9 FPGA. A maximum of 4.507 ns combinational path delay with maximum operating frequency of 180.55 MHz against cost of 0.033 watt total power consumption at 25 degree celcius junction temperature compute using XPower Analyzer tool. Thus, proposed booth multiplier design achieves much lower power consumption and reduction of area with better throughput than previous multiplier designs as shown in Fig.5. B. Power Estimation A Xilinx ISE 14.7 software tool is used for synthesis & implementation of logic, also an XPower Analyzer for power estimation as shown in Fig.6. Dynamic Power = 0.015 Watt Static Power = 0.018 Watt Total Power = 0.033 Watt
V. ACKNOWLEDGEMENT I am grateful and thankful to my project guide Dr.A.K.Kureshi, for his valuable guidance and kind cooperation to complete this project. I would also like to place on record my profound sense of gratitude to Dr.A.K. Kureshi for providing me an opportunity to undertake a project on “Hardware Implementation of Configurable Booth Multiplier on FPGA”. VI. REFRENCES [1] D. JackulineMoni,P. Eben Sophia, ”Design of Low Power and High Speed Configurable Booth Multiplier”, in proc. IEEE 978-1-4244-8679-3/11,2011. [2] B.NagaVenkata Satya Durga Jahnavi, Shivani Mupparaju, Dr.LPadmasree, ”Design,Comparison and Implementation of Multipliers on FPGA”,in proc. IJETR,ISSN: 2321-0869, Volume-1, Issue-7, September 2013. [3] Wai-Leong Pang, Kah-Yoong Chan, Sew-Kin Wong, Choon Multiplier for VLSI Designer’s Library”, in proc. Wseas Transactions on Systems,E-ISSN: 2224-2678,Issue 12, Volume 12, December 2013. [4] Keshaveni. N, “High Speed Area Efficient 32 Bit Wallace Tree Multiplier”, in proc. International Journal of Computer Applications (0975 – 8887) Volume 124 – No.13, August 2015. [5] Shweta S. Khobragade, Swapnali P. Karmore, “Review on: Low Power VLSI Design of Modified Booth Multiplier”, in proc. International Journal of Engineering and Advanced Technology (IJEAT),ISSN: 2249 – 8958, Volume-2, Issue-5, June 2013. [6]NarsampalliBhargavi, Ms. Shatabdi Nandi, D. Devi Lavanya, ”Design and Performance Analysis of Multiplier using Wallace-Booth Algorithm”,in proc. IJSER, Volume 5, Issue 8,ISSN 2229-5518, August2014. [7]WilliamStalling,”Computer Organization and Architecture”, 6th Edition ,Pearson Education International, U.S.A,ISBN 0-13049307-4,2003.
Fig.6. XPower Analyzer for Power Estimation. International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.01, January-2016, Pages: 0099-0103
Hardware Implementation of Configurable Booth Multiplier on FPGA [8] Fayed A and M. A. Bayoumi, “A novel architecture for low-power design of parallel multipliers,” in Proc. IEEE Comput. Soc. Annu Workshop VLSI, Apr. 2001,pp. 149–154. [9] www.xilinx.com.
International Journal of VLSI System Design and Communication Systems Volume.04, IssueNo.01, January-2016, Pages: 0099-0103
