InGaSb: single channel solution for realizing III-V CMOS
Z. Yuan*, A. Nainani1, A. Kumar, X. Guan, B. R. Bennett2, J. B. Boos2, M. G. Ancona2 and K. C. Saraswat
Stanford University, Stanford, CA 1 Applied Materials, Santa Clara, CA 2 Naval Research Lab, Washington, DC *
[email protected] charge near the interface is available to respond to the Introduction There has been an upsurge of interest in the possibility of a interface-states. The effective bandgap (Egeff) of AlInSb/GaSb stack low-power, high-performance CMOS based on III-V materials. For is calculated using TB and as seen in Fig. 7, Egeff increases such a technology to be realized, advances are needed in a number of dramatically as TGaSb is reduced, eventually approaching that of areas including: (a) comparable high performance from n- and AlInSb when TGaSb is below 6 monolayers (ML). Due to this p-channel devices for complementary logic; (b) reducing the impact confinement effect, in terms of band energies, the heterostructure of Dit; and (c) overcoming low density of states (DOS) of electrons design is close to having one single WB cap layer (AlInSb) on top of which could limit the NMOS ION. In this study, methods are the channel. Therefore, this method gives the freedom to choose the investigated that deliver improvements in these three areas (Fig. 1). Al-compound barrier layer, achieve good passivation, and suppress We chose to work on the 6.1-6.2Å lattice constant system with the interface state response at the same time. To realize this InGaSb as the channel material because of its advantages in terms of experimentally, the surface was terminated with GaSb and capped band engineering and high mobility/offsets for both electrons and with arsenic during the MBE growth. Subsequent decapping of the holes [1-2]. Despite its larger lattice constant, antimonide’s are also As was done in a monitored fashion in the ALD chamber, which found to be potentially more suitable for hetero-integration [3]. We minimizes the exposure to air and preserves the ultrathin GaSb on demonstrate electron/hole mobility > 4000/900cm2/Vs can be the surface. C-V on both n- and p- substrate show marginal achieved in a single channel material. For the first time in III-V frequency dispersions (Fig. 8a-b). Midgap Dit response as measured systems, both n- and p-channel transistors with one single channel by the conductance method on MOS capacitors is an order of magnitude lower with the heterostructure design (HR-TEM in Fig. material show comparable high on-current. 8c) compared to bulk GaSb (Fig. 9). Low subthreshold swing (SS) at Band Engineering for III-V CMOS low temperature, close to theoretical kT/q limit, on both A. Heterostructure design for CMOS To avoid complications in CMOS circuit design and n/p-MOSFETs can be observed (Fig. 10), which confirms minimal manufacturing [4,5], it is favorable to employ a single material impact of Dit with this heterostructure stack. system that enables both good NMOS and PMOS transistors. While C. Γ-L Bandstructure Engineering for Ballistic nMOSFETs One of the major concerns for III-V NMOS is the degradation of high performance InGaAs NMOS and Ge PMOS have been demonstrated, realizing InGaAs PMOS [6] and Ge NMOS [7] has ION due to low DOS and spillover of the charge from high-µ Γ- to proven to be difficult. AlGaSb/InGaSb provides an excellent low-µ L-valley at high sheet charge [10]. We study these Γ-L solution in this regard as it has a type-I band lineup that can confine bandstructure effects with TB and a ballistic transport model for both electrons and holes (Fig. 2), and high µe and µh [2]. XPS allows varying stoichiometry of InxGa1-xSb. Fig. 11 shows higher In% the valence-band offset (VBO) to be determined by comparing the increases the energy separation between the Γ- and L-valleys while valence band (VB) spectrum of InGaSb and AlGaSb using the Ga the effective mass of the Γ-valley is further reduced. As a result, high peak as a reference (Fig. 3a). Bandgaps extracted from PL In% leads to a significant loss of charge due to low DOS (Fig. 12). measurements (Fig. 3b-d) allow the conduction-band offset (CBO) At the same time, an excessive population of electrons in the to be also calculated (Fig. 2). With sufficient VBO and CBO, the L-valley degrades vinj (Fig. 13). In terms of drive current, an In% of heterostructure design can thus confine both electrons/holes. Fig. 4 20-40% seems optimal for keeping most of electrons in the Γ-valley shows a tight binding (TB) simulation of the accumulation of at relevant NS values (Fig.14) while offering a better I DSAT in electrons and holes within the stack. At sheet charge density (NS) comparison to GaSb which has the highest DOS or InSb which has relevant for MOSFET operation, 80/90% of the electron/hole can be the highest vinj. Thus InxGa1-xSb with low In% is chosen for confined in the high-mobility channel. Gated Hall measurements on experimental study. Finally, both p- and n-channel MOSFETs were fabricated with the this heterostructure (Fig. 5) show 7X/2.5X higher µe and 7X/4X higher µh at an NS of 1×1012/6×1012cm-2 for electrons and holes same heterostructure design apart from having the channel p- or n-doped respectively. Pd/Pt/Au and Au/Ni/Ge/Au metal stacks were respectively, in comparison to silicon. alloyed to form an embedded direct contact to the QW. On-current of B. Amelioration of interface state response Achieving Dit levels comparable to silicon has been proven to be 4μA/μm, 3.8μA/μm at LG=50μm (Fig. 15) were observed for PMOS challenging on III-V surfaces using conventional methods such as and NMOS respectively. The NMOS characteristic is limited by chemical cleaning, Si/Ge interfacial layer, sulfide treatment and contact and series resistance, which leaves room for further in-situ passivation. We explore band engineering as a way of improvement. This is, to our best knowledge, the first demonstration minimizing the effect of Dit. Use of a wide-bandgap (WB) material of a high mobility NMOS and PMOS in the same channel material as the capping layer is known to help improve mobility and reduce with comparable ION, (Table. 1) thereby making InGaSb an the impact of Dit. For InGaAs and InGaSb systems, alloying with Al attractive channel material for realizing complementary logic in is commonly used to provide bandoffsets that confine carriers [8] III-V’s. (for InGaAs, it also gives better offsets than InP). However, good References passivation of these alloys has been found difficult [9]. By the [1] H. Kroemer, Physica E, vol. 20, p. 196, 2004. [2] B. R. Bennett, et al., J. insertion of an ultrathin interfacial layer (e.g GaSb) on which good Cryst. Growth, vol. 312, pp. 37-40, 2009. [3] C. Merckling, et al., J. Appl. passivation is achieved, we can both reduce the Dit and its effect by Phys., vol. 109, 073719, 2011. [4] M. Yokoyama, et al., VLSI Symp., p. 60, the quantization. Fig.6 exemplifies this concept on InGaSb/AlInSb 2011. [5] D. Lin, et al., IEDM Tech. Dig., p. 327, 2009. [6] L. Xia, et al., system. Quantum confinement effect in AlInSb/GaSb/Al2O3 IEDM Tech. Dig., p.315, 2011. [7] S. Takagi, M. Takenaka, VLSI Symp., p. quantum well becomes more dominant as the thickness of the 147, 2010. [8] F. Xue, et al., Appl. Phys. Lett., vol. 99, 033507, 2011. [9] M. interfacial GaSb layer (TGaSb) scales down as in Fig. 6 (c). Thus, less Kobayashi, Appl. Phys. Lett., vol. 96, 142906, 2010. [10] S. Takagi, et al., IEEE Trans. Electron Dev., vol. 55, p. 21, 2008.
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Fig. 1: Problems in III-V high-mobility MOSFETs and corresponding solutions presented in this work.
Fig. 4: Results from TB calculations show (a) hetero-structure design can provide high NS at given gate voltage (b) most of the charge is confined in the high-mobility channel.
1.32eV
In0.2Ga0.8Sb 0.70eV 0.70eV
AlGaSb
CBO 0.32eV AlGaSb
Lack of material system to support both n- and p-channel devices Type-I heterostructure design good for both N/PMOS with InGaSb channel (Fig. 2-4) μe/ μh exceeding Si in a single channel material (Fig. 5) High Dit Suppression of Dit response by confinement effect (Fig. 6-10) Low DOS of electrons Γ-L valley band-engineering (Fig. 11-14)
VBO 0.30eV Fig. 2: InGaSb/AlGaSb used in this study forms a type-I heterostructure with sufficient CBO/VBO to confine both electrons and holes.
Fig. 3: (a) VBO is measured using UV-XPS by taking the difference between VB spectrum from the channel and the buffer. Bandgaps of (b) AlGaSb, (c) InGaSb and (d) GaAs are measured using photo-luminescence (PL) at 80K.
Fig. 6: Dit, band diagram and Fermi-level during MOSFETs operation for a) high-k/bulk GaSb; b) thick / (c) thin interfacial GaSb. Confinement effect results in fewer ρ near the interface, which suppresses the interaction b/w traps and carriers.
Fig. 5: (a) Electron and (b) hole mobility measured in In xGa1-xSb channel vs. Ns using gated Hall measurement. Electron/hole mobility is > 2.5X/4X as compared with Si universal even at high Ns.
(c) Fig. 7: Effective bandgap (Egeff) of GaSb in Al2O3/GaSb/AlInSb stack increases with decreasing GaSb thickness, approaching that of AlInSb alone when TGaSb is below a few monolayers.
Fig. 8: Well-behaved capacitance characteristics measured on both (a) p- and (b) n-channel substrates with the proposed heterostructure design. Marginal dispersion indicates minimal impact from Dit; (c) HR-TEM shows experimental implementation with 2ML of GaSb b/w Al2O3 and wide bandgap AlInSb.
Fig. 9: Comparison of conduction peaks b/w bulk GaSb and proposed heterostructure design indicates an order of magnitude reduction in Dit response.
Fig. 10: Low subtheshold swing close to theoretical kT/q limit can be obtained for (a) P/ (b) NMOS with the heterostructure design, indicating minimal impact of Dit.
Fig. 11: (a) Lowest conduction band energy in InXGa1-XSb in increasing In% calculated using TB. (b) Different factors that lead to trade-off between NS and vinj for optimal IDSAT.
Fig. 13: vinj as a function of sheet charge for different In %. The drop in vinj at high sheet charge is due to excessive L-valley population.
Fig. 12: Varying In% in InGaSb changes DOS, hence number of carrier in the Γ/L valley. High In% leads to significant loss in DOS. Two slopes correspond to Γ/L valleys respectively.
ION (μA/μm)
Fig. 14: In% of 20-40% gives the highest IDSAT at relevant VG due to highest Ns×vinj product and is chosen for experimental study.
Fig. 15: Output characteristics of (a) PMOS and (b) NMOS with metal S/D. NMOS characteristic can be further improved by engineering contact and series resistance.
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N/P
p
n
This work LG=50μm
~4 InGaSb
~3.8 InGaSb
0.9
Ref. [4] LG=50μm
~2.4 Ge
~8 InGaAs
3.3
Ref. [5] LG=1.5μm
~110 Ge
~450 InGaAs
4.1
μ @ 1012cm-2 (peak) (cm2/Vs) p
n
Gated Hall 900 4000 260 1800 Ge InGaAs 400 Ge
1300 InGaAs
Table 1: This work shows comparable N/P ION and high electron and hole mobility in the same channel material, which makes InGaSb an attractive candidate for III-V CMOS.
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