Investigation of novel symmetric and asymmetric

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Int. J. Power Electronics, Vol. 7, Nos. 3/4, 2015

Investigation of novel symmetric and asymmetric multilevel converter topology with reduced power switches Jagabar Sathik Mohd. Ali* Department of Electrical Engineering, J.J College of Engineering and Technology, Trichy 620 008, Tamil Nadu, India Email: [email protected] *Corresponding author

Ramani Kannan Department of Electrical Engineering, K.S.Rangasamy College of Technology, Tiruchengode 637 215, Tamil Nadu, India Email: [email protected] Abstract: The multilevel inverter has tremendous challenges to improve the power quality in DC/AC high power application. Multilevel inverter is drawing more attention due to modularity and robustness, especially high voltage applications. In conventional multilevel inverters require a more number of switches and complex switching circuits and size is bulky. This paper proposes a novel multilevel power converter topology with reduced power switches and gate driver circuit without affecting state-of-art necessities. This proposed topology has minimum switching and conduction losses, low voltage stress (dv/dt), low electromagnetic interference, low total harmonic distortion (THD) and better efficiency. Both symmetric and asymmetric methods are simulated using MATLAB/SIMULINK tool. Based on simulation, the prototype experimental setup has been made and results are verified. Keywords: H-Bridge inverter; multilevel converter; nearest level control modulation; reduced switches. Reference to this paper should be made as follows: Mohd. Ali, J.S. and Kannan, R. (2015) ‘Investigation of novel symmetric and asymmetric multilevel converter topology with reduced power switches’, Int. J. Power Electronics, Vol. 7, Nos. 3/4, pp.226–242. Biographical notes: Jagabar Sathik Mohd. Ali received an undergraduate degree in Electronics and Communication Engineering from Madurai Kamaraj University, Madurai, India, in 2002, and a Master’s degree in Power Electronics and drives from Anna University, Chennai, India, in 2004. He is currently working towards a PhD from the Faculty of Electrical Engineering, Anna University, India. In 2011, he joined the Department of Electrical and Electronics Engineering, J.J. College of Engineering and Technology, Tiruchirappalli, India. His major areas of interest include analysis and control of power electronic converters and renewable energy systems.

Copyright © 2015 Inderscience Enterprises Ltd.

Symmetric and asymmetric multilevel converter topology

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Ramani Kannan graduated from Bharathiar University, Coimbatore, in 2004, and post-graduated from Anna University, Chennai, in 2006. He obtained a PhD in Electrical Engineering from Anna University in 2012. Since January 2006, he has worked as an Associate Professor at the Department of EEE, K.S. Rangasamy College of Technology, Tiruchengode. He has 75 published works in international/national conferences and journals. His research interests involve power electronics, inverters, modelling of sinduction motors and optimisation techniques. He currently guides undergraduate and postgraduate students and supervises PhD scholars in Anna University. He is a member of the ISTE, IETE and IEEE and has received the CAYT award from AICTE, New Delhi. He is currently part of many editorial boards and acts as an editorin-chief of international journals and IEEE conferences.

1

Introduction

In the last few decades, many researchers are working to develop the new topologies, different modulation techniques and novel control technique to improve the performance of multilevel converters (Kouro et al., 2010; Abu-Rub et al., 2010; Kazmierkowsk et al., 2011). In general, three basic conventional multilevel converters are 1

diode clamp

2

flying capacitor

3

cascaded H-Bridge presented by Rodriguez, Lai and Peng (2002) and Lai and Peng (1996).

Depending on different applications, the conventional multilevel converters are chosen based on the following factor such as modularity, control and implementation complexity, voltage balancing and fault tolerance (Franquelo et al., 2008). These topologies are possible to generate infinite number of equal stepped voltage level as for a theoretical explanation. In practical, the number of level increases, they may require more number of power switches, clamping diode, flying capacitor and associated components, respectively. Further which may increase the installation area, the cost of the converter and complex control circuits. In order to reduce these drawbacks, different topologies are presented in literature. In Thamizharasan et al. (2013), a new topology is presented with reduced power switches. But in this topology required combined MOSFET and IGBT switches to eliminate interloping current, which may reduce the converter modularity. In Najafi and Yatim (2012), new multilevel inverter topology is introduced with minimum power switches, in this topology transformer is used in output side. In Babaei, Alilu and Laali (2014) and Nagarajan and Saravanan (2014), multilevel inverters are generating the higher number of voltage levels with minimum switches, but still switches are in higher side. In Shalchi et al. (2014), both symmetric and asymmetric topologies are proposed with a combination of both power diodes and IGBT. This method is proposed with different algorithms to select magnitude of DC source and possible numbers of voltage levels were discussed. In this topology, the large number of power diodes is presented, which may produce spikes or disturbance in output voltage. To avoid these spikes in load, R value should be higher than the L value. A combination of the conventional series and the switched capacitor inverter units is proposed by Babaei and

228

J.S. Mohd. Ali and R. Kannan

Gowgani (2014). The number of DC sources and active power IGBTs and a variety of DC source magnitude are reduced, even though this topology may require more number of capacitors. The bidirectional switches have great reverse blocking capability than unidirectional switches, and this bidirectional switch is used by Gupta and Jain (2014) and Mokhberdoran and Ajami (2014). However, these topologies increase the number of switch count and total cost of the inverter. Different configurations are presented by Babaei, Kangarlu and Mazgar (2012). This topology that does not require bidirectional switches, so the number of power switches is gradually reduced and different algorithms are proposed to select the magnitude of DC source voltages. But, one of the major disadvantages of this converter is that it requires different voltage rating of power switches for symmetric topology, which leads to produce more loss compared to conventional topologies. Different algorithms are proposed to select DC source voltage magnitudes with reduced power switches. This paper presents a new series/parallel connection of both symmetric and asymmetric multilevel inverter (MLI), which contains a minimum number of power switches with two different voltage ratings.

2

Proposed topologies

2.1 Suggested symmetric topology In this section, the overview of the basic structures of proposed topology is introduced and mathematical expressions for number of voltage level (NLevel), number of IGBT (NIGBT), peak inverse voltage (PIV) of individual switches, maximum blocking voltage (VBLOCK), and a number of DC source voltages calculation are discussed. Figure 1a shows the general basic structure of the proposed topology, which consists of n number of DC source voltages, that is separated with unidirectional controlled power switches called as voltage adder (S1,S2,S3….Sn) and also each DC source are connected with parallel switches known as subtractor (P1,P2,P3….Pn). In proposed topology, all the DC sources have equal magnitude (Vdc). Figure 1b is the basic two source adder/subtractor unit. The switches S1 and P1 are connected series/parallel to the DC source, which may increase the voltage ratings of the switches; here worth to mention the reduction of power switches. In adder/subtractor unit switches S1 and P1 turned on simultaneously, the Vdc1 and Vdc2 get short circuited, to avoid this P1 and S1 switch should be turned on alternatively. The two sources adder/subtractor circuit can be inserted in any part of the circuit. This topology is divided into two units 1

combined series/parallel switches with a DC voltage source also called as level generator unit

2

polarity changer H-Bridge unit.

Symmetric and asymmetric multilevel converter topology Figure 1

229

(a) Generalised basic structure of the proposed symmetric topology (b) basic adder/subtractor unit (see online version for colours)

The series connection of DC sources with switches is called as voltage adder and the parallel connected switch is called as voltage subtractor. Table 1 illustrates the switching pattern for the n DC sources. 1’s and 0’s representing turned on and turned off switches. The corresponding switches will be turned on to synthesized positive stepped waveform. The series/parallel unit is connected with H-Bridge, which is used to create a current path in both the directions at load terminals. Different levels are obtained by proper switching of voltage adder/subtractor switches as shown in Table 1. The proposed topology should be used isolated DC sources. In general, the isolated DC sources can be provided through a DC source voltage through renewable energy sources. The maximum output voltage (Vo, max) is sum of all the DC source voltage is as given below:

V0, max = Vdc1 + Vdc2 + Vdc3 + " + Vdcn

(1)

Vdc = Vdc1 = Vdc2 = Vdc3 " = Vdcn n

V0, max = ∑ Vdcn i −1

nth DC source voltage is Vdcn,

(2)

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Table 1

Generalised switching sequence for proposed symmetric topology

Equations (1) and (2) illustrate the output level of adder/subtractor circuit. Both the positive and negative levels are synthesized by using the H-Bridge circuit, at load (Vo, Load) synthesized stepped output voltage level will be obtained as mentioned below ⎧+Vdcn Vo ,Load = ⎨ ⎩−Vdcn

for HS1 , HS4 = 1 for HS2 , HS3 = 1

(3)

In this proposed topology, the number of output voltage levels (NLevel) and number of IGBT (NIGBT) are calculated based on number of DC source (n): N Level = 2n + 1

(4)

NIGBT vs NLevel: ⎧ N Level + 1 N IGBT = ⎨ ⎩ N Level − 1

for 3 ≤ N Level ≤ 7 for N Level > 7

(5)

NIGBT vs n: ⎧(2n + 2) N IGBT = ⎨ ⎩(2n)

for 1 ≤ n ≤ 3 for n > 4

(6)

From Equations (6) and (7), it is clear that the number of IGBT required for NLevel ≤ 7 same as presented by Nagarajan and Saravanan (2014).

2.1.1 Power stage operation In this section, nine-level symmetric multilevel inverter is discussed to understand the proposed topology as shown in Figure 2. In representing each DC source which is subtracted from each parallel switches, in this case, any two DC sources can be subtracted from the corresponding parallel switch (Nagarajan and Saravanan, 2014). The


231

maximum magnitudes of blocking voltage capability for IGBTs are Vdc in CHB symmetric configuration, but in the proposed method, the blocking voltage of Figure 2

Proposed nine-level symmetric topology

IGBT Sn and Pn is 2Vdc and remaining IGBTs are Vdc. The magnitude of each steps are calculated for nine-level inverter is explained as follows: Level 1 = Vdc + 0

(7)

Level 2 = Vdc + S1

(8)

Level 3 = Vdc + S 2

(9)

Level 4 = Vdc + S1 + S 2

(10)

Desired Vdc= Vdc + voltage adder switches (S1, S2, S3…Sn)

(11)

where P1 = Vdc and P2 = 2Vdc (i.e.) P1 will subtract the Vdc voltage and P2 will subtract 2Vdc voltage, respectively. To obtain a nine-level output voltage, the mathematical equations are expressed as (7)–(10), the general expression for NLevel is represented in (11). Each DC voltage source is subtracted with corresponding on state parallel switches (subtractor switch). From Table 2, the corresponding switches will be on and off to produce the stepped waveform. The theoretical explanation for the table is: the adder/subtractor unit is generating positive polarity output voltage based on the switching pattern presented in Table 2, which can produce possible five positive output levels from zero to a maximum value of 4Vdc. The H-Bridge unit (polarity changer) is serially

232


connected with adder/subtractor unit (level generator) to create a current path to load in both positive (HS1 and HS4) and negative (HS2 and HS3) direction (−4Vdc to +4Vdc). Table 2

Various switching patterns for proposed nine-level inverter Switch states

P1

P2

S1

S2

HS1

HS2

HS3

HS4

Voltage level at Vo,Load

1

1

0

0

1

0

0

1

+Vdc4

0

1

1

0

1

0

0

1

+Vdc4+Vdc1

1

0

0

1

1

0

0

1

+Vdc2+Vdc3+Vdc4

0

0

1

1

1

0

0

1

+Vdc1+ Vdc2+ Vdc3+ Vdc4

0

1

0

0

1

1

0

0

0

1

1

0

0

0

1

1

0

−Vdc4

0

1

1

0

0

1

1

0

− (Vdc4+Vdc1)

1

0

0

1

0

1

1

0

− (Vdc2+Vdc3+Vdc4)

0

0

1

1

0

1

1

0

− (Vdc1+ Vdc2+ Vdc3+ Vdc4)

2.1.2 Peak inverse voltage calculation (VPIV) To choose appropriate IGBT, the individual switch peak inverse voltages should be taken into account. Voltage stress in other words, the standing voltage of switches can be calculated by using the following expression:

VPIV

for Sn and Pn ⎧2Vdc ⎪ for remaining all switches in level ⎪⎪ Vdc =⎨ generator ⎪ NS ⎪∑ V for H-Bridge switches ⎪⎩ i =1 dcn

(12)

2.1.3 Blocking voltage capability (VBLOCK) One of the most important parameters of total cost of multilevel inverter is to determine the maximum blocking voltage capability of power switches. As shown in Figure 1b, the switches S1 and P1 should be able to withstand for a maximum voltage of Vdc1 + Vdc2, the maximum blocking voltage for individual switches in level generator part is Vdc except the two source adder/subtractor unit. The following method is used to calculate the maximum blocking voltage of the switches. As shown in Figure 1a, the blocking voltage of S1, S2, S3….Sn P1, P2…….. Pn are calculated as follows: Vdc1 = Vdc2 = Vdc3 ...... = Vdcn , in symmetric method all the DC source voltages are considered as equal value. Vdc = S1 = S 2 = S3 " S n −1 = P1 " Pn −1

(13)

VB1 = S1 + S 2 + S3 " Sn − 1 + P1 + " Pn −1

(14)

S n = Pn = 2 × Vdc

(15)

Symmetric and asymmetric multilevel converter topology VB2 = Sn + Pn

233 (16)

H S1 = H S 2 = H S 3 = H S 4 = 4 × N s VBH = H S1 + H S 2 + H S 3 + H S 4

(17)

VBLOCK = VB1 + VB 2 + VBH

(18)

VBLOCK = (6n − 2)Vdc

(19)

where, VB1, VB2, VBH and VBLOCK are maximum blocking voltage of Vdc switches, 2Vdc switches, H-Bridge switches and total blocking voltage of inverter, respectively. The determination of maximum blocking voltage for a proposed multilevel inverter is expressed in (19).

2.2 Suggested asymmetric topology In order to obtain more number of voltage level, the asymmetric method is proposed. The different magnitude of DC source voltage (unequal) is used to increase the number of output voltage level with reduced power switches. In asymmetric method, various voltage rating switches are required, which normally increases the cost of the inverter. Mathematical expression of number of voltage level (Nlevel), number of IGBT (NIGBT), variety of DC source (NVARIETY), peak inverse voltage (PIV) of individual switches and maximum blocking voltage capability (VBLOCK) of asymmetric topology is derived and also two different suitable configurations for asymmetric topology are discussed. Figure 3 shows the overview structure of the proposed asymmetric topology. The different level is achieved by proper switching of the IGBT. In this topology, different magnitudes of DC source voltages are used to provide a higher number of steps voltage with minimum number of switches. Figure 3

Generalised basic structure of the proposed asymmetric topology (see online version for colours)

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Level generator output produces positive stepped waveform to obtain both polarity synthesized stepped waveform is produced by H-Bridge circuits (polarity changer), the following equation explains the output voltage at VLoad. ⎧+Vdcn Vo ,Load = ⎨ ⎩−Vdcn

for H S1 , H S4 = 1 for H S2 , H S3 = 1

(20)

For asymmetric multilevel inverter, two different methods to determine magnitude of DC source voltage are shown in Table 3. Table 3

3

Various algorithm to determine magnitude of DC source

Comparison with other topologies

The comparison of the proposed topology with other symmetric topologies is explained in literatures. The proposed topology required minimum number of switches for different output voltage level as shown in Figure 4a. Figure 4

(a) Comparison of NSOURCE vs. NSWITCH symmetric topology and (b) comparison NVARIETY vs NLevel for asymmetric topology (see online version for colours)

The proposed asymmetric multilevel inverter uses a lower number of IGBT than (Babaei, Dhqan and Sabhi, 2013). The CHB asymmetric MLI and (Babaei, Kangarlu


235

and Mazgar, 2012) use 16 and 12 IGBTs for 31 Level with four varieties of DC sources. For instance, but in this case uses 12 IGBTs with three varieties of DC sources for 31 Level. Figure 4b shows the variety of DC source for different voltage levels and compared with Shalchi et al. (2014), Gupta and Jain (2014) and Babaei, Dhqan and Sabhi (2013). The total power loss proposed topology is compared with conventional CHB multilevel inverter is shown in Figure 5. In this, the proposed topology has low power loss due to less number of power switches. Figure 5

NLevel vs TLoss p.u (see online version for colours)

In proposed topologies, the number of devices in the current path is lower than the conventional topologies, which may minimise the power losses. The cost of a single switch with different voltage ratings are presented by Gupta and Jain (2014) and at www.galco.com (Galco Industrial Electronics, Inc). In Table 4, the cost for both Vdc and 2Vdc switch voltage ratings is presented with same current ratings, respectively. Calculation of the total cost of the inverter is as follows: Total cost of switches = Number of switches × Cost of the single switch Table 4

Costs of IGBTS for different voltage ratings

*

as on 07/05/2015(http://www.galco.com)

Total cost of the inverter = Number of switches in Vdc voltage ratings + Number of Switches in 2Vdc voltage ratings + sum of DC voltage source switches voltage ratings (H-Bridge switches) + OC Total cost of the inverter =N1ΔC1 + N 2 ΔC2 + N H ΔCH + NSOURCE + N VARIETY + OC (21)

where N1, N2 and NH are a number of switches with maximum blocking voltages of Vdc, 2Vdc and sum of DC voltage source switch voltage ratings (H-Bridge switches), respectively, ΔC1 , ΔC2 , ΔCH and OC are cost of switches for voltage ratings of Vdc, 2Vdc,

236


H-Bridge switches and other components, respectively. NSOURCE and NVARIETY is the number of DC source and variety of DC source magnitude required for the inverter. The maximum blocking voltage of the proposed MLI is equal to Babaei (2012). In high power/voltage applications, higher voltage class of H-Bridge switches brings significantly increased cost higher than the CHB. In this study, it is worth to mention the reduction of power switches.

4

Simulation and experimental results

4.1 Simulation results To examine the performance of the proposed multilevel converter in generating a desired output voltage, the simulated output voltage and current waveforms are discussed in this section. This converter circuit diagram (Fig. 6) is modelled by MATLAB/SIMULINK to study the capability of the suggested converters. Symmetric topology output voltage, current waveforms are shown in Figure 7a and 7b, respectively. In this paper, for symmetric topology, the desired output voltage levels are obtained by, first, using nearest level control method (Perez et al., 2007). The voltage reference (Vref) is compared with the nearest possible voltage level and the appropriate switch pattern in selected. Other modulation techniques are proposed by Malek (2014), Bayoumi (2014), Maamoun et al. (2002) and Govindaraju (2013). Figure 6

Proposed nine-level symmetric topology

Symmetric and asymmetric multilevel converter topology Figure 7

237

(a) Simulated voltage output waveform (b) simulated current waveform (see online version for colours)

4.1.1 Symmetric topology This method is suitable for the high number of output voltage levels, since the operating principle is based on an approximation and not a modulation with a time average of the reference and, secondly, equal-phase (EP) method is derived from the simplest idea, to average distribute the switching angles in the range 0-π is explained by Ramani, Sathik and Sivakumar (2015). The switching angles can be calculated to eliminate the selective harmonics or reduce THD. The main switching angles are determined by the formula: 1800 N Level

αi = i

i = 1,2,3....

N Level − 1 2

(22)

α i -Switching angle of each level To examine the performance of both modulation algorithms is simulated in symmetric topology and the measured parameters are listed in Table 5. In the simulation, each DC source magnitude is 50 V and load values are R = 25 Ω and L = 50 mH, respectively. Table 5

Performance of modulation algorithm for proposed topology

Modulation technique Nearest level control Equal phase method

THD (%) R (Ω)

L (mH)

P (W)

Q (Var)

VRMS

IRMS

100 01 01

00 76 76

211.7 37 34

00 885 674

146.11 146.11 130.00

100

00

165

00

130.00

1.46 6.09 5.30

V 9.12 9.12 13.5

I 9.12 0.65 3.83

1.30

13.5

13.5

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4.1.2 Asymmetric topology For asymmetric topology, both proposed methods are simulated and the output waveform is discussed as follows. In 15-level inverter, circuit diagrams are required 04 DC source with two varieties of DC source magnitude are shown in Figure 8. In this case, an equal phase modulation algorithm is simulated. The design parameters are R = 10 Ω and L = 100 mH, the magnitude of DC source is 350 V, respectively. The asymmetric method output voltage waveforms and current waveforms are shown in Figure 9a and 9b, respectively. The efficiency of the proposed multilevel inverter is higher than other topologies because less number of power devices are in current path; number of switches is reduced and there is less power losses. Figure 8

15-level proposed asymmetric topology (Method II)

Figure 9

Simulated 15-Level output (a) voltage waveform and (b) current waveform (see online version for colours)


239

4.2 Experimental results In order to verify the performance of simulation-based results, the prototype model developed for nine-level inverter, experimental test has been conducted. The Xilinxbased system used to generate the pulse signal for power switches. The switching patterns are embedded on FPGA Spartan XE3S250E controller. In experimental verification, individual DC source magnitude is 15V (4 × 15 V = 60 V) and Load RL values 100 Ω and 100 mH are chosen, respectively. The IGBT IRF 840 100 V and 10 A are used for experimental test. The experimental prototype illustrating the interface of the power circuit module, DC sources and pulse generator is shown in Figure 10b. Figure 10 (a) Block diagram of gate driver circuit (b) hardware photograph (see online version for colours)

The first experimental study for showing the capability of the proposed multilevel converter in the generation of different voltage steps waveforms and current waveforms are shown in Figures 11 and 12. The experimental result corresponds very well with the simulation output voltage and current. Figure 11 Nine-level experimental output voltage waveform

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Figure 12 Experimental output current waveform

The output current is almost sinusoidal, the load of the multilevel inverter is almost a low-pass filter (R-L). The proposed multilevel inverter gate driver circuit block diagram for unidirectional transistor is shown in Figure 10a. In this optocoupler 6N137 is used.

5

Conclusion

A new symmetric and asymmetric multilevel inverter has been proposed, which is directed towards the minimum number of power electronics devices for higher number of voltage levels. The basic working principle of the proposed symmetric topology has been explained. The simulation studies performed for symmetric nine-level inverter are based on the proposed structure that has been tested experimentally. The comparison with other topologies was also discussed, confirming that, the required number of power electronics components and associated with gate driver circuits are low in the proposed structure. For instance, 9-level inverter based on symmetric topology uses 08 IGBTs, where the conventional CHB 16 IGBTs and other topologies (Najafi and Yatim, 2012; Nagarajan and Saravanan, 2014) uses higher number of power electronics component than proposed topology. The proposed asymmetric topology is more suitable for high voltage application with less number of power switches. Simulation and experimental results have proved the performance of the proposed topologies. For future work, the proposed multilevel inverter will be implementing in hardware prototype model to test the performance and results to be verified.


241

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