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Reliability Modeling of Electronic Systems Subjected to High Strain Rates 2 Pradeep Lall(l) , Sandeep Shantaram(l) , David Locker( ) (1) Auburn University Department of Mechanical Engineering NSF-CAVE3 Electronics Research Center Auburn, AL 36849 (2) US AMRDEC, Redstone Arsenal, Huntsville, AL 3 5 802 Tele: (334) 844-3424 E-mail: [email protected] Abstract

Electronic products are subj ected to high G-Ievels during mechanical shock and vibration_ Failure-modes include solder-joint failures, pad cratering, chip-cracking, copper trace fracture, and underfill fillet failures. The second­ level interconnects may be experience high-strain rates and accrue damage during repetitive exposure to mechanical shock. Industry migration to leadfree solders has resulted in proliferation of a wide variety of solder alloy compositions. One of the popular tin-silver-c?pper alloys is Sn3AgO .5Cu. The high strain rate propertIes of leadfree solder alloys are scarce. Typical material tests systems are not well suited for measure�ent ofh gh stra n rates typical of mechanical shock. PrevIously, hIgh stram rates techniques such as the Split Hopkinson Pressure Bar (SHPB) can be used for strain rates of 1 000 per sec. However, measurement of materials at strain rates of 1 1 00 per sec which are typical o f mechanical shoc is difficult to address. In this paper, a new test-techmque developed by the authors has been presented for The measurement of material constitutive behavior. instrument enables attammg strain rates in the neighborhood of 1 to 1 00 per sec. High �peed �ameras . operating at 300,000 fps have been used m conjunctIOn with digital image correlation for the measurement of full-field strain during the test. Constancy of cross-head velocity has been demonstrated during the test from the unloaded state to the specimen failure. Solder alloy constitutive behavior has been measured for SAC305 solder. Constitutive model has been fit to the material data. Samples have been tested at various time under thermal aging at 25°C and 1 25°C. The constitutive model has been embedded into an explicit finite element framework for the purpose of life-prediction of leadfree interconnects. Test assemblies has been fabricated and tested under JEDEC JESD22-B l l l specified condition for mechanical shock. Model predictions have been correlated with experimental data.

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1. Introduction

Electronic products are generally subj ected to high G­ loads in shock and vibration environments. The second­ level solder interconnects bear a considerable portion of the deformation load subj ected on the printed circuit board during mechanical shock and vibration and are susceptible to damage and eventual failure. Previously, eutectic or near eutectic tin-lead based solder j oints were

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widely used in the electronics industry because of their ease of solderability and long term reliability under a variety of commonly used environmental conditions. In the recent past, the electronics industry has migrated to leadfree solder alloy compositions or so called "green" products under the ROHS initiative. Tin-Silver-Copper (SnAgCu or SAC) alloys are being widely used as replacements for the standard 63 Sn-3 7Pb eutectic solder. Properties of leadfree solder alloys at strain rates typic�lIy experienced by the solder j oint during typical mechamcal shock events are scarce. Previously, constitutive material behavior of solder has been studied at high strain rates by using Split Hopkinson Pressure Bar test [Chan 2009, Siviour 2005] high strain rate impact tester [Wong 2008] dynamic Impact tester [Meier 2009]. In this paper, an impact hammer has been used in conjunction with digital image correlation and high-speed video for measurement of material constitutive behavior of leadfree SAC alloys. Previously, researchers have studied the microstructure, mechanical response and failure behavior of leadfree solder alloys when subj ected to elevated isothermal aging and/or thermal cycling [Darveaux 2005, Ding 2007, Hsuan 2007, Pang 2004, Xiao 2004] and effects of room temperature aging on lead-free solder alloys properties [Chuang 2002, Coyle 2000, Darveaux 2005, Lee 2002, Pang 2004, Tsui 2002, Zhang 2009] at low strain rate events «1 per sec) . In the past, Digital Image Correlation (DIC) has been used in the electronic industry for various applications. DIC has b�en use to measure full field displacement and deformation gradIent in electronic assemblies subj ected to drop and shock [Lall 2007b , 2008a,b , 2009, 20 1 Oa,b , Miller 2007, Park 2007a,b , 2008], damping ratio on the surface of the b�ard [Peterson 2008] examination of velocity, rotation, bending on portable products subj ected to impact test [Scheijgrond 2005], stresses in solder interconnects of BGA packages under thermal loading [Bieler 2006, Raj endra 2002, Sun 2006, Xu 2006, Yogel 200 1 , Zhang 2005, Zhou 200 1]. Previously, prediction of transient dynamics has been investigated using equivalent layer models [Gu 2005], smeared property models [Lall 2004, 2005], Conventional shell with Timoshenko-beam Element Model and the Continuum Shell with Timoshenko-Beam Element Model [Lall 2006a,b , 2007a-d, 2008a-d], implicit global models [Irving2004, Pitaressi 2004], and global-local sub-models [Tee 2003 ,Wong 2005, Zhu 200 1 , 2003 , 2004]. Explicit sub models [LaII

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2012 13th international Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2012

2009, 20 1 0]. However, the high strain rate properties of leadfree alloys at elevated isothermal aging and room temperature aging are scarce. In this paper, a motion-controlled impact-hammer with a slip-joint has been used for stress-strain measurement of the solder sample at strain rates in the range of 1 - 1 00 per sec. All the SAC solder specimens were prepared in-house. Effect of aging on mechanical behavior of lead free solder have been examined using tensile tester for SAC3 0S alloys that were aged for various durations (0-2 month) at room temperature (2S°C) and at elevated temperature (SO°C) . All the events were monitored using two high-speed cameras. DIC has been used to measure full field strain contour on each specimen subj ected for tensile test. FE model for high-strain rate pull test has been developed and analyzed using both dynamic explicit as well as explicit integration schemes. In addition, test assemblies has been fabricated and tested under high-G level loading condition for mechanical shock. Node based explicit sub-models and finite-element based peridynamic models for test assemblies under high G-Ievel loading have been developed incorporating material properties extracted from high strain rate tensile testing for solder interconnect life prediction. 2.

profile obtained during air cooling is shown in Figure 2. The specimen are examined by X-ray imaging to ensure that the sample is free from void or premature crack in the gage length as shown in Figure 3 and Figure 4. Cooling Profile (Air Cooling)

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2012 13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2012

Digital Image Correlation for PCB subjected to 0° drop test 3D-DIC measurement concept for a truss member as shown in Figure 12 can be expanded to entire PCB assembly subjected to drop and shock [Lall 2009, 2007", 200g d]. Full-field in-plane 2D strain contour at different time steps has been extracted (within I-ms of the drop 3� 40

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Figure 43: Velocity (V3) components along dropping directions of the board at g discrete locations using DIC technique. Peridynamics Based FEA of Electronic Package Subjected To Drop Test Simulation of the PCB assembly drop test has been carried out using peridynamic approach within FE code. Coupling of FE and peridynamic scheme is retained to reduce the computational time [Macek 2007]. Hybridization of the conventional finite elements with peridynamics trusses modeling concept for uniaxial tensile test has been expanded to simulate the PCB assembly drop and shock event. Figure 44 shows peridynamic based FE modeling concept for electronic package across the solder interconnect interface. All corner solder interconnects region has been chosen to be the peridynamic truss region since they are the weakest link in the entire PCB assembly [Lall 2005]. Peridynamic truss region has been deployed on both PCB-solder and substrate-solder side inorder to simulate multiple failure modes such as cracks between copper and solder on

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2012 13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2012

damage progression across the left bottom (LB) solder interconnect at various time steps. For the LB solder interconnect which is residing in the red hatched region damage is predicted between the time interval O.6ms to l ms and in the actual drop event red hatched region failure time is O.7ms.

package side as well as board side, bulk solder failure, cracks between PCB and solder. This model contains two set of trusses similar to peridynamics based uniaxial tensile test simulation but with the different dimension. Truss lengths modeled for peridynamic region across solder interconnect is mentioned in the Table 4. Elastic modulus (E) for different layers of truss region has been derived similar to the peridynamic E calculation implemented for truss region under uniaxial tensile test. Figure 45 shows the 3D view of the peridynamics based truss elements across the solder interconnect interface with dotted line representing truss regions. Table 4: Truss lengths for solder interconnect O.06366E-03 m

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Figure 45: 3D view of the peridynamics based truss elements across the solder interconnect interface (elements with in dotted ellipse represents peridynamic truss region) 10. FE Model Correlation with Experiment

Figure 46 shows the location of peridynamic based solder interconnects in the finite element model. All the four comers of PBGA is modeled using peridynamic truss elements. Figure 47 shows the damage initiation and

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Figure 47: Damage initiation and damage progression across left bottom (LB) solder interconnect on board side.

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2012 13th international Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2012

This shows the capability of the peridynamic FE modeling approach to predict the damage initiation and damage progression for extremely loaded structures. Mostly for all the corner solder interconnects damage initiates between solder and board side. This is expected since experimentally board has failed with in 1ms from the point of impact (i.e. before board reaching maximum compression state). 11. Summary

In this paper, detailed procedure of a simple uniaxial high-speed tensile test simulation based on peridynamic approach has been provided. Peridynamic modeling concept has been extended to simulate damage phenomena for the electronic package subjected to controlled drop test. Material properties and failure thresholds have been derived from high-strain rate uniaxial tension tests. In addition, high-speed imaging and DIC measurements on board assemblies have been used to measure the initial and boundary conditions for explicit time integration scheme. Peridynamic based FE analysis of the board assembly has been used to predict the failure location in the second-level solder interconnects. Measurements show that FE based peridynamics is a useful technique to predict damage initiation and damage progression for various test boards with ball-grid array package architecture under extreme high-G loading situations. The research presented in this paper has been supported by NSF Center for Advanced Vehicle and Extreme Environment Electronics (CAVE3 ) consortium-members. References

2.

3.

4.

5.

6.

l l . Darveaux, R., Shear Deformation of Lead Free Solder Joints, Proceedings of the

55th

Electronic Components

and Technology Conference, pp. 882-893 , 200 5 . 1 2 . D ing,

Y.,

Wang, c . , Tian,

Y.,

and L i , M., "Influence o f

Aging o n Deformation Behavior of 96. 5 Sn3 . 5Ag Lead

Acknowledgments

l.

Reliability of Pb-free Solder Joints, Proceedings of the 56th ECTC, pp. 1462- 1471, May 2006. 7. Chan, D., Nie, X., Bhate, c . , Subbarayan, G., Dutta, I., High Strain Rate Behaviour of Sn3.8AgO.7Cu Solder Alloys and Its Influence on the Fracture Location Within Solder Joints, 3rd International Conference on Energy Sustainability, ASME InterPACK, San Francisco, California, USA, pp 989-995, July 19-23, 2009. 8. Che, F.X., Luan, J.E., Baraton, X., Effect of Silver Content and Nickel Dopant on Mechanical Properties of Sn-Agbased Solders, Proceedings of the 58th Electronic Components and Technology Conference, Orlando, Florida, pp.485-490, May 27-30, 2008. 9. Chuang, C. M., Liu, T. S., Chen, L. H., Effect of Aluminum Addition on Tensile Properties of Naturally Aged Sn-9Zn Eutectic Solder, Journal of Materials Science, Vol. 37(1), pp. 191-195, 2002. l O . Coyle, R. J., Solan, P. P., Serafino, A. J., and Gahr, S. A., The Influence of Room Temperature Aging on Ball Shear Strength and Microstructure of Area Array Solder Balls, Proceedings of the 50th Electronic Components and Technology Conference, pp. 160169, 2000.

Abdul-Baqi, A., Schreurs, P. J. G., Geers, M. G. D., Fatigue damage modeling in solder interconnects using a cohesive zone approach, International Journal of Solids and Structures, Volume 42, pp. 927-942, 2005. Agwai, A., Guven, I., Madenci, E., Peridynamic Theory for Impact Damage Prediction and Propagation in Electronic Packages due to Drop, 58th Electronic Components and Technology Conference, pp. 1048-1053, Lake Beuna Vista, Florida, 2008. Amodio, D., Broggiato, G., Campana, F., Newaz, G., Digital Speckle Correlation for Strain Measurement by Image Analysis, Experimental Mechanics, Vol. 43, No. 4, pp. 396-402, 2003. Bao, Y., Dependence of ductile crack formation in tensile tests on stress triaxiality, stress and strain ratios, Enginnering Fracture Mechanics, 77, pp 505522, 2005. Bay, B., Smith, T., Fyhrie, D., Saad, M., Digital Volume Correaltion: Three-dimension Strain Mapping using X-ray Tomography, Experimental Mechanics, Vol. 39, No. 3, September 1999. Bieler, T., Jiang, H., Influence of Sn Grain Size and Orientation on the Thermomechanical Response and

-

Journal ofAlloys and Compounds, Vo. 428, pp. 274-28 5 , 2007. 13.Gu, J., Cooreman, S., et aI., Full-Field Optical Measurement For Material Parameter Identification With Inverse Methods, WIT Transactions on The Built Environment, Vol. 85, 2006. 14.Hsuan, T. C., and Lin, K. L., Effects of Aging Treatment of Mechanical Properties and Microstructure of Sn-8.5Zn-0.5Ag-0.01AI-0.1Ga Solder, Materials Science and Engineering, A 456, pp. 202-209, 2007. 15.Irving, S., Liu, Y., Free Drop Test Simulation for Portable IC Package by Implicit Transient Dynamics FEM, Proceedings of the 54th ECTC, pp. 1062 1066, 2004. 16.Kehoe, L., Lynch, P., Guenebaut, V., Measurement of Deformation and Strain in First Level C4 Interconnect and Stacked Die using Optical Digital Image Correlation, Proceedings of the 56th ECTC, pp. 18741881, May 2006. 17.Kim, H., Zhang, M., Kumar, C., Liu, p., kim, D., Xie, m., Wang, Z., Improved Drop Reliability Performance with Lead Free Solders of Low Ag Content and Their Failure Modes, Proceedings of 57th ECTC, Reno, Nevada, pp 962- 967, May 29-June 1, 2007. 18.Lall P., Shantaram S., Panchagade D., Peridynamic­ Models Using Finite Elements for Shock and Vibration Reliability of Lead-free Electronics, Proceedings of ITHERM 2010, Las Vegas, NV, June 2-5, 2010". Free Solder Alloy During In Situ Tensile Tests,"

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1 9 . Lall P., Kulkarni M., Angral A., Panchagade D., Suhling J., Digital-Image Correlation and XFEM Based Shock-Reliability Models for Leadfree and Advanced Interconnects , Electronic Components and Technology Conference, 60th Electronic Component and Technology Conference, Las Vegas, NY, pp. 9 1 1 0 5 , 20 1 0b • 20. Lall, P., Shantaram, S., Angral, A., Kulkarni, M., Explicit Submodeling and Digital Image Correaltion Based Life-Prediction of Leadfree Electronics under Shock-Impact, 5 9th Electronic Component and Technology Conference, pp 542-555, 2009. 2 1 . Lall, P., Choudhary, P., Gupte, S., Suhling, J., Health Monitoring for Damage Initiation and Progression during Mechanical Shock in Electronic Assemblies, IEEE Transactions on Components and Packaging Technologies, Vol. 3 1 , No. 1 , pp. 1 73- 1 83 , March 2008a• 22. Lall, P., Panchagade, D., Choudhary, P., Gupte, S., Suhling, J., Failure-Envelope Approach to Modeling Shock and Vibration Survivability of Electronic and MEMS Packaging, IEEE Transactions on Components and Packaging Technologies, Vol. 3 1 , No. 1 , pp. 1 041 1 3 , March 2008 b • 23 . Lall, P., Iyengar, D., Shantaram, S., S., Gupta, P., Panchagade, D., Suhling, J., KEYNOTE PRESENTA nON: Feature Extraction and Health Monitoring using Image Correlation for Survivability of Leadfree Packaging under Shock and Vibration, Proceedings of the 9th International Conference on Thermal, Mechanical, and Multi-Physics Simulation and Experiments in Micro-Electronics and Micro­ Systems (EuroSIME), Freiburg, Germany, pp. 594608, April 16- 1 8, 2008e• 24. Lall, P., Iyengar, D., Shantaram, S., Pandher, R., Panchagade, D., Suhling, J., Design Envelopes and Optical Feature Extraction Techniques for Survivability of SnAg Leadfree Packaging Architectures under Shock and Vibration, Proceedings of the 5 8th Electronic Components and Technology Conference (ECTC), Orlando, Florida, pp. 1 036- 1 047, May 27-30, 2008 d • 25 . Lall, P., Choudhary, P., Gupte, S., Suhling, J., Hofmeister, J., Statistical Pattern Recognition and Built-In Reliability Test or Feature Extraction and Health Monitoring of Electronics under Shock Loads, 57th Electronics omponents and Technology Conference, Reno, Nevada, pp. 1 1 6 1 - 1 1 78, May 30June 1, 2007a. 26. Lall, P., Gupte, S., Choudhary, P., Suhling, J., Solder­ Joint Reliability in Electronics Under Shock and Vibration using Explicit Finite Element Sub-modeling, IEEE Transactions on Electronic Packaging Manufacturing, Volume 30, No. 1 , pp. 74-83, January 2007 b . 27. Lall, P., Panchagade, D., Iyengar, D., Shantaram, S., Suhling, J., Schrier, H., High Speed Digital Image Correlation for Transient-Shock Reliability of

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Electronics, Proceedings of the 57th ECTC, Reno, Nevada, pp. 924-93 9, May 29 - June 1 , 2007e• 28. Lall, P. Panchagade, D., Liu, Y., Johnson, W., Suhling, J., Smeared Property Models for Shock­ Impact Reliability of Area-Array Packages, ASME Journal of Electronic Packaging, Volume 1 29, pp. 373-3 8 1 , December 2007d . 29. Lall, P., Choudhary, P., Gupte, S . , Health Monitoring for Damage Initiation & Progression during Mechanical Shock in Electronic Assemblies, Proceedings of the 5 6th ECTC, San Diego, California, pp.85-94, May 30-June 2, 2006a. 3 0 . Lall, P., Panchagade, D., Choudhary, P., Suhling, J., Gupte, S., Failure-Envelope Approach to Modeling Shock and Vibration Survivability of Electronic and MEMS Packaging, Proceedings of the 5 5th Electronic Components and Technology Conference, pp. 522529, 2005 . 3 1 . Lall, P., Panchagade, D., Liu, Y., Johnson, W., Suhling, J., Models for Reliability Prediction of Fine­ Pitch BGAs and CSPs in Shock and Drop-Impact, Proceedings of the 54th ECTC, pp. 1 296- 1 303, 2004. 32. Lee, S . W., Tsui, Y. K., Huang, X., and Yan, C. c . , Effects of Room Temperature Storage Time on the Shear Strength of PBGA Solder Balls, Proceedings of the 2002 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2002-395 14, pp. 1 -4, 2002. 3 3 . Lim, P. M., K. T., Seah, S . K. W., Tackling the Drop Impact Reliability of Electronic Packaging, ASME InterPAK, July 6 - 1 1 , Maui, pp. 1 - 9, 2003 . 34. Macek, R., Silling, S . , Peridynamics via finite element analysis, Finite Element in Analysis and Design 43 , pp 1 1 6 8 - 1 178, 2007. 3 5 . Meier, K., Roelling, M., Wiese, S., Wolter, K., Mechanical Solder Characterisation Under High Strain Rate Conditions,AIP Conf. Proceedings, Volume 1 300, pp 1 66- 17 5 , 20 1 0 . 3 6 . Miller, T., Schreier, H., Reu, P, High-speed DIC Data Analysis from a Shaking Camera System, Proceedings of the SEM Conference, Springfield, Massachusetts, June 4-6, 2007. 3 7 . Pandher, R., Healey, R., Reliability of Pb-Free Solder Alloys in Demanding BGA and CSP Applications, Electronic Systems, Proceedings of the 5 8th Electronic Component & Technology Conference, Orlando, Florida, pp. 20 1 8-2023 , May27th- May30th, 2008 . 3 8 . Pandher, R . , Lewis, Brian., Vangaveti, R . , Singh, B., Drop Shock Reliability of lead free Alloys - Effect of Micro- Additives, Proceedings of the 57th ECTC, Reno, Nevada, pp. 669 - 676, May 29- June 1 , 2007. 39. Pang, J. H. L., Xiong, B . S., and Low, T. H., Low Cycle Fatigue Models for Lead-Free Solders, Thin Solid Films Vol. 462-463, pp. 408-4 12, 2004. 40. Park, S., AI-Yafawi, A., Yu, D., Kwak, J., Lee, J., Goo, N., Influence of Fastening Methods on the Dynamic Response and Reliability Assessment of PCB S in Cellular Phones Under Free Drop, Proceedings of the ITherm, Intersociety Conference on

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Thermal and Thermo-mechanical Phenomena, Orlando, Florida, pp.876-882, May 28-3 1 , 2008 4 l . Park, S., Reichman, A., Kwak, J., Chung, S., Whole Field Analysis of Polymer Film, Proceedings of the SEM Conference, Springfield, Massachusetts, June 46, 2007b. 42. Park, S., Shah, C., Kwak, J., Jang, C., Pitarresi, J., Transient Dynamic Simulation and Full-Field Test Validation for A Slim-PCB of Mobile Phone under Drop Impact, Proceedings of the 5 7th ECTC, Reno, Nevada, pp. 9 1 4-923 , May 29 - June 1, 2007a. 43 . Peterson, D., Cheng, C., Karulkar, P.C., Characterization of Drop Impact Survivability of a 3D-CSP Stack Module, Proceedings of the 5 8th Electronic Component and Technology Conference, Orlando, Florida, pp. 1 648- 1 6 5 3 , May 27-30, 200 8 . 44. Pitaressi, J., Roggeman, B . , Chaparala, S., Mechanical Shock Testing and Modeling of PC Motherboards, 54th Electronics Compoents and Technology Conference, pp 1 047 - 1 054, 2004. 45. Raj endra, Pendse, D., Zhou, P., Methodology For Predicting Solder Joint Reliability In Semiconductor Packages, Microelectronics Reliability, Vol. 42, pp. 3 0 1 -305, 2002. 46. Reu, P., Miller, T., High-Speed Multi-Camera DIC for Finite Element Model Validation, Part 1 , SEM Annual Conference and Exposition on Experimental and Applied Mechanics, June 4-7, 2006 . 47. Scheijgrond,P.L.W., Shi, D.X.Q., Driel, WOO.V., Zhang,G.Q., Nijmeij er, H., Digital Image Correlation for Analyzing Poratable Electronic Products during Drop Impact Tests, 6th International Conference on Electronic Packaging Technology, pp. 1 2 1 - 1 26, Aug 30 .-Sept 2. 2005 . 48. Shi, X., Pang, H., Zhang, X., Liu, Q., Ying, M., in-Situ Micro-Digital Image Speckle Correlation Technique for Characterization of Materials 'Properties and Verification of Numerical Models, IEEE Transactions on Components and Packaging Technologies, Vo1.27, No.4, December, 2004. 49. Silling, S., A., Askari, E., A meshfree method based on the peridynamics model of solid mechanics, Comput. Struct. 83, pp I 526- 1 5 3 5 , 200 5 . 5 0 . Silling, S., Zimmermann, M., Abeyaratne, R., Deformation of Peridynamic bar, 1. Elaticity 73, pp 1 73 - 1 90, 2003 . 5 l . Silling, S., Refomulation of elasticity theory for discontinuities and Long-range forces, J. Mech. Phys. Solids 48, pp I 75-209, 2000 . 52. Siviour, C., R., Walley,S., M., Proud, W., G., Field, J., E., Mechanical properties of SnPb and Lead-free Solder at High Rates of Strain, Journal of Physics D: Applied Physics 3 8 , 4 1 3 1 -4 1 39, 2005 . 5 3 . Srinivasan, V., Radhakrishnan, S., Zhang, X., Subbarayan, G., Baughn, T., Nguyen, L., High Resolution Characterization of Materials Used In Packages through Digital Image Correlation, ASME InterPACK, July 1 7-22, 2005 .

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54. Sun, Y., Pang, J., Shi, X., Tew, J., Thermal Deformation Measurement by Digital Image Correlation Method, Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronics Systems, pp. 92 1 -927, May 2006. 55. Tee, T. Y. , Hun Shen Ng, Chwee Teck Lim, Eric Pek , Zhaowei Zhong , Board Level Drop Test and Simulation of TFBGA Packages for Telecommunication Applications, Proceedings of the 53rd ECTC, pp. 1 2 1 - 1 29, 2003 . 56. Tiwari, V . , Williams, S . , Sutton, M., McNeill, S . Application

of

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ImpactTesting, Proceedings of the

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SEM Annual

Conference and Exposition on Experimental and Applied

2005. 57. Tsui, Y. K. , Lee, S. W., and Huang, X., Experimental Investigation on the Degradation of BGA Solder Ball Shear Strength Due to Room Temperature Aging, Proceedings of the 4th International Symposium on Electronic Materials and Packaging, pp. 478-48 1 , 2002. 5 8 . Towashiraporn, P., Xie, c., Cohesive Modeling of Solder Interconnect Failure in Board Level Drop Test, Proceedings of the ITHERM, pp. 8 1 7-825 , 2006 . 59. Wong, E., H., Selvanayagam, C.,S., Seah, S.,K.,W., Driel, W.,D., Caers, J.,F . ,J.,M., Zhao, X.,J., Owens,N., Tan, L.,c., Frear, D.,R. , Leoni, M. , Lai, Y.,S., Yeh, C.,-L., "Stress-strain characteristics of tin­ based solder alloys at medium strain rate, , Materials Letters 62,pp.303 1-3034, 2008 . 60. Wong, E. H., Lim, C. T., Field, J. E., Tan, V. B . c . , Shim, V. Tiwari, V., Williams, S., Sutton, M., McNeill, S., Application of Digital Image Correlation in Impact Testing, Proceedings of the 2005 SEM Annual Conference and Exposition on Experimental and Applied Mechanics, June 7-9, 200 5 . 6 1 . Xiao, Q., Nguyen, L., and Armstrong, W. D., "Aging and Creep Behavior of Sn3 .9AgO .6Cu Solder Alloy," Proceedings of the 54th Electronic Components and Technology Conference, pp. 1 3 2 5 - 1 332, 2004. 62. Xu, L., Pang, H., Combined Thermal and Electromigration Exposure Effect on SnAgCu BGA Solder Joint Reliability, Electronic Components and Technology Conference, pp. 1 1 54- 1 1 59, May 2006 . 6 3 . Yang, W., Messle, R., Microstructure evolution of eutectic Sn-Ag solder j oints, Journal of Electronic Materr., Vol. 23, No. 8, pp. 767- 772, 1 994. 64. Yogel, D., Grosser, V., Schubert, A., Michel, B., MicroDAC Strain Measurement for Electronics Packaging Structures, Optics and Lasers in Engineering, Vol. 36, pp. 195-2 1 1 , 200 l . 6 5 . Zhang, Y., Cai, Z., Suhling, J.,c., Lall, P., Bozack, M., "Aging Effects in SAC Solder Joints," Proceedings of the SEM Annual Conference June 1 -4, 2009 Albuquerque New Mexico USA, 2009. 66. Zhang, F., Li, M., Xiong, c., Fang, F., Yi, S., Thermal Deformation Analysis of BGA Package by Digital Image Correlation Technique, Microelectronics International, Vo1.22, No. 1 , pp. 34-42, 200 5 . Mechanics, June 7-9,

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67. Zhou, P., Goodson, K. E., Sub-pixel Displacement and Deformation Gradient Measurement Using Digital ImageSpeckle Correlation (DISC), Optical Engineering, Vol. 40, No. 8, pp 1 6 1 3 - 1 620, August 200 l . 6 8 . Zhu, L., Marccinkiewicz, W., Drop Impact Reliablity Analysis of CSP Packages at Board and Product System Levels Through Modeling Approaches, Proceedings of the ITherm Conference, pp. 296 - 303, 2004.

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69. Zhu, L., Modeling Technique for Reliability Assessment of Portable Electronic Product Subj ected to Drop Impact Loads, Proceedings of the 53rd ECTC, pp. 1 00- 1 04, 2003 . 70. Zhu, L., Submodeling Technique for BGA Reliability Analysis of CSP Packaging Subj ected to an Impact Loading, InterPACK Conference Proceedings, 200 1 .

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