Deep-Submicrometer MOS Technology. Abstract-Lightly doped drain (LDD) types of MOSFET structures have been analyzed in detail in order to understand the ...
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IEEE ELECTRON DEVICE LETTERS, VOL. 11, NO. 11, NOVEMBER 1990
Limitations of LDD Types of Structures in Deep-Submicrometer MOS Technology Abstract-Lightly doped drain (LDD) types of MOSFET structures have been analyzed in detail in order to understand the issues and trade-offs in the application of these structures to deep-submicrometer technology (Lgnte5 0.35 pm) in which the minimum feature size of the technology is exploited as the total gate length of the device. Because of considerable channel doping compensation resulting from the desired graded drain profile of the N - region, larger and unacceptable chargesharing effects are encountered. The problem can be avoided if the LDD N - region is shallow and steeply profiled. However, this leads to unacceptably high hot-carrier generation rates. This major conflict in design requirements (suppression of charge sharing as well a6 reduction of hot-camer effects) results in serious limitations of LDD MOSFET’s in their applicability to deep-submicrometer technology.
I. INTRODUCTION
H
OT-CARRIER degradation is a major limitation of MOS device scaling because of the high electric fields encountered in submicrometer MOSFET’s. Many lightly doped drain (LDD) types of structures [1]-[7] have been proposed and have enjoyed varying degrees of success for 0.5- 1.5-pm design rules. However, as we show in this letter, great difficulties arise in applying the LDD types of structures to deep-submicrometer dimensions (LgateI0.35 pm) in which it is desired to use the minimum feature size for the total gate length. These difficulties arise from the competing needs of the requirement for hot-carrier suppression and the requirement for avoiding adverse charge-sharing effects. As a result, the LDD types of MOSFET’s have serious limitations in application to deep-submicrometer technology. 11. ANALYSIS In the analysis and discussion that follows, 0.35-pm MOSFET technology is used to illustrate the results and conclusions. Also, as mentioned above, it is assumed that it is desired to exploit the minimum feature size (0.35 pm) of the technology as the total physical gate length. The N- and N + drain profiles used in the analysis are based on simulations of realistic implant and diffusion conditions as opposed to artificially constructed profiles. SUPREM, PISCES, and one-dimensional (1-D) hydrodynamic simulators were used to predict the structural and electrical characteristics [8], [9]. The impact ionization rate and substrate current predictions are based on both a local-field model (PISCES) [9] and a 1-D Manuscript received March 6, 1990; revised August 12, 1990. This work was supported in part by the Semiconductor Research Corporation and the Texas Advanced Technology Program. The authors are with the Microelectronics Research Center, University of Texas, Austin, TX 78712. IEEE Log Number 9040234.
non-local-field (energy dependent) model similar to that used by Fukuma and Lui [lo]. In the design and optimization of the MOSFET structure for a given technology, all of the MOSFET requirements for performance, reliability, and manufacturability must be considered. A reasonable set of such requirements is listed below for 0.35-pm MOSFET’s: compatible with 3.3-V power supply ( V, max = 4 V), V, = 0.7 V (room temperature), AV, for L,,, = 0.35 f 0.07 pm 5 50 mV (manufacturability), AV, for V, = 0.05-4 V I50 mV (DIBL), Isuh I50-200 nA/pm for AI, or Ag, < 10% in 10 years (reliability), I,eakI1-10 pA/pm ( V , = 4 V, V, = 0 V, T = 100”C), I,,, = 0.5 mA/pm ( V , = 4 V, V, = 4 V), Vpt
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low series resistance, operating temperature range: 0- 125°C. These requirements must also be consistent with anticipated manufacturing variations. For example, we have assumed a manufacturing tolerance for the gate length of k70 nm (f3a). The choice of Isuh 5 50-200 nA/pm for adequate hot-carrier reliability is based on previously published experimental results and on existing lifetime models derived from observed degradation of drain current and transconductance [11]-[13]. The key feature of the LDD concept is the insertion of a graded, or more gently profiled, N- drain region between the N + part of the drain and the channel region. The Nregion sustains the drain voltage over a longer region and thus reduces the peak electric field which is predominantly lateral at the drain. In Fig. 1, the three general types of LDD structures are shown. Considering the first type shown in Fig. l(a) (main gate overlaps the N+ region), it can easily be shown that in order to limit the peak electric field, the lateral extent of the N- region beneath the gate r should be 2100 nm. Since the N- region is self-aligned to the gate, and since r is -70% of the N- junction depth, X j ( N - ) , then Xj(N-) must be 100-200 nm [2], [5], [14], [15]. However, this is where a major problem arises at deep-submicrometer gate lengths. Because the effective channel length is so short, the more gently graded profile of the N- region begins to substantially compensate the p-type doping concentration in the short-channel region. This reduces considerably the aver-
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IEEE ELECTRON DEVICE LETTERS, VOL. 1 1 , NO. 11, NOVEMBER 1990
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(C) Fig. 1 . Illustration of the major types of LDD MOSFET structures. (a) Gate overlaps N + region. (b) Gate does not overlap N + region. (c) Extensive gate-drain overlap.
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sidering simulation results for a 0.35-pm LDD MOSFET device of the type shown in Fig. l(a) with to, = 7 nm, Nch= 6.2 x 10‘7cm-3 (V, = 0.7 V), and different N junction depths. Our simulations show a variation in the peak doping concentration in the channel region from 1.8 X 1017 to 1.2 x lo’* cm-3 and a V, (at V, = 50 mV) variation of 800 mV for a k20% variation ( k 7 0 nm) of Lgatcfrom its nominal value of 0.35 pm for X j ( N - ) = 150 nm. AV, decreases to 65 and 35 mV for N - junction depths of 75 and 60 nm, respectively. As can be seen, with N - junction depths of 150 nm or greater, the channel doping compensation effect so intensifies the undesirable charge-sharing effects that the device behavior becomes unacceptable. Thus, in order to avoid these problems, the maximum depth of the N region should be 5 7 5 nm and steeply profiled for this 0.35-pm gate length example. Or, equivalently, for the LDD structure in Fig. l(a) the lateral extent of the N - region 60 nm, and the lateral profile needs to should not exceed be steep. With the restrictions on X j ( N - ) discussed above, simulations of the LDD structure in Fig. l(a) were performed for Lgate= 0.35 pm, t o x = 7 nm, V, = 0.7 V, and X,(N-) = 75 nm. The N- dose was varied but kept below the level which would result in band-to-band tunneling and hence gate-induced drain leakage (GIDL). For all cases, the predicted peak substrate current is excessive (at least 3 to 5 pA/pm of device width) for an N - dose range of 1-2 X 1013 cm-’. These unacceptably high values are a consequence of the N - region depth and profile restrictions discussed above. Thus, the LDD structure in Fig. l(a) can be designed to sufficiently minimize charge-sharing problems but at the expense of high substrate current, and hence unacceptable reliability. Fig. and (c) illustrates the other two general types of LDD structures, the LDD MOSFET without gate overlap of the N + drain region, and the LDD with extensive gate-drain overlap (GOLD, inverse-T, poly spacer) [6], [7]. The distinguishing feature of this latter type of structure is the extension of part of the gate over a longer N - region. In both types of structures the N - region is self-aligned to the thick or main part of the gate. Here, also, the lateral extent of the N- region beneath the thick portion of the gate is limited to 60 nm (and X j ( N - ) must be 5 75 nm) in order to avoid adverse charge-sharing effects which are amplified by doping compensation in the channel region. In the LDD structure without gate overlap of the N + region (Fig. l e ) , the length of the N - region, L N - ,and the N - implant dose must be adjusted to keep the peak electric field beneath the gate. This is necessary to avoid more rapid degradation of the drain current due to increased charge trapping that would take place at the sidewall oxide-silicon interface if the peak field were beneath the sidewall oxide [16]. Although the longer N - region provides an opportunity to drop the drain voltage over a longer distance and reduce the peak electric field, the shallow junction requirement for the N - region, together with the N - dose required to keep the peak electric field beneath the gate (1-3 x 10l3 cm-’) are such that the N region still looks essentially like a steeply profiled, shallow
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le)
(b)
Fig. 2. Illustration of the problem of channel doping compensation by the N - source/drain region for L,, s 0.35 pm. (a) Deeper junction with more gradual profile. (b) Shallow junction with steep profile.
age net p-type doping concentration in the channel region, and the magnitude of the reduction is very sensitive to gate-length variations such as encountered in manufacturing. This channel region doping compensation strongly amplifies the charge-sharing effects and causes excessive AV, versus L , , drain-induced barrier lowering (DIBL), and leakage current. This is qualitatively illustrated in Fig. 2. For a deeper N- junction, the effective, or average, p-type doping in the channel region is more sensitive to gate-length variations. The sensitivity can be reduced to acceptable levels by using a shallower junction with a correspondingly steeper doping profile. This point can be better appreciated by con-
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TASCH et al. : LIMITATIONS OF LDD STRUCTURES IN DEEP-SUBMICROMETER MOS TECHNOLOGY
N + region, just as is the case for the LDD structure in Fig. l(a). The peak substrate current was simulated for this structure (Fig. l(b)) for a range of N- doses of 1-3 x 1013 cm-2 and a range of N- region lengths ( L N - )of 55-200 nm, with the combination of the two parameters always adjusted to maintain the peak field beneath the gate. The predicted peak substrate currents are somewhat lower, but still above 1 pA/pm, a value that can be considered to be marginal at best. Furthermore, the lowest peak substrate currents were obtained only for L,-= 150-200 nm, so that the combined length of the gate (0.35 pm) and the N regions extending beyond the gate is 0.5-0.65 pm. This structural situation is undesirable wherever the intent is to exploit the minimum feature size of the technology (0.35 pm in this example) as the total gate length in order to realize minimum pitch and maximum packing density. In the LDD structure with extensive gate-drain overlap (see Fig. l(c)), the length of the gate extension is typically 0.1-0.2 pm per side. Since the longer N - region is covered by the gate, the magnitude of the N- dose can be decreased, resulting in a reduced peak field and correspondingly reduced peak substrate current. However, this improvement comes at the expense of a total gate length increase from 0.35 to 0.50-0.65 pm. This too is undesirable wherever it is desired to exploit the minimum feature size as the total gate length. If attempts are made to reduce the total gate length by reducing the length of the thick part of the gate, then the reduced Le, results in considerable channel doping compensation and consequential charge-sharing problems greater than those discussed earlier for the LDD structure in Fig. l(a). If the total gate length is decreased by reducing the thinner gate extensions, the peak electric field increases, and the predicted substrate currents increase to the high levels obtained for the other types of structures. 111. DISCUSSION AND CONCLUSIONS From the analysis presented in the preceding section, it can be seen that at deep-submicrometer dimensions (I 0.35 pm), restrictions must be placed on the N - drain region depth and profile in the LDD type of structure. Because of compensation of the p-type doping in the short-channel region by the N region profile, serious charge-sharing problems arise unless the N - drain region is shallow and steeply profiled. However, if this requirement is satisfied, the peak electric field becomes too great, and unacceptably high peak substrate currents result. While this problem can be alleviated by using the GOLD or inverse-T type of LDD structure Fig. l(c), it is at the expense of having the total gate length considerably larger than the minimum feature size of the technology used to fabricate the device. Thus, if it is desired to use the LDD type of structure in deep-submicrometer technology and also exploit the minimum feature size in the total physical gate
length in order to realize minimum pitch and maximum packing density, serious problems and limitations are encountered. This is due to a basic conflict between the requirement to minimize the N- drain region junction depth and have a steep doping profile in this region in order to avoid chargesharing problems on the one hand, and the requirement to grade, or lengthen, the N - region profile in order to suppress high electric fields and substrate current on the other hand. If, in the future, there are new reliability analysis results or substantial improvements in gate dielectric hot carrier tolerance which allow the hot-carrier reliability criterion (peak substrate current) to be relaxed, then the limitations described in this letter diminish, the amount depending on the improvements. If not, then a greater reduction of power supply voltage and/or substantially improved MOSFET structures will be needed for deep-submicrometer MOS technology. REFERENCES
P. J . Tsang, S. Ogura, W . W . Walker, J. F. Shepard, and D. L. Critchlow, “Fabrication of high-performance LDDFET’s with oxide sidewall-spacer technology,” ZEEE Trans. Electron Devices, vol. ED-29, p. 590, 1982. E. Takeda et al., “An As-P(nf-n-) double diffised drain MOSFET for VLSI’s,” ZEEE Trans. Electron Devices, vol. ED-30, p. 652, 1983. Y. Toyoshima, N. Nihira, and K. Kanzaki, “Profiled lightly doped drain (PLDD) structure for high reliable NMOS-FET’s,” in 1985 Symp. VLSZ Tech. Dig., p. 118. S. Jain, W. T. Cochran, and M. L. Chen, “Sloped-junction LDD (SJLDD) MOSFET structures for improved hot-carrier reliability,” ZEEE Electron Device Lett., vol. 9, p. 539, 1988. T. Hori, “1 /4-pm LATID (large-tilt-angle implanted drain) technology for 3.3-V operation,” in IEDM Tech. Dig., 1989, p. 777. R. Izawa, T. Kube, and E. Takeda, “Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI,” IEEE Trans. Electron Devices, vol. 35, p. 2088, 1988. I-C. Chen, C. C . Wei, and C. W. Teng, “Simple gate-to-drain overlapped MOSFET’s using poly spacers for high immunity to channel hot-electron degradation,” IEEE Electron Device Lett., vol. 11, no. 2, p. 78, 1990. PISCES ZZB, Stanford Univ., Stanford, CA, Nov. 5, 1985. TMA PISCES-2B, Version 8908, Technology Modeling Associates, Inc., Palo Alto, CA, Apr. 20, 1989. M. Fukuma and W. W. Lui, “MOSFET substrate current model including energy transport,” IEEE Electron Device Lett., vol. EDL-8, no. 5, p. 214, 1987. C. Hu et al., “Hot-electron-induced MOSFET degradation-Model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. ED-32, p. 375, 1985. T. Horiuchi, H. Mikoshiba, K. Nakamura, and K. Hamano, “A simple method to evaluate device lifetime due to hot-carrier effect under dynamic stress,” ZEEE Electron Device Lett., EDL-7, p. 337, 1986. M. C. Jeng et al., “Performance and hot-electron reliability of deep-submicron MOSFET’s,” in IEDM Tech. Dig., 1987, p. 710. M. Inuishi et al., “Optimum design of gate/n-overlapped LDD transistor,” in 1989 Symp. VLSI Tech. Dig., 1989, p. 33. R. Izawa and E. Takeda, “The impact of N - drain length and gate-drain/source overlap on submicrometer LDD devices for VLSI,” IEEE Electron Device Lett., vol. EDL-8, p. 480, 1987. F. C. Hsu and H. R . Grinolds, “Structure-enhanced MOSFET degradation due to hot-electron injection,” IEEE Electron Device Lett., vol. EDL-5, p. 71, 1984.
