Loss Balancing SVPWM for Active NPC Converters

Loss Balancing SVPWM for Active NPC Converters Xin Jing1, Jiangbiao He2, Nabeel A. O. Demerdash2 1

2

Global Vehicle Engineering Global Electrification, General Motors Corporation Torrance, CA, 90505, USA E-mail: [email protected]

Department of Electrical and Computer Engineering Marquette University Milwaukee, WI, 53233, USA E-mail: [email protected]

Abstract—This paper presents a novel loss balancing modulation method for more evenly distributing semiconductor losses in multilevel active neutral-point-clamped (ANPC) converters. The presented method is achieved by optimally utilizing the redundant switching states of space vector pulse width modulation (SVPWM) in ANPC converters. A comparison of the effect of losses distribution between the proposed loss balancing SVPWM (LB-SVPWM) method and the conventional phase-shifted PWM (PS-PWM) methods is carried out in simulation. The effectiveness of the presented LB-SVPWM method is also verified in ANPC converters based on all-SiC MOSFETs. The results show that the proposed method can distribute the device losses more evenly, especially for all-SiC based ANPC converters, which can in turn improve the output power capacity and switching frequency. In addition, with utilization of the introduced loss balancing SVPWM method in ANPC converters, 15% higher output voltage and lower harmonic distortion can be achieved compared to PS-PWM modulated ANPC converters.

I.

INTRODUCTION

Neutral-point-clamped (NPC) converters, among the most popular topologies of multilevel voltage source converters (VSCs), have been shown to provide significant advantages over conventional two-level VSCs. Such advantages are namely higher power capacity, lower harmonic distortion both in the input and output, and much smaller ⁄ and common mode voltages in converter output [1-4]. Therefore, multilevel NPC converters have been increasingly employed in both industrial medium voltage and low-voltage drives, such as ABB ACS6000 [5], Siemens Simovert MV [6], Yaskawa G7 [7], and the like. However, two major disadvantages restrict the further development of NPC multilevel converters, which include unbalanced neutral-point voltage and uneven loss distribution among the semiconductor devices. For multilevel NPC VSCs, the unbalanced neutral-point (NP) voltage can be caused by multiple reasons, such as different characteristics among the semiconductors, unequal dc-link capacitors, and unbalanced loads. Such an unbalanced NP voltage would further increase voltage stress on switching devices and incur additional harmonic distortions, which will compromise the performance of the NPC converters if such problems are not resolved [8]. Recently, this issue has been extensively studied and numerous NP voltage balancing

978-1-4799-2325-0/14/$31.00 ©2014 IEEE

strategies have been presented in the literature [8-12], and thus this aspect will not be investigated here. In fact, the uneven loss distribution between outer switches and inner switches in one leg of NPC converters is a more severe issue limiting the output power and switching frequency of NPC VSCs [13]. With such concern, a novel derivative topology of NPC converters, the so-called active NPC (ANPC) converter, was proposed to improve the loss distribution among switching devices [12-23]. The improvement of loss distribution of ANPC converters benefits from the addition of more zero switching states by employing active switches antiparallel connected with the clamping diodes of NPC converters. In this paper, a novel loss balancing method based on space vector pulse width modulation (SVPWM) is proposed to better even the loss distribution of switches in ANPC converters by taking full advantage of the redundant switching states. The objective of this method is to select the optimal zero states that can reduce the power losses on the most stressed devices. The conduction time of switching devices is modeled as a piecewise function of the modulation index and power factor, thereby allowing an online calculation to be performed. Furthermore, this paper also investigated the effectiveness of the proposed loss balancing SVPWM (LBSVPWM) for all-SiC-MOSFET based ANPC converters. The motivation is that once all-SiC devices are used in ANPC converters, then all those introduced loss-balancing method in the literature [14] may not work satisfactorily as expected, because SiC devices has much lower switching losses compared to Si counterparts, and thus their conduction loss is the main objective to be balanced. II.

THREE-LEVEL ANPC CONVERTERS

The basic topology of a three-phase three-level ANPC inverter is shown in Fig. 1, and the switching states as well as the corresponding output voltages of Phase-A are given in Table I. It can be seen that this PWM strategy has four “0” states, namely “0U2,” “0U1,” “0L1,” and “0L2”, rather than a single zero state in a conventional three-level NPC inverter. For positive state “+”, the switch T6 is turned on for balancing the voltage stress between the switches T3 and T4. Similarly, for negative state “-”, switch T5 should be turned on to force an equal voltage between the switches T1 and T2. For the “0” states, by turning on the switches T2 and T5, the phase current

281

T1

Vdc 2

C1

T5 Vdc

D5

T2

T7

D1

D2

T11 D11

T13

D7

T8

D8

T17

D17

T14

D13

D14

n T6

D6

T3

D3

T12

D12

T9

D9

T18

C2 −

Vdc 2

T4

T5

a b c

D10

States

D15

"+" "0U2" "0U1" "0L1" "0L2" "-"

D6

T2

T3

T4

T5

T6

1 0 0 1 0 0

1 1 1 0 0 0

0 0 0 1 1 1

0 0 1 0 0 1

0 1 1 0 0 1

1 0 0 1 1 0

NO.

+Vdc/2 0 0 0 0 - Vdc/2

1 2 3 4 5 6

can flow in both directions, either from the neutral point to the load or from the load to the neutral point. For this situation, the switch T4 could be in the “on” or “off” state, which yields two zero switching states “0U2” and “0U1”. In the same manner, when the switches T3 and T6 are conducting, the switch T1 may be in an “on” or “off” state, which achieves two additional zero switching states “0L1” and “0L2”. It is known that the loss distribution for an ANPC converter varies with the operation points, which are determined by two factors, namely the modulation index, , and the power factor, . The fundamental value of the threephase output phase voltage of a three-level ANPC converter could be calculated based on the modulation index and dc-link voltage. For a constant dc-link voltage, the load currents are thereby varied with that further influences the loss distribution of the switching devices. The power factor indicates the direction of the load currents and furthermore determines the conduction and switching devices that will be elaborated in the following few sections. However, it has been shown that ANPC converters have significantly uneven loss distribution when they are operating at boundary conditions of max or min , with 1 or 1 . The loss unbalance severity at other operating points between such boundaries is less critical, and thus only boundary cases are considered here.

T6

D3

T4

SWITCHING STATES FOR PHASE-A OF AN ANPC INVERTER T1

T3

D5 T2

D2

D5 T2

T5

n D3

(b)

T1

D1

T3 D6

T4

D4

(a)

V_an

T5

D2

n T6

D16

Switching Sequence

T2

T1

n

D4

T6

D1

D2

T3 D6

(c)

D3

T4

D4

Fig.2. Conduction and switching devices in the ANPC inverter for positive and negative currents. (a) Commutation between state “+” and state “OU1/OU2”. (b) Commutation between state “+” and state “OL1”. (c) Commutation between state “+” and state “OL2”.

Fig.1. Topology of a three-level three-phase ANPC inverter

TABLE I.

D5

T16

T10

D4

T15 D18

D1

T1

Commutations between state “+” and “OU1/0U2”: For positive current flow, the devices T1 and T2 will experience conduction losses, while devices D5 and T2 will produce conduction losses for the “OU1/0U2” states. Even though devices T4 and T6 are in the “on” states, they do not have any conduction losses because there is no current flow. For the commutations from “+” to “OU1/0U2”, T6 should be turned off first, T1 is turned off subsequently, and finally T5 is turned on. During such transition, T1 experiences turn-off loss. For the reverse commutation from “OU1/OU2” to “+”, T1 and D5 experience the turn-on and recovery losses, respectively. The commutations from “+” to “OU1” and “OU2” are identical except during the on state of T4 for “OU1.” However, T4 does not experience switching loss because of no current flow. Therefore, these two types of commutations are summarized as one which is shown in Fig. 2 (a). Similarly, for negative current flow, the devices D1 and D2 will generate conduction losses for the “+” state, while the devices D2 and T5 will produce conduction losses for the “OU1/OU2” states. Accordingly, for the commutations between state “+” and “OU1/OU2”, devices T5 and D1 will experience switching and recovery losses, respectively, due to the reverse current. The switching and conduction devices for both positive current and negative current are summarized in Table II and Table III, respectively.

As indicated in Table I, the transition from state “+” to state “0” has four different commutations: “+” to “OU2”, “+” to “OU1”, “+” to “OL1”, and “+” to “OL2”, and similar scenarios for the transition from state “-” to state “0”. The transitions between state “+” and all the four zero states are shown in Fig. 2 where the switching devices are marked by dotted circles. The narrow line with green and yellow colors shows the flowing path of the positive current, while the bold line with red and blue colors demonstrates the flowing path of the negative current. These commutations are briefly discussed as follows [24]:

282

TABLE II.

COMMUTATED DEVICES FOR POSITIVE CURRENT States

“+” “OU2” “OU1” “OL1” “OL2” “-” TABLE III.

Conduction Devices T1 T2 T2 D5 T2 D5 T6 D3 T6 D3 D3 D4

Switching Devices “+” to 0

“-” to 0

↕ T1 D5 T1 D5 T2 D3 T1 D3 NA

NA T2 D4 T2 D3 T6 D4 T6 D4 ↕

COMMUTATED DEVICES FOR NEGATIVE CURRENT States

“+” “OU2” “OU1” “OL1” “OL2” “-”

Conduction Devices D1 D2 T5 D2 T5 D2 T3 D6 T3 D6 T3 T4

Switching Devices “+” to 0

“-” to 0

↕ T5 D1 T5 D1 T3 D2 T3 D1 NA

NA T4 D2 T3 D2 T4 D6 T4 D6 ↕

Type-③: The zero states are also selected from Table II for this type of commutation. At 0 1, the zero states “OL1/OL2" need to be selected at first, since it helps reduce the loss on T2. Thereafter, “OU2” is utilized because it can reduce the conduction loss of D3 at a high modulation index when 1 0, and also balances the loss distribution at a low modulation index when 0 1. Fig.3. Four types of commutation of ANPC converters

The commutations given in Tables II and III can be summarized into four categories: type-①, type-②, type-③ and type-④ based on the current direction, all of which are illustrated in Fig. 3. In Fig. 3, the four types of commutation can be defined as four-quadrant operation: Type-①: positive voltage negative current; Type-②: positive voltage positive current; Type-③: negative voltage positive current; Type-④: negative voltage negative current. In order to achieve balanced loss distribution among switching devices, zero states that involve the conduction of less stressed devices are required to be identified and selected. III.

ZERO STATES SELECTION

For ANPC converters, it is known that the inner two switches in one phase leg have the largest conduction losses for a high modulation index case when the power factor is 1. Therefore, in order to reduce the conduction loss on T2, the zero states should be carefully selected for all four types of commutation. The conduction time of these four types of commutation shown in the Fig. 3 varies with the power factor. Here, the Type-② and Type-④ commutations have a longer conduction time for 0 1, and Type-① and Type-③ commutations have longer conduction time for 1 0. Type-①: This type of commutation only involves “+” and “0” states with negative current, therefore the zero states should be selected from Table III. At 0 1 , the switches T2 and T3 are the most stressed devices for a high modulation index, hence the zero states “OU2/OU1” are selected because the other zero states, “OL1” and “OL2” will involve the conduction of switch T3. Additionally, in order to balance the loss distribution at a low modulation index, the zero states “OL2/OL1” should be also utilized. Another reason why selecting “OL2/OL1” is that such zero states do not involve the conduction of the diodes D1 and D2, which experience more power loss than others at 1 0. However, the “OL1” involves the switching of the diode D2, which could make the loss distribution more unbalanced at high modulation indices. Therefore, the state “OL2” should be applied after the zero states “OU2/OU1”

Type- ④ : The zero states in Type- ④ of commutation should be selected from Table III. The zero state “OU2” is applied first due to the fact that other zero states involve the conduction and switching of T3. Moreover, for the purpose of balancing the loss at a low modulation index for 0 1 and reducing the conduction loss of D2 at a high modulation index for 1 0 , zero states “OL2/OL1” should be selected thereafter. Based on the above analysis, the switching sequences which can mitigate the most stressed devices are given in Table IV, where the corresponding conduction and switching devices are also summarized. In order to utilize all zero states, only “OU1” is applied in Type-① and Type-② commutations because “OU2” is used in Type- ③ and Type- ④ commutations. Similarly, “OL1” will replace the alternatives “OL1/OL2” for Type-③ and Type-④ commutations. To achieve a better loss distribution, the primary and secondary zero state conduction ratios should be varied with and . For simplifying the analysis, the case for 1 is considered first and the analysis for a general will be studied later. For the 1 case, there are only Type-② and Type-④ commutations. For a random , the conduction time of the states “+” and “-” should approximately be /2 for a fundamental period . The conduction time of all zero states should be 1 for . Moreover, assuming the conduction ratio of the primary zero state is for , then the conduction ratio of the secondary zero state will be 1 . Based on Table IV, a general analysis for the conduction time of all the devices in Phase-A can be given in Table V.

Type-②: For this type of commutation, the zero states should be selected from Table II. At 0 1, the zero state “OL2” should be used at first since all other zero states involve the switching or conduction of switch T2. Thereafter, for purposes of balancing the losses at low modulation index when 0 1 and reducing the conduction of D3 at high modulation index in the range of 1 0, zero states “OU2/OU1” should be selected.

283

TABLE IV.

LOSS BALANCING SEQUENCES

Primary zero state Type① Type② Type③ Type④

“+” D1 D2 “+” T1 T2 “-” D3 D4 “-” T3 T4

TABLE V.

→ T5 D1 → T1 D3 → T6 D4 → T4 D2

OU1 T5 D2 OL2 T6 D3 OL1 T6 D3 OU2 T5 D2

→ T5 D1 → T1 D3 → T6 D4 → T4 D2

Secondary zero state “+” D1 D2 “+” T1 T2 “-” D3 D4 “-” T3 T4

→ T3 D1 → T1 D5 → T2 D4 → T4 D6

OL2 T3 D6 OU1 T2 D5 OU2 T2 D5 OL1 T3 D6

→ T3 D1 → T1 D5 → T2 D4 → T4 D6

DEVICE CONDUCTION TIME IN PHASE-A FOR

“+” D1 D2 “+” T1 T2 “-” D3 D4 “-” T3 T4 1

It should be noted that even though the conduction time in Table V is not accurate enough, it is sufficient to analyze the device conduction time trends for various ratios. The conduction time of T1 and T4 should be kept unchanged when increasing or decreasing the ratio. Furthermore, the conduction time of T2, T3, D5 and D6 will be decreased when is increasing while the conduction time of T5, T6, D2 and D3 will be increased. The reduced conduction time of T2 and T3 and incremental conduction time of T5, T6, D2 and D3 are desirable for high modulation indices because of the fact that T2 and T3 are the most stressed devices while T5, T6, D2 and D3 are the less stressed devices. Similarly, reducing implies increasing conduction time of T2, T3, D5 and D6 and decreasing conduction time of T5, T6, D2 and D3, which are advantageous for low modulation indices. Therefore, based on the analysis above, it can be concluded that a large ratio should be adopted for high modulation indices and a low ratio for lower modulation indices. Hence, for various modulation indices, a better balanced loss distribution among the devices can be achieved by changing the ratio of in the application of SVPWM. IV.

LOSS BALANCING SVPWM

A. Principle of the Loss Balancing SVPWM For a three-level ANPC converter, the operation of each leg has six switching states: “+”, “OU2”, “OU1”, “OL1”, “OL2” and “-”. By taking all three phases into account, the inverter has a total of 216 possible switching states. However, only a few of them are helpful for loss balancing purposes. The space vector block diagram for a three-level ANPC inverter can be derived from an NPC converter in which all the zero states are replaced by “x.” The state “x” could be any one of the zero states “OU2,” “OU1,” “OL1,” and “OL2.” Therefore, for a three-level ANPC inverter, one can still utilize 27 switching states to express all the possible switching states, such as [1 x x]. The space vector block diagram in the (α-β) reference frame is shown in Fig. 4, which has been divided into six 60 degree sectors. Each sector consists of 4 regions (1, 2, 3 and can be 4). In any sector, the output reference voltage vector constructed from different non-zero vectors and zero vectors according to the region in which the reference voltage vector is located. The voltage vectors can be still classified into four categories, namely zero vectors (V0), small vectors (V1 to V6), medium vectors (V7 to V12), and large vectors (V13 to V18). V15

For a three-level ANPC converter, the vector conduction time can be calculated in the same way as an NPC converter, see reference [4] for details. The switch sequences for a threelevel ANPC converter could also be derived based on an NPC converter. The problem then is how to choose the zero state to achieve a balanced loss distribution. The switching sequences for a three-level ANPC converter in sector 1 region 4 are given in Table VI. From Table VI, it can be seen that there are four different transitions, [x→1→1→1], [x→ x→1→1], [6→ 6→ 6→x] and [6→ 6→ x→x] for all the three phases. In summary, there are only two transitions carried out in region 4, [x→1] and [6→x]. For the [x→1] transition, the zero state “x” could be zero state “5” and zero state “3” based on Table IV. Meanwhile, the zero state “x” could be zero state “2” and zero state “4” for the [6→x] transition. One key point is to keep the conduction ratios of the primary zero states “5” and “2” as , and the secondary zero states “3” and “4” as 1 . Considering the analysis given in section III, the loss balance switching sequences of region 4 in sector 1 for a three-level ANPC converter is derived and given in Table VII. For the sake of simplicity, only half of the sample time is given in Table VII due to the symmetrical distribution of the voltage vectors. All the switching sequences of region 4 for other sectors can be deduced based on Table VII. The switching sequences of region 3 can also be derived through Table VII due to the fact that it shares the same transitions as region 4. The loss balance switching sequences of region 3 in sector 1 for a three-level ANPC converter is given in Table VIII. For region 2, the transitions are similar with region 4, however, this involves a new transition, [6→ x→ x→x→1]. In order to balance the losses, the transitions become [6→ 2→ 4→ x→ 5→ 3 →1], where the middle state “x” is an unknown transition. However, in order to minimize the switching number and keep the ratios of the primary and secondary zero TABLE VI.

SEVEN SEGMENTS SWITCHING SEQUENCES OF REGION 4 FOR SECTOR 1

TABLE VII. LOSS BALANCE SWITCHING SEQUENCES OF REGION 4 IN SECTOR 1 FOR A THREE-LEVEL ANPC CONVERTER

V14

V8

V9

V2

V3

V16

V4

V0

V*

γ

V7

V1

V13

TABLE VIII. LOSS BALANCE SWITCHING SEQUENCES OF REGION 3 IN SECTOR 1 FOR A THREE-LEVEL ANPC CONVERTER V5

V10

V6

V17 V11

V12

V18

Fig.4. Space vector block diagram for a three-level ANPC converter

284

TABLE IX.

LOSS BALANCE SWITCHING SEQUENCES OF REGION 2 IN SECTOR 1 FOR A THREE-LEVEL ANPC CONVERTER

TABLE X.

data sheet parameters and the device current. This method inherently has the advantages of being simple, accurate, and widely applied in the literature [15, 26-31]. See reference [15] for detailed calculation process. In this paper, for the purpose of evaluating the loss distribution performance of the PS-PWM and LB-SVPWM, the loss distribution factors (LDF) and stress ratios (SR) are introduced and defined as follows:

LOSS BALANCE SWITCHING SEQUENCES OF REGION 1 IN SECTOR 1 FOR A THREE-LEVEL ANPC CONVERTER

⁄6 ∑

⁄6

, ,

⁄ states as constant, the middle state “x” should be [4→ 5] for the odd sectors and [2→ 3] for the even sectors. For example, the transitions should be [6→ 2→ 4→4→5→ 5→ 3 →1] for sector 1 and [6→ 4→ 2→2→3→ 3→ 5 →1] for sector 2. Thus, the zero states can be distributed evenly for all the sectors. The loss balance switching sequences of region 2 in sector 1 for a three-level ANPC converter is given in Table IX. Similar analysis can be conducted for region 1, and in order to further reduce the losses on the most stressed devices (T2 and T3), only the primary zero states are considered in the zero vector, V0. The loss balance switching sequences of region 1 in sector 1 for a three-level ANPC converter is given below in Table X. While the switching sequences given in Table VII though Table X are the simplest ones, it is important to note that there are also many other switching sequences. Other sequences will involve more segments than these given in Tables VII X. B. Calculation of Proportionality Constant From the analysis in section III, it is known that a large proportionality constant can balance the loss distribution more evenly at high modulation indices and a lower ratio is helpful for balancing the loss distribution at low modulation indices. The ratio function could be expressed by a secondorder polynomial, or a more complex equation; however the relationship between and is expressed by a continuous piecewise function here to simplify the calculation. 7/4 0.5

0.5

0

0.4

(1)

0.4

1

(2)

Here, m=0.4, is the boundary condition of these two linear equations, and is obtained through test points. The inspiration here is to obtain a modulation index, with which by adjusting the value of the variable b, the power losses over the most stressed devices, T2 and T3, will be correspondingly changed. C. Power Losses for Semiconductor Devices The power losses in a semiconductor device can be divided into three categories: switching loss, conduction loss and blocking loss [25]. The blocking loss is usually ignored due to its small contribution to the total loss. The power losses for the switching devices are calculated based on the device

(3) (4) (5) (6)

where, and 1,2,5 are the losses on the ith IGBT and diode, respectively. The loss distribution factor describes the extent of variation or dispersion deviating from the average loss. A low LDF indicates that the losses in all switching devices tend to be very close to the average loss (LDF=0 means that the loss distributes equally for each device), while a high LDF demonstrates that the losses among all switching devices are distributed over a wide range of values. D. Loss Balancing SVPWM Considering the Power Factor For an inverter case, when the power factor is reduced, the conduction time of Type-① and Type-③ commutations will be increased, but shorter than Type- ② and Type- ④ commutations. Thus, the losses among the semiconductor devices will be distributed more evenly because the reduced power factor involves the conductions of D1, D2, D3, D4, T5 and T6. Therefore, based on the above analysis and Table IV, the conduction ratios of the primary and secondary zero states could be summarized given next. For an ANPC inverter case, the most stressed devices are still T2 and T3 for high modulation indices. Therefore, the zero states “OU1” and “OL1” in Type-① and Type-③ commutations, respectively, are considered as the primary zero states and account for a high conduction ratio. For the sake of simplicity, one can directly apply the primary zero state ratios of Type-② and Type-④ commutations as the ratios of zero states “OU1” and “OL1” in Type- ① and Type- ③ . Therefore, a better loss distribution can be achieved for all four types of commutations. It should be mentioned that one can also apply the power factor analysis to the ratio calculation primarily to search for the optimum value when considering both modulation m and power factor . However, such a method involves a two dimensional calculation, and thus a 2-D look up table and corresponding interpolations would be necessary. Therefore, in order to simplify the calculation, the ratio is calculated based on m and , independently. V.

EVALUATION OF THE PROPOSED LB-SVPWM

A. LB-SVPWM Characteristics To demonstrate the characteristics of the proposed LBSVPWM for a three-level ANPC converter, the LB-SVPWM

285

is compared with PS-PWM3 [14] under various modulation index conditions in the simulation. In this simulation, the system is configured as a three-phase three-level ANPC inverter with a dc-link voltage of 3 kV, feeding an RL load (Rload=5 Ω, Lload=0.01 H). The fundamental frequency is 60 Hz, and the switching frequency is 1800 Hz. The current and voltage waveforms for a three-level ANPC inverter modulated by LB-SVPWM are shown in Fig. 5. Comparisons of the dc-link voltage utilization and total harmonics distortion (THD) of the line-to-line voltage under various modulation index conditions are given in Fig.6. As shown in Fig.6 (a), the proposed LB-SVPWM can obtain a higher voltage conversion ratio (around 1.15 times of the results from PS-PWM3 strategy), and generate less THD in output voltages when compared with that from PS-PWM3 techniques, as shown in Fig.6 (b). Another interesting observation which was found through the simulation analysis is that the THD for the LB-SVPWM is lower than that of PSPWM3 even when they have the same fundamental output voltage. B. Loss Distribution Results It was also found that the proposed LB-SVPWM strategy experiences slightly more switching losses than the PS-PWM strategy due to the reason that it involves more segments in the switching sequences in one fundamental period. However, such characteristic of LB-SVPWM is helpful for reducing the THD in the output voltage and currents. Besides, this drawback will not be obvious for high-power medium-voltage power converters, in which the switching frequency is generally very low (below 10 kHz). Also, switching losses can be mitigated by using soft switching technologies [32-33], and will be very small in all-SiC based ANPC converters, which will be discussed in Section VI of this paper. 3000

To conduct an objective comparison, the loss comparison was achieved by keeping the fundamental value of the output voltage constant irrespective the types of PMW strategies, which can be realized by adjusting the modulation indices [29]. Here, the IGBT power modules manufactured by Infineon, FS225R17OE4 (1.7 kV/225A), is selected for the loss calculations. Moreover, for the purpose of evaluating the loss distribution performance of PS-PWM1, PS-PWM3 [14] and LB-SVPWM, the loss distribution factors (LDF), stress ratios (SR), under various fundamental line-to-line voltages are given in Fig.7 and Fig.8. For making a comparison over all modulation indices, large (VLL =2808V, VLL =2407V and 1800V), medium (VLL =1531V) and small (VLL=725.2V and 144.7V) voltage vectors were selected. From Fig.7 and Fig.8, it can be observed that the LBSVPWM has lower loss distribution factors and stress ratios than the other two PS-PWM techniques, which indicates that the device losses for the LB-SVPWM are distributed more evenly, and the power losses on the most stressed device were reduced. The device loss distributions yielded from the PS-PWM and LB-SVPWM methods under various modulation indices are shown in Fig. 9. According to Fig. 9, it can be seen that the LB-SVPWM distributes the device losses more evenly, where the losses on the devices T2 and D5 are distributed to other devices D2 and T5. Besides, the comparison of THD in the output current of ANPC inverters, as shown in Fig.10, indicates that using the presented LB-SVPWM method can achieve the least THD than the other two PS-PWM methods presented in the literature [14].

10*Iph (A) VLL (V)

2000 1000 0 -1000 -2000 -3000 0.04

0.045

0.05

0.055

0.06 Time (s)

0.065

0.07

0.075

Fig.7. Comparison of the loss distribution factor (LDF) between various modulation methods of ANPC inverters.

0.08

Fig.5. Line-to-line voltages and phase current of a three-level ANPC inverter (modulation index: m=0.8).

(a)

(b)

Fig. 6. Comparison of the voltage conversion ratio and THD in output line voltage between PS-PWM3 and LB-SVPWM with various modulation indices. (a) voltage conversion ratio. (b) THD.

Fig.8. Comparison of the device stress ratios (SR) between various modulation methods of ANPC inverters.

286

Device total losses (w)

counterparts. Therefore, it’s very necessary n to evaluate the performance of the presented LB-SVPWM method in loss balancing of all-SiC ANPC converterrs.

400 PS-PWM1

300

PS-PWM3

200

The SiC devices used here aree CREE SiC MOSFETs, CAS100H12AM1 (1200V/100A), with w SiC Schottky diodes integrated in the package. The simullation results of the losses distribution effects at various modulaation indices are shown in Fig. 11, from which we can conclud de that, the proposed LBSVPWM has a better loss-balancing g effect for all-SiC ANPC converters. The main reason is that the proposed modulation ncing the conduction loss method is more effective for balan and SiC devices typically has larg ger conduction loss than switching loss in the total losses conttribution.

LB-SVPWM

100 0 T1

D1

T2

D2

T5

D5

Device total losses (w)

(a) 120 100 80 60 40 20 0

VII. CONCLUSSIONS PS-PWM1

Loss distribution of switching dev vices in power converters, which is generally determined by the specific modulation method for given switching devices, plays an important role in the reliability and output capacity off power converters. In this paper, an improved modulation meth hod based on conventional the switching devices. Comparative analysis a was carried out in simulation between the proposed metthod and the conventional

PS-PWM3 LB-SVPWM T1

D1

T2

D2

T5

D5

Device toal losses (w)

Device power losses (w)

(b) 50 40 30

PS-PWM1

20

PS-PWM3

10

LB-SVPWM

0 T1

D1

T2

D2

T5

50 40 30

PS-PWM1

20

PS-PWM3

10

LB-SVPWM

0 T1

D5

D1

T2

D2

T5

D5

(a)

(c) Device toal losses (w)

Fig. 9. Losses distribution of switching devices in ANPC inverters with various modulation indices (a) m=0.95, (b) m=0..5, (c) m=0.25.

15 10

PS-PWM1 PS-PWM3

5

LB-SVPWM 0 T1

D1

T2

D2

T5

D5

Fig.10. Comparison of total harmonic distortion (THD D) in output current of ANPC inverter with various modulation m methods .

VI.

SVPWM IN ALLEVALUATION OF THE PROPOSED LB-S SIC MOSFET BASED ANPC CONVEERTERS

As a matter of fact, loss distribution among switching devices of power converters is not only affected by the modulation method, but also can be influenceed by the inherent characteristics of the switching devices utilizzed. For instance, the currently emerging wide bandgap devicees such as SiC and GaN devices, have much lower switching loosses than their Si

287

Device toal losses (w)

(b) 4 3

PS-PWM1

2

PS-PWM3

1

LB-SVPWM

0 T1

D1

T2

D2

(c)

T5

D5

Fig. 11. Losses distribution of switchiing devices in all-SiC ANPC inverters with various modulation indices (a) m=0.95, (b) m=0.5, (c) m=0.25.

PS-PWM methods for both all-Si ANPC inverters and all-SiC ANPC inverters, which verified the advantages of the presented modulation method in balancing the loss distribution, increasing the fundamental output voltage, and reducing harmonic distortion in the output voltage, especially for all-SiC ANPC converters. Experimental verification will be conducted in future work to validate the theoretical analysis and simulation results presented above. REFERENCES [1]

[2]

[3]

[4]

[5] [6] [7] [8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

[16]

Jih-Sheng Lai, and Fang ZhengPeng, “Multilevel Converters-A New Breed of Power Converters,” IEEE Transactions on Industry Applications, Vol. 32, No. 3, pp. 509-517, May/June 1996. José Rodríguez, Steffen Bernet, Bin Wu, Jorge O. Pontt, and Samir Kouro, “Multilevel Voltage-Source-Converter Topologies for Industrial Medium-Voltage Drives,” IEEE Transactions on Industrial Electronics, Vol. 54, No. 6, pp. 2930-2945, December 2007 Ramón C. Portillo, MaÁngeles Martín Prats, José I. León, Juan Antonio Sánchez, Juan M. Carrasco, Eduardo Galván and Leopoldo Garcia Franquelo, “Modeling Strategy for Back-to-Back Three-Level Converters Applied to High-Power Wind Turbines,” IEEE Transactions on Industrial Electronics, Vol. 53, No. 5, pp. 1483-1491, October 2006. Xin Jing, “Modeling and Control of a Doubly-Fed Induction Generator for Wind Turbine-Generator Systems,” Marquette University, master thesis, December 2012. ABB [Online]. Available: http://www.abb.com. Siemens [Online]. Available: http://www.ad.siemens.com. Yaskawa [Online]. Available: http://www.yaskawa.com. Arkadiusz Lewicki, Zbigniew Krzeminski, and Haitham Abu-Rub, “Space-Vector Pulsewidth Modulation for Three-Level NPC Converter With the Neutral Point Voltage Control,” IEEE Transactions on Industrial Electronics, Vol. 58, No. 11, pp. 5076-5086, November 2011. Guojun Tan, Qingwei Deng, and Zhan Liu, “An Optimized SVPWM Strategy for Five-Level Active NPC (5L-ANPC) Converter,” IEEE Transactions on Power Electronics, 2013, on publish. Nikola Celanovic and Dushan Boroyevich, “A Comprehensive Study of Neutral-Point Voltage Balancing Problem in Three-Level NeutralPoint-Clamped Voltage Source PWM Inverters,” IEEE Transactions on Power Electronics, Vol. 15, No. 2, pp. 242-249, March 2000. Sergio Busquets Monge, Sergio Somavilla, Josep Bordonau, and Dushan Boroyevich, “Capacitor Voltage Balance for the Neutral-PointClamped Converter using the Virtual Space Vector Concept With Optimized Spectral Performance,” IEEE Transactions on Power Electronics, Vol. 22, No. 4, pp. 1128-1135, July 2007. Sridhar R. Pulikanti, Mohamed S. A. Dahidah, and Vassilios G. Agelidis, “Voltage Balancing Control of Three-Level Active NPC Converter Using SHE-PWM,” IEEE Transactions on Power Delivery, Vol. 26, No. 1, pp. 258-267, January 2011. Thomas Brückner, Steffen Bernet, and Henry Güldner, “The Active NPC Converter and Its Loss-Balancing Control,” IEEE Transactions on Industrial Electronics, Vol. 52, No. 3, pp. 855-868, June 2005. D. Floricau, G. Gateau, A. Leredde, and R. Teodorescu, “The Efficiency of Three-Level Active NPC Converter for Different PWM Strategies,” in Proc.13th European Conference on Power Electronics and Applications, 2009, pp. 1-9. Xin Jing, Jianbiao He and Nabeel A. O. Demerdash, “Application and Losses Analysis of ANPC Converters in Doubly-Fed Induction Generator Wind Energy Conversion System,” in Proc. IEEE International Machines and Drives Conference, Chicago, May 2013, pp.131-138. Lin Ma, Xinmin Jin, T. Kerekes, M. Liserre, R. Teodorescu and P. Rodriguez, “The PWM Strategies of Grid-Connected Distributed Generation Active NPC Inverters,” in Proc. IEEE Energy Conversion Congress and Exposition, San Jose, September 2005, pp. 920 – 927.

[17] Jun Li, A. Q. Huang, S. Bhattacharya, and Wei Jing, “Application of Active NPC Converter on Generator Side for MW Direct-driven Wind Turbine,” in Proc. IEEE Applied Power Electronics Conf., 2010, pp. 1010-1017. [18] Thomas Brückner, Steffen Bernet, and Peter K. Steimer, “Feedforward Loss Control of Three-Level Active NPC Converters,” IEEE Transactions on Industry Applications, Vol. 43, No. 6, pp. 1588-1596, November/December 2007. [19] Dan Floricau, Guillaume Gateau, and Alexandre Leredde, “New Active Stacked NPC Multilevel Converter: Operation and Features,” IEEE Transactions on Industrial Electronics, Vol. 57, No. 7, pp.2272-2278, July 2010. [20] Jun Li, Alex Q. Huang, Zhigang Liang and Subhashish Bhattacharya, “Analysis and Design of Active NPC (ANPC) Inverters for FaultTolerant Operation of High-Power Electrical Drives,” IEEE Transactions on Power Electronics, Vol. 27, No. 2, pp. 519- 533, February 2012. [21] Savelii Zhukov, “Loss Modeling of Three-Level Inverters controlled with Space Vector Modulation Technique,” Lappeenranta University of Technology, master thesis, 2012. [22] O. Apeldoorn, B. Ødegård, P. Steimer and S. Bernet, “A 16 MVA ANPC-PEBB with 6 kA IGCTs,” in Proc. IEEE IAS, Hong Kong, October 2005, Vol. 2, pp. 818-824. [23] P. K. Steimer, O. Apeldoorn, B. Ødegård, S. Bernet and T. Brückner, “Very High Power IGCT PEBB technology,” in Proc. IEEE PESC, Recife, 2005, pp. 1-7. [24] Jose Rodriguez, Steffen Bernet, Peter K. Steimer, and Ignacio E. Lizama, “A Survey on Neutral-Point-Clamped Inverters,” IEEE Transactions on Industrial Electronics, Vol. 57, No. 7, pp. 2219-2230, July 2010. [25] A. D. Rajapakse, A. M. Gole, and P. L. Wilson, “Electromagnetic Transients Simulation Models for Accurate Representation of Switching Losses and Thermal Performance in Power Electronic Systems,” IEEE Transactions on Power Delivery, Vol. 20, No. 1, pp.319-327, January 2005. [26] Sibylle Dieckerhoff, Steffen Bernet and Dietmar Krug, “Power LossOriented Evaluation of High Voltage IGBTs and Multilevel Converters in Transformerless Traction Applications,” IEEE Transactions on Power Electronics, Vol. 20, No. 6, pp.1328-1336, November 2005. [27] Johann W. Kolar, Hans Ertl, and Franz C. Zach, “Influence of the Modulation Method on the Conduction and Switching Losses of a PWM Converter System,” IEEE Transactions on Industry Applications, Vol. 21, No. 6, pp. 1063-1075, November/December 1991. [28] Dušan Graovac and Marco Pürschel, “IGBT Power Losses Calculation Using the Data-Sheet Parameters,” Infineon Application Note, V 1.1, pp. 1-17, January 2009. [29] Yunxiang Wu, Mohsin A. Shafi, Andrew M. Knight and Richard A. McMahon, “Comparison of the Effects of Continuous and Discontinuous PWM Schemes on Power Losses of Voltage-Sourced Inverters for Induction Motor Drives,” IEEE Transactions on Power Electronics, Vol. 26, No. 1, pp. 182-191, January 2011. [30] M. H. Bierhoff and F. W. Fuchs, “Semiconductor Losses in Voltage Source and Current Source IGBT Converters Based on Analytical Derivation,” in Proc. IEEE Annual Power Electronics Specialists Conference, 2004, Vol. 4, pp. 2836-2842. [31] Lassi Aarniovuori, Lasse I. E. Laurila, Markku Niemelä, and Juha J. Pyrhönen, “Measurements and Simulations of DTC Voltage Source Converter and Induction Motor Losses,” IEEE Transactions on Industrial Electronics, Vol. 59, No. 5, pp. 2277-2287, May 2012. [32] B. Kaku, I. Miyashita, S. Sone, “Switching loss minimised space vector PWM method for IGBT three-level inverter,” in Proc. IEE Electric Power Applications, Vol. 144, No.3, pp. 182-190, 1997. [33] Gabriel Ortiz, Hirofumi Uemura, Dominik Bortis, Johann Walter Kolar, and Oscar Apeldoorn, “Modeling of Soft-Switching Losses of IGBTs in High-Power High-Efficiency Dual-Active-Bridge DC/DC Converters,” IEEE Transactions on Electron Devices, Vol. 60, No. 2, pp. 587-597, February 2011.

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