Low-Power Circuits using Dynamic Threshold Devices Paul Beckett Electrical & Computer Engineering RMIT University +613 99255301
[email protected] ABSTRACT We present simulations for ultra-thin body, fully-depleted, double-gate (DG) silicon-on-insulator (SOI) devices that can be readily optimized for both static power loss and performance by dynamically shifting the threshold voltage during operation. A small number of simple circuits are analyzed and it is demonstrated that subthreshold power can be reduced by a factor in excess of 103 for these examples.
Categories and Subject Descriptors B.7.1 [INTEGRATED CIRCUITS] Types and Design Styles – Advanced technologies, VLSI.
General Terms Design.
Keywords Subthreshold leakage, double-gate, thin-body, SOI, silicide, CMOS, nanotechnology.
1. INTRODUCTION Balancing the needs of low power and high performance in future nanoscale systems will be a difficult optimization problem that will have to be addressed at a number of levels [1], [2]. For example, the analysis in [3] shows that hitting the 2016 ITRS targets for high-performance logic would require threshold voltages to be controlled to within 0.1V. This will be increasingly difficult to achieve as channel lengths scale below 50nm due to physical effects such as random dopant fluctuation, surface roughness and variability in device dimensions along with electrical effects such as charge sharing and DIBL. Ultimately, of course, it will be decisions about supply and threshold voltages that will determine both the dynamic and subthreshold power loss in a system - as well as its operating frequency. For example, as the supply voltage is reduced, thereby saving dynamic power, it will become increasingly difficult to find a fixed threshold voltage that optimizes both delay and static power, especially given a likely increase in process variability. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. GLSVLSI’05, April 17–19, 2005, Chicago, Illinois, USA. Copyright ACM 1-59593-057-4/05/0004...$5.00.
One solution is to allow VTH to vary, thereby changing the optimization problem into one of setting an appropriate threshold in a particular part of the system or during a particular part of its operating cycle. There have already been a number of proposals (e.g. [7, 8]) that exploit the shifts in threshold voltage that can be produced by modulating the back-gate bias in double-gate devices. Their common objective is to allow subthreshold power and delay to be optimized separately, thereby reducing the need to carefully manage the threshold voltage and subthreshold slope in order to achieve a particular power-delay design point. This paper focuses on the application of thin-body (TB), fullydepleted (FD) double-gate (DG) silicon-on-insulator (SOI) devices. These are likely to become a preferred nanoscale circuit element due to their potentially superior sub-threshold performance and better control of short-channel effects. By simulation it is shown that, as the channel thickness reduces to the order of 5nm, the effect of the back gate bias increases to a point where threshold shifts of greater than 400mV are possible with ±1V back gate bias changes. The remainder of the paper proceeds as follows. In Section 2 we present the results of simulations performed on TBFD-DGSOI devices with fully silicided source and drain regions showing the scale of the threshold shifts possible with this technology as the channel thickness reduces. In Section 3 we present SPICE results for circuits based on these devices demonstrating how power and delay can be separately optimized. In Section 4 we conclude and briefly look at one potential application of the technique.
2. THIN BODY SILICIDE DEVICES The increased difficulty in maintaining low IOFF as channel lengths scale down below 50nm has resulted in a revival of interest in Schottky barrier MOSFETs (first described more than 30 years ago [9]), in which metal silicides (e.g. PtSi, ErSi etc.) replace the heavily doped silicon source and drain regions [10, 11]. Metal silicides form natural Schottky barriers to silicon substrates, acting to confine carriers and reducing or eliminating the need for impurities in the channel to prevent current flow in the "off" condition [12]. Compared with conventional devices these exhibit several advantages, including the elimination of punchthrough and latch-up. As well as offering a significantly simpler processing technology, they may also be more compact and scalable than conventional CMOS due to the elimination of the well(s), body contacts and isolation regions. At the ultimate dimensions for this technology (e.g. lengths in the order of 10nm), the channels would effectively become undoped silicon wires with regular silicide patterns forming the source/drain regions. At this scale it may be possible to approach densities of 108 gates/mm2.
However, this comes at a cost - the overall current drive of Schottky barrier devices can be significantly lower than MOS due to the very high resistance of their source/drain regions at low supply voltages [13]. The resultant loss in performance (implied by an increased τ=CV/I) would have to be made up at the architectural level. Sidewall Oxide
S
GF Gate Oxide SiO2 TOXF = TOXB = 1.5nm ErSi1.7
ErSi1.7
Si channel TSI = 5-30nm ND = 1015 cm-3
GB
D Self-aligned erSi S/D φBN =0.28
Metal gates: ψ =variable LGATE = 4 x TSI
Figure 1. Simplified view of a n-type thin body, fullydepleted double-gate silicide transistor with undoped channel. The p-type uses PtSi source/drain.
of ErSi1.7 (n-type: barrier height φBN = 0.28eV above Si) and PtSi. (p-type: φBP = 0.23eV). The gate work function (ψ) was adjusted to give the desired threshold voltage VBG=0. The gate length was set at 4xtSI, to maintain good gate control and to reduce short channel effects that would unnecessarily complicate the analysis. Figure 2 illustrates the sensitivity of the threshold voltage (as seen at the front gate) to the back gate bias with various values of channel thickness (tSI) between 5nm and 30nm. These plots are for the ntype transistor; those for the p-type have a similar form. In Figure 2 the threshold values have been normalized such that ∆VTH=0 at VBG=0. It can be seen that as the channel thickness is reduced the threshold sensitivity increases to a point where at tSI=5nm, setting VBG = -1V can produce ~0.45V shift in threshold voltage. A shift of similar magnitude is observed for the p-type device at VBG=VDD+1. While it is theoretically possible for DG-SOI transistors to approach the ideal subthreshold slope for MOS (~60mv/decade) when used in double gate mode (both gates driven together), no device fabricated to date has even approached this figure. In the ground-plane mode, the behavior of S is similar to that of planar devices and is given by [15]:
S=
Figure 2. Threshold voltage change (∆ ∆VTH) vs. back gate voltage at various tSI for the n-type device of Figure 1. P-type device characteristics are similar.
Figure 3. TCAD simulated log(ID) vs VFG (n-type) for various body thickness values (tSI). ID has been normalized to its value at VFG=1V, showing the relative effect on IOFF achieved with a –1V shift in VBG. VDD=1V, and the initial threshold voltage for each curve (at VBG=0) has been set to approximately 0.2V. Thin-body double-gate p and n-type silicide S/D devices of the general form shown in Figure 1 were analyzed with a commercial TCAD simulator1 using classical drift-diffusion models. These models have been shown to be sufficiently accurate to around tSI=5nm, the limit of this work [14]. The devices have uniform, lightly doped channels (ND = 1015 cm-3) with source/ drain regions 1
Atlas/SPisces - Silvaco Inc.
kT C ln(10)1 + S q C OXF
(1)
where: COXF = the front gate oxide capacitance ≈ εOX/TOXF and CS is the effective body capacitance between the inversion layer and the back gate: CS ≈ εSI/tSI if the back surface is in accumulation, and CS = CSICOXB/(CSI+COXB) in depletion. Substituting εSI ≈ krεOX, (kr = εSI/εOX ≈ 3 for SiO2 dielectric), the subthreshold slope becomes:
k r TOXF (2) S ≈ 601 + mv/decade. + k T T r OXB SI The term krTOXB becomes zero if the back surface is in accumulation. While reducing the body thickness increases the threshold sensitivity (∂VTH/∂VBG), Equation (2) implies that it also degrades the subthreshold slope. To maintain S
