Low Voltage Bootstrap Switch using 0.18-µm

Low Voltage Bootstrap Switch using 0.18-µm Technology Shruti Oza1, N.M.Devashrayee2 1

Asst. Professor, E.C. Department, Kalol Institute of Technology & Research Centre, Kalol

Abstract: This paper discusses low voltage bootstrap switch for sample & hold circuit; compares its performance with classical CMOS transmission gate. The bootstrap switch is designed with nMOS using 0.18-µm technology, 1.8V. The results obtained indicate effect of bootstrap switch for a specified supply voltage, without considering bulk-effect compensation. An important attribute of the design is that the on resistance and gate source voltage of the switch are almost constant. The W/L ratio of the transistor is selected considering trade off between Ron and Charge Injection. Key Words: Bootstrapping, Charge Injection, Ron , Sampling Switch. 1. Introduction The sub-micrometer CMOS process is the technology for current and future semiconductor systems and applications due to its low-cost. Technology constraints and battery-powered operation require that lowvoltage analog circuits be designed[6-8]. Whereas low-voltage operation is associated with many advantages for digital circuits, it generally complicates the design of analog circuits. When the supply voltage is lowered, not only does it become increasingly difficult to maintain the same (high) level of SNDR performance, but also even the functionality of the circuit may be hard to preserve [5]. The design of analog switches, which conduct reliably in the rail-to-rail range, is the main difficulty in the design of low-voltage circuits. In low-voltage systems, analog sampling becomes particularly difficult because the available headroom severely limits the tradeoffs among dynamic range, linearity, design flexibility, speed and power dissipation [1-4]. This paper describes nMOS bootstrap switch designed considering simple circuits at low voltage. The paper is organized as follows: Section-II describes brief introduction of MOS switches. The design criterion is mentioned in Section-III. Section-IV discusses low voltage nMOS bootstrap switch. Finally, simulation results are discussed in Section-V.

2. MOS Switches Analog switches are common building blocks in analog signal processing. A MOSFET in itself can be used as an analog switch. The drain and source terminals are the two switch terminals and the gate (and sometimes bulk’) terminals are used to control the conductivity of the channel between the two switch terminals. NMOS transistors cannot conduct for source voltages beyond Vdd − Vthn for normal clock signals, where

Vthn is the threshold voltage of NMOS transistor. Conversely; PMOS transistor cannot conduct for voltages Ron below Vthp , where Vthp is the threshold voltage of PMOS transistor. The conductance of MOS is shown in fig. 1.

Fig. 1 Conductance of MOS v/s Supply voltage

Fig. 2 Conductance of CMOS v/s Supply voltage

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The benefit of CMOS TG is lower & linear overall conductance. Another advantage of using CMOS TG is that it can pass logic high or low without threshold voltage drop. In analog applications, switches must achieve high speed and linearity with high precision. Figure 2 shows conductance of CMOS TG. In MOS switches finite amount of mobile charge is stored in the channel when an MOS transistor is on. When the transistor turns off, the channel charge disappears through either the source/drain electrodes or the substrate electrode. The channel charge being transferred to the data node superposes an error component to the sampled voltage. This charge injection is an important factor to be considered while designing switch.

3. Design Criteria The on conductance of CMOS can be given by gon =μn *Cox*(W/L)n *(VDD−Vin −Vthn) +μp *Cox*(W/L) p *(Vin−|Vthp|) Now, if we make

μ n * C ox * (W / L )n = μ p * C ox * (W / L )P

then conductance of the

CMOS TG will be independent of the input. The on-resistance g on = 1 / Ron . In order to make Ron smaller we should increase (W/L) ratio. Again charge injection can be given by

[

]

ΔQc = −((W*L)n *Cox *(VDD−Vthn−Vin)) +((W*L) p *Cox *(Vin−| Vthp |))

and ΔVe = ΔQc /[2 * C h ] To reduce charge injection (W/L) ratio should be decreased. Considering design criteria for CMOS TG, in order to decide switch specifications the set up shown in fig. 3. In order to decide (W/L) ratio of switch, its effect on R on and charge injection is observed. For 0.18μm technology, (W / L) p = 2.41(W / L) n is selected to make conductance independent of the input. Figure 4 shows output of the CMOS TG switch for sine input.

Fig. 3 CMOS TG Switch

Fig. 4 Output of CMOS TG Switch

4. Low Voltage NMOS Bootstrap Switch For nMOS Ron is given by

As Ron for nMOS depends on V gs , in order to make Ron independent of input variations we have to make V gs independent of input. This is possible by using gate – source bootstrapping shown in fig. 5. The circuit requires two non overlapping clock signals phi-1 & phi-2. During phi-2 capacitor Ca charges to Published in International Journal of Advanced Engineering & Applications, Jan. 2010

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Vdd and nMOS doesn’t conduct. During phi-1 Ca will be in series of Vin . This makes approximately equal to Vdd .

Fig. 5 Basic Concept of Bootstrapping

Fig. 6 nMOS Bootstrap Switch

The nMOS bootstrap switch shown in fig 6 uses clock doubling circuit, bootstrap circuit and nMOS sampling switch. In fig. 6 rounded rectangle shows clock-doubling circuit, which drives transistor MN_3. The gate voltage of transistor MN_3 toggles between Vdd − Vt and 2 ⋅ Vdd − Vt . This is required in order to have reliable operation. The transistors MN_9, MP_2, MN_4, MN_3 and MN_8 correspond to five ideal switches Sw1-Sw5. MN_10 is the main sampling switch. During phase phi-2 MN-10 is connected to Gnd through switch MN8 and capacitor Ca is charged. Thus MN_10 doesn’t conduct during phi-2. During phi-1 MN_10 is on and charged capacitor Ca will be connected in series with Vin . The charged capacitor provides constant voltage of Vdd between gate and source of MN_10 during phase Phi-1 of the clock, thus also ensures a low on-resistance independent of the input signal. During this phase, MN_5 pulls down the gate of MP-2, turning it on and allowing the charge to flow from capacitor Ca to the gate of MN_6, MN_9 and MN_10. MN_6 and MN_7 increase the reliability of the transistors MP_2 and MN_8. For all the transistors used in circuit, Vgs , Vds and Vgd are less than Vdd , which ensures reliability of the circuit.

5. SIMULATION RESULTS The simulation results are obtained using 0.18µm technology. The supply voltage is varied from 1.4V to 2V to observe variations in Vgs and Ron . Figure 7 shows Ron v/s Vin for various Vdd . It can be observed that the value of Ron is less for higher value of Vdd . As supply voltage decreases the variation and value of Ron increases. The maximum variation of Ron is 6.5% at 1.4V supply.

Fig. 7

Ron v/s Vin

for various

Vdd

Published in International Journal of Advanced Engineering & Applications, Jan. 2010

Fig. 8

V gs v/s Vin

for various Vdd . 22

Similarly, fig. 8 shows V gs v/s Vin for various Vdd . For the various supply voltage as we are varying

Vin from 0.2 to supply voltage we can observe that V gs remains constant, which show the effect of bootstrap switch. The maximum variation in V gs is 0.17% only. Figure 9 shows output of bootstrap switch with on and off period for sine input of 10MHz frequency. The effect of charge injection can be observed during off period of the switch. The amount of charge injection is dependent on (W/L) ratio of the switch and hold capacitance. To observe the effect of these parameters, width of sampling switch is varied by 10% and fig. 10 shows the result. Similarly fig. 11 shows result when hold capacitance is varied by 10%. Table-1 summarizes all the results.

Fig.9 Bootstrap Switch Output for Sine Input

(a)

(b) Fig. 10 (a) Effect of Load variation (b) Effect of Width (Sampling Switch) variation

(a)

(b) Fig 2.8 Effect of Ch Variation- (a) DC input (b) Sine input

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6. Conclusion The nMOS bootstrap switch designed here with 0.18µm technology, 1.8V. As (W/L) ratio of the main nMOS switch is selected considering the effect of it on Ron and Charge injection, the switch can be used for sample and hold circuit. Also switch is reliable for low voltage operation. The simulation results indicate that switch performance well even at low voltage. References [1]Mohammad Irfan Kazim-“Design of highly linear sampling switches for CMOS Track & Circuits”, http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6339, 2006 [2] Christian Jesus B. FAYOMI, Gordon W. ROBERTS, -“Design & Characterization of Low Voltage Analog Switch without the need for Clock Boosting, The 47th IEEE International Midwest Symposium on Circuits and Systems, Vol-3, pp-315-18, July-2004 [3] Christian Jesus B. FAYOMI, Gordon W. ROBERTS, and Mohamad SAWAN, - “Low-Voltage CMOS Analog Bootstrapped Switch for Sample-and-Hold Circuit: Design and Chip Characterization”, IEEE International Symposium on Circuits and Systems, Vol-3, pp-2200-2203, May-2005 [4] Liang Dai and Ramesh Harjani- “CMOS Switched-Op-Amp-Based Sampleand-Hold Circuit”, Proceedings of IEEE Symposium on Circuits and Systems, Vol-1, pp-476-479, June-1998 [5] Jesper Steensgaard, “Bootstrapped Low-Voltage Analog Switches”, Proceedings of IEEE Symposium on Circuits and Systems Vol-2, pp-29-32, July-1999 [6] P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design”, Oxford Press, New York, 2004 [7] Christian Jesus B. Fayomi, Gordon W. Roberts and Mohamad Sawan,- “Reliable Circuit Techniques for Low-Voltage Analog Design in Deep Submicron Standard CMOS: A Tutorial”, Analog Integrated Circuits and Signal Processing, Vol-39 , Issue 1, pp-21-38 April-2004. [8] Joyce Cheuk and Wai Wong, "CMOS Sample-and-Hold Circuits," Academic materials. Department of Electrical and Computer Engineering, University of Toronto, November, 2001

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