Maximum Predictability in Signal Interactions With ... - IEEE Xplore

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 55, NO. 4, AUGUST 2006

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Maximum Predictability in Signal Interactions With HARETICK Kernel Mihai V. Micea, Member, IEEE, Vladimir-Ioan Cretu, Member, IEEE, and Voicu Groza, Senior Member, IEEE

Abstract—This paper addresses the problem of the predictability of the critical digital-signal acquisition and processing applications while interacting with signals. The hard real-time compact kernel (HARETICK) is briefly presented along with the model of the hard real-time tasks: the ModX. This paper focuses on the specification, analysis, scheduling, and implementation of the applications able to generate perfectly periodic signals on the HARETICK-based platforms. A specific nonpreemptive technique for scheduling a set of the ModXs with fixed-execution times during their periods—the fixed execution nonpreemptive (FENP) algorithm—was introduced. Some of the most interesting experimental results are also discussed. Index Terms—Execution context, fixed execution, operating kernel, predictability, real-time, scheduling, signal generation, task model.

I. I NTRODUCTION

T

ODAY’S scientific and engineering communities invest important amount of efforts and resources in the fields of digital signal processing (DSP) and embedded systems, as they are integrated in a very large number and diversity of environments and digital-control applications, covering almost every human activity. Such applications, including digital-signal acquisition and processing, sensor-data processing, digital waveform and programmable function generation [1]–[4], require, in most cases, real-time behavior of the hardware–software components of the target platform [5]–[7]. Furthermore, many applications have a critical impact on the environment and on humans. Predictable signal interaction of the embedded digital-control and data-processing systems is a key issue in the field, with direct implications in a large variety of applications, including radio detection and ranging (RADAR) processing [8], complex data acquisition [9], digital-communication systems [10], signal spectral analysis [11], configurable waveform generation [12], and many others. The basic control architectures currently

Manuscript received June 15, 2005; revised April 19, 2006. This work was supported in part by a grant from the Romanian Ministry of Education CNCSIS 717/2005-2007 and a grant from Motorola, Inc., Austin, TX, and Freescale Semiconductor Inc. (formerly a Motorola company), Austin, through the Ph.D. Collaboration Program with the Department of Computer and Software Engineering (DCSE) Timisoara, Romania, DALT-PhD/2001-2005. M. V. Micea and V.-I. Cretu are with the Department of Computer and Software Engineering (DCSE), “Politehnica” University of Timisoara, 300223 Timisoara, Romania (e-mail: [email protected]; [email protected]). V. Groza is with the School of Information Technology and Engineering (SITE), University of Ottawa, Ottawa, ON KIN 6N5, Canada (e-mail: [email protected]). Digital Object Identifier 10.1109/TIM.2006.876530

used for the sensor-data acquisition systems [1], [4], [9], [10], [13]–[15] involve generating perfectly periodic “Start of Conversion” (SOC) pulses to the converter. The conversion results can be fetched asynchronously on the interrupts generated by the activation of the “End of Conversion” signal issued by the converter or in a periodic manner, based on the SOC signalgeneration mechanism. When signal interactions such as periodic signal/waveform generation or periodic input-data acquisition have strict timing specifications imposed by the critical applications, the most common approaches currently used involve a supplemental specialized external hardware, including direct digital synthesis (DDS), phase-locked loops (PLL), fractional N-frequency synthesis (F-N FS), programmable real-time counters and clock devices (RTC), etc. [1], [8], [10], [12]–[16]. Such solutions increase the complexity of the hardware and control algorithms at the embedded platform level, with direct implications on the cost and production time of the systems. Correct operating results of the critical applications on the embedded systems require solutions to a threefold problem: 1) computational correctness of the system; 2) its ability to guarantee that all specified deadlines will be met (timing correctness); and 3) consistent predictability support for application analysis and operation. The last two requirements still remain as the important issues for today’s real-time-system development and engineering fields [17], [18]. A large number of the real-time systems and application development tools were derived from traditional time-sharing models and further adapted and optimized to increase their speed of reacting to the events. Their main disadvantage resides in the lack of a compatibility between their hardware/software architecture, which is designed to provide a good average case behavior, and the requirements of real-time applications that specify a correct behavior of the system even under worst–case operating conditions [19]–[21]. Another important issue regarding the predictability of the hard real-time (HRT) systems is related to the unrestricted use of interrupts [22] and of the associated asynchronous mechanisms and tasks. Our current research focuses on developing suitable methodologies and architectures that enable HRT and embedded systems to meet the basic requirements of the critical applications previously stated in this section. The approach is based on studying and integrating the proper models of time, signals, and tasks, emphasizing nonpreemptive operating techniques. This paper discusses the problem of providing a maximum predictability for the critical digital-signal acquisition and processing applications operating under a special-purpose HRT kernel known as hard real-time compact kernel (HARETICK)

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Fig. 1. Task scheduling and execution within the HARETICK kernel.

while interacting with the signals. The proposed solution does not involve any supplemental specialized signal/waveformgeneration hardware to be integrated on the embedded or DSP-based target platforms. It is based, instead, on particular HRT task-scheduling techniques designed for the HARETICK kernel, as described in the following sections. II. HARETICK: A H IGHLY P REDICTABLE HRT O PERATING K ERNEL HARETICK is a single-user multitasking hybrid real-time operating kernel that is designed to provide a maximum predictability for the critical or HRT applications on embedded and DSP-based platforms. “Hybrid real-time” refers to the fact that the kernel provides support for two concurrent task execution environments: the HRT context, for the execution of the HRT tasks in a nonpreemptive manner, and the soft RT (SRT) context, for the execution of the SRT (or regular) tasks in a classical, preemptive, and priority-based manner. The HRT context has precedence over the SRT context. Thus, the HARETICK is able to guarantee that all the tasks scheduled and executed within the HRT context will meet all their temporal specifications, even under the worst–case operating conditions [23]. A homogeneous set of models for time, signals, and real-time tasks has been designed as a basis for the kernel implementation and operation, as well as for the development, programming, and analysis of the real-time applications. Thus, a ModX (executable module) models a periodic modular HRT task, with the complete and firm temporal specifications scheduled and executed in the nonpreemptive (HRT) context Mi ≡ T , P , S, F 

(1)

where P = {P IN , P OUT , P GLB } is the set of input, output, and global parameters of Mi , respectively; S = {S IN , S OUT } is the set of input and output signals, with which Mi interacts; F is the task instruction set (its functional specification); and
 Mi Mi Mi Mi , Tex , Tdl , Tdy , N Mi T = Tpr (2)

represents the set of the temporal parameters of Mi , in their respective order: period, execution time, deadline, delay of execution during each period, and execution count [24]. Due to the nonpreemptive approach of scheduling and executing the ModXs, their interactions with the input signals are accommodated by the periodic polling techniques, taking into account that even the asynchronous signals (events) provide a minimum time interval between any two consecutive occurrences. This interval is then considered when calculating the necessary value for the period of the corresponding ModX [24]. HARETICK provides all the necessary support for the representation and management of the real-time applications and their ModXs once they are loaded on the target platform. ModX execution within the HRT context of the kernel is managed by the system executive, known as the HRT dispatcher (HDIS), in a timely fashion, based on the programmable realtime system clock (RTC). Fig. 1 depicts an example of an application scheduling (upper half of the diagram) and execution (lower half of the diagram) on the HARETICK kernel, focusing on its two concurrent operating contexts: HRT (for ModXs) and SRT (for classical and SRT tasks) [25]. After system startup and initialization, a prescheduling phase is launched [prescheduling HRT scheduler (P-HSCD)] to load the system dispatch table (HDis_Tab) with the ModX executions during the first scheduling cycle of the HRT context. The execution of the HRT scheduler during the prescheduling phase is functionally identical to the normal execution of the HSCD, except that this time, the HRT context of the kernel has not yet been activated. For the scenario depicted in Fig. 1, the layout of the HDis_Tab containing the first scheduling cycle of the HRT context is presented in Fig. 2. The system initialization (SYSINIT) task then finishes the initialization of the HRT context and activates the real-time clock with its associated interrupts (the only type of interrupts allowed in the system). The HRT context is launched at time t0 , as a result of the RTC interrupt, which occurs consecutively to the activation of the RTC timers. First, the prefix component of the executive (PD ≡ HDIS_PRE) saves the SRT context and prepares for launching the first ModX scheduled in the HDis_Tab

MICEA et al.: MAXIMUM PREDICTABILITY IN SIGNAL INTERACTIONS WITH HARETICK KERNEL

(here, Mi ). Before the Mi is actually launched, the PD module sets the RTC-timer compare interrupt to the start time of the next ModX in the HDis_Tab (here, Mj , scheduled at an instance t2 ). Next, the PD decrements the execution-count parameter of the current ModX [the N Mi parameter, see also (2)] if it currently specifies a finite nonzero number of executions for Mi [23], [24]. Mi paThe specified execution time for any ModX [the Tex rameter, see (2)] is calculated based on the worst–case execution time (WCET) [26]–[28] that resulted from the offline schedulability analysis [24], [25], [29], [30]. On the other hand, the effective execution time of the ModXs at run time is often shorter. This difference between the scheduling times and the actual execution times is depicted in Fig. 1, where ModX Mi is scheduled to start at t0 and finish at t2 = t0 + WCETM i , while it actually finishes at t1 < t2 . The same behavior can also be observed for the other ModXs exemplified in Fig. 1. Upon termination, every ModX calls the executive suffix (SD ≡ HDIS_SUF), which decides whether to restore the SRT context and hand over the control (t3 ) if there is enough time remaining until the next execution of a scheduled ModX. Otherwise, the SD enters an empty loop and waits to be interrupted by the RTC (the run idle loop (RUNIDLE) state, which is started at t1 and interrupted at t2 ). The SRT tasks (Li , etc.) are scheduled and executed by the SRT scheduler (SS ≡ SSCD) in a traditional, time-sharing, and priority-based manner. Any HRT scheduling cycle finishes with the termination of the HSCD scheduler (e.g., the time interval t10 − t0 in Fig. 1; see also Fig. 2), which loads the next scheduling cycle into the system HDis_Tab. The kernel behavior, in case of a ghost ModX (Mn , scheduled at t10 ), is also exemplified in Fig. 1. A ModX becomes a ghost ModX when its execution count is decremented to zero at run-time by the system executive (the PD module). In this case, the PD calls directly the SD component of the executive. III. A CHIEVING M AXIMUM P REDICTABILITY IN S IGNAL I NTERACTIONS A. Fixed-Execution ModX Model The ModX model proposed for the HRT tasks allows them to be scheduled and executed anywhere within each of their periods. On the other hand, there is an important class of the HRT applications requiring interactions with the perfectly periodic signals, such as digital-signal acquisition and processing, digital waveform and programmable function generation, synchronous digital communications, etc. Such applications need a particular type of the ModXs, with fixed execution during each task period, called “FModXs.” Fig. 3 depicts an example of a perfectly periodic output signal Sj , with the period τ , which is generated by the ModX Mi . The period of Mi is S Mi equal to the period of the signal Tpr = Tprj = τ , but Mi must Mi ) within each also be executed at the fixed-time instances (Tst,k of its periods. Therefore, Mi becomes an FModX. The temporal parameters of the FModX can be derived from the corresponding parameters of the ModX, as defined in (2),

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Fig. 2. HDis_Tab layout for a scheduling cycle within the HRT context.

Fig. 3. Generation of a perfectly periodic signal.

by setting both its execution delay during each period and its deadline to be separated exactly by the execution time of the ModX  Mi Mi Mi Tst,k = Tst,k+1 = Tst,k+2 = · · · = TstMi (3) Mi Mi Mi Mi Tdy = Tst and Tdl = TstMi + Tex where TstMi is the execution start time of FModX Mi during each period. Formally, the temporal behavior of the FModX can be modeled using the unity step function and modular arithmetic to construct the Mi (t) function, as in the following definition: Definition 3.1: Let Mi (t) be a function defined as   Mi Mi : N → {0, 1}.Mi (t) = σ t mod Tpr − TstMi   Mi Mi (4) − TstMi − Tex − σ t mod Tpr where “mod” is the modulo operator, and σ is the unity step function  1, x ≥ 0 σ : Z → {0, 1}.σ(x) = . 0, x < 0 With a convention that a value of “1” for the Mi (t) function is equivalent to the execution state of the FModX at the time instance t, Mi (t) can be used to model the time behavior of Mi .
Offline analysis of the FModX set of a critical application is a mandatory step to determine its operating feasibility.

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Fig. 4. Example of a fixed execution for a set of two FModXs and the execution-mapping function.

The analysis is reduced to calculating the start time for each FModX, considering as a preliminary condition the fact that the first FModX in the set starts at the moment zero. We assume the usual sorting of the FModX set in a nondecreasing order by the period.

Definition 3.2: We define the fixed-execution mapping of M2 ) as the function M1 over the period of M2 (Tpr  M2 ∆M2 /M1 : 0, 1, . . . , Tpr − 1 → {0, 1} M1 1 D ·Tpr −1

∆M2 /M1 (τ ) = Let M = {M1 , M2 } a set of two independent FModXs, sorted in a nondecreasing order by the period

M1 M2 ≤ Tpr . with Tpr

(5)

According to Definition 3.1, the pair of the FModXs can be modeled with the following functions:    M1 M1  M (t) = σ t mod T − T 1  st pr         M1 M1  − σ t mod Tpr − TstM1 − Tex     M2   − TstM2 M2 (t) = σ t mod Tpr         M2 M2  − σ t mod Tpr − TstM2 − Tex

  M2 . M1 τ + k · Tpr

(8)

k=0

B. Nonpreemptive Scheduling of Two-FModX Sets

   M1 M1  M1 ≡ Tpr , Tex , TstM1  ,  M2 ≡ T M2 , T M2 , T M2 st pr ex

t ∈ N.

We introduce the following notations for the greatest common divider (D) and the least common multiplier (M) of the FModX periods in the schedulability analysis of the FModX set M  M not M2 1 , Tpr D = GCD Tpr  M1 M2 = max δ ∈ N∗ |Tpr mod δ = Tpr mod δ = 0  M not M2 1 M = TLCM = LCM Tpr , Tpr  M1 M2 = min µ ∈ N∗ |µ mod Tpr = µ mod Tpr =0 .

(6)


The fixed-execution-mapping function calculates for any M2 time instance τ within the interval Tpr a value that indicates if M1 is executing (∆M2 /M1 (τ ) = 1) or not, along the entire operation of the set M on the kernel platform. Fig. 4 exemplifies the fixed execution of a set of two FModXs {M1 M2 }, with the following temporal specifications [according to (2), (3) and Fig. 3]:
  M1 M1  M1 ≡ Tpr = 15, Tex = 3, TstM1 = 0
 . (9)  M2 ≡ T M2 = 20, T M2 = 1, T M2 = 4 st pr ex The greatest common divider of the periods of M1 and M2 is D = 5, while their least common multiplier is TLCM = M = 60. TLCM also indicates the time interval for the offline schedulability analysis. The values of the temporal parameters represent the time units, which can be scaled to accommodate the actual application-timing specifications. uti The processor Mi Mi /Tpr )= lization (PU) of the set M is U M = 2i=1 (Tex 0.251 ≤ 1, which satisfies the necessary condition for the uniprocessor schedulability [31]–[34]. Fig. 4 also depicts the diagram of the ∆M2 /M1 function, which maps the execution of the FModX M1 over the period of M2 during the scheduling of M1 and M2 , within the analysis interval ∆M2 /M1 (τ ) =

2

M1 (τ + k · 20),

with τ = 0, 1, . . . , 19.

k=0

(7)

The mapping function divides the period of M2 into four identical intervals of the length D = 5. It can be easily noticed

MICEA et al.: MAXIMUM PREDICTABILITY IN SIGNAL INTERACTIONS WITH HARETICK KERNEL

that there are four time slots left for the execution of M2 within its period: {3–5, 8–10, 13–15, 18–20}. The length of each time slot is equal to two time units. From the specifications of the temporal parameters of M2 [stated in (9)], it follows that 1) execution time of M2 is shorter than the time-slot length and 2) start time of M2 lies within the first available time slot. As a result, the schedulability analysis of this set of the FModXs confirms its feasibility. Unlike the example above, most practical cases of applications do not specify the start times of the FModXs in the set. Therefore, the offline analysis has also the task of calculating the start times of each FModX. In the following, we will demonstrate the main observations drawn in the example above, preparing the formal construction for introducing the nonpreemptive-scheduling algorithm. Theorem 3.1: Let M = {M1 , M2 } be a set of two independent FModXs sorted in a nondecreasing order by the period, as specified in (5) and D ∈ N∗ , which is the greatest common divider of the FModX periods. The fixed-execution mapping of M1 over the period of M2 , ∆M2 /M1 (τ ) is a periodic function of the period D ∆M2 /M1(t0 ) = ∆M2 /M1 (t0 + D)

∀t0 ∈





M2 0, 1, . . . , Tpr −1

. (10)

Proof: From the definition of the fixed-executionmapping function (Definition 3.2) and from (10), we need to demonstrate that  M1 Tpr −1 ∀k ∈ 0, 1, . . . , D   M1 Tpr ∃m ∈ 0, 1, . . . , −1 so that D     M2 M2 M1 t0 + k · Tpr = M1 t0 + D + m · Tpr . (11) 

M1 M2 With the notations Tpr = α · D and Tpr = β · D, with M1 M2 Tpr ≤ Tpr , it follows that α ≤ β, and not

β = γ·α+δ

(12)

where δ ∈ Zα = {0, 1, . . . , α − 1}, and α and δ are relatively prime numbers (GCD{α, δ} = 1). M1 M2 , Tpr } = D. Equation (12) is a result of GCD{Tpr Supposing that GCD{α, δ} = ξ > 1, it would follow that M1 M2 , Tpr } = D · ξ, which contradicts the theorem GCD{Tpr hypothesis. With the notations above and applying the Definition 3.1 for the function M1 (t), (11) to be demonstrated becomes ∀k ∈ Zα = {0, 1, . . . , α − 1} ∃m ∈ Zα

so that

(t0 +k·β ·D) mod (α·D) = (t0 +(m·β +1)·D) mod (α·D). (13)

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Using the modulo-congruency property of two numbers, which states that any a, b ∈ Zn = {0, 1, . . . , n − 1} are congruent modulo n(a mod n = b mod n), if and only if n divides (a − b) [i.e., (a − b) mod n = 0], (13) becomes (t0 + k · β · D − t0 − D − m · β · D) mod (α · D) = 0. (14) Further on, we apply the modular-addition and modularmultiplication properties 

(a + b) mod n = (a mod n+b mod n) mod n ∀a, b ∈ Z n (a·b) mod n = (a mod n·b mod n) mod n

to transform (14) successively, as follows: (((k − m) · β − 1) · D) mod (α · D) = 0 ((k − m) · β − 1) mod α = 0 ((k − m) · β) mod α = 1 ((k − m) mod α · (γ · α + δ) mod α) mod α = 1 ((k − m) mod α · δ) mod α = 1. Because α and δ are relatively prime numbers, there exists a multiplicative inverse µ ∈ Zα , such that (µ · δ) mod α = 1. As a result, we have (k − m) mod α = µ, or m = (k − µ) mod α.

(15)

Thus, for any k ∈ Zα , there is a pair {m, µ} ∈ Zα , so that m = (k − µ) mod α, for which (11) is verified. Moreover, m takes all the values in Zα = {0, 1, . . . , α − 1}, as k scans the
entire set Zα . Corollary 3.1: The fixed-execution-mapping function of M1 over the period of M2 , ∆M2 /M1 (τ ) has exactly νM2 /M1 M2 periods over the Tpr interval, where νM2 /M1 =

M2 Tpr . D

(16)

Proof: The proof is a direct consequence of the Definition 3.2 of the mapping function and of Theorem 3.1. M2 − 1}, i.e., Thus, ∆M2 /M1 (τ ) is defined for τ ∈ {0, 1, . . . , Tpr M2 for Tpr time units, and on the other hand, the mapping function is periodic of the period D. Therefore νM2 /M1 =

M2 Tpr =β D

represents the number of periods of the mapping function over M2 the Tpr interval.
The total number of executions of M1 over the schedulability analysis interval TLCM of the FModX set M [see also (7)] is equal to M2 Tpr TLCM = νM2 /M1 . = M1 D Tpr

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Further on, according to Corollary 3.1, it follows that each period of the mapping function ∆M2 /M1 (τ ) contains exactly one execution of M1 . Based on the fixed-execution-mapping function and its properties discussed above, the problem of a nonpreemptive scheduling of a set of two independent FModXs can be approached. Theorem 3.2: Let M = {M1 , M2 } be a set of two independent FModXs sorted in a nondecreasing order by the period, as specified in (5). Set M is schedulable in a nonpreemptive context, if and only if  M2 M2 − Tex ∃t0 ∈ 0, 1, . . . , Tpr

so that M

2 t0 +T ex −1

∆M2 /M1 (τ ) = 0.

(17)

Proof: According to Theorem 3.2, if the FModX set M is feasible, there must exist at least one interval of the successive values of τ , for which the mapping function ∆M2 /M1 (τ ) is zero. Moreover, this interval, noted with Tx , is greater than or equal to the execution time of M2 M2 Tx ≥ Tex .

On the other hand, according to Theorem 3.1, the fixedexecution-mapping function is periodic, of the period D. As a consequence, Tx cannot be longer than the period of ∆M2 /M1 (τ ) : Tx ≤ D. Following the same theorem and Corollary 3.1, each period of the ∆M2 /M1 (τ ) function maps a single execution of M1 , i.e., over each period of length D, M1 consecutive the mapping function has the value “1” for Tex instances of τ . As a result

τ =t0

M1 Tx ≤ D − Tex .

Proof: 1) Direct implication: If (17) is true, then set M is feasible. If (17) is true, then over the period of M2 , there exists a time interval longer or equal to the execution time of M2 , which starts at the time instance t0 and within M2 , Tex which there are no executions of M1 that can be mapped. M2 − 1] can be As a result, the time interval [t0 , t0 + Tex allocated to schedule the executions of M2 , during each of its periods. Since the executions of M1 and M2 will not overlap with the conditions stated above, during the entire operation of the set M , it follows that there is at least one feasible schedule for the FModXs in the set. 2) Reciprocal: If the set M is feasible, then (17) is true. If M is feasible, then, there exists a schedule for M1 and M2 , so that their executions will not overlap. This is equivalent to the fact that the mapping function of M1 over the period of M2 contains at least one “free” time interval [i.e., an interval Tf for which ∆M2 /M1 (τ ) = 0 ∀ τ ∈ Tf ] that is longer than or equal to the execution
time of M2 . As a result, (17) is true. Corollary 3.2: If the set of the FModXs M = {M1 , M2 } is feasible so that

∃t0 ∈



M2 M2 0, 1, . . . , Tpr −Tex



M

with

(19)

2 t0 +T ex −1

∆M2 /M1 (τ ) = 0

τ =t0

then, TstM2 = t0 . Proof: The proof of the corollary is derived directly from the Theorem 3.2. This corollary permits an algorithmic approach in calculating the execution start time of an FModX, based on the mapping function analysis.
Corollary 3.3: If the set of the FModXs M = {M1 , M2 } is feasible, then 



M1 M2 M1 M2 . Tex + Tex ≤ D = GCD Tpr , Tpr

(18)

(20)

From (19) and (20), the corollary statement is verified.
Corollary 3.3 practically states the necessary and sufficient condition for the nonpreemptive scheduling of the sets of two fixed-execution ModXs: The necessary and sufficient condition, for a set of two independent FModXs to be schedulable in a nonpreemptive context, is that the sum of their execution times must not exceed the greatest common divider of their periods. C. Nonpreemptive Scheduling of Sets of Multiple FModXs Starting from the principles introduced and demonstrated above for the nonpreemptive scheduling of the two-FModX sets, a generalization of the number of independent FModXs in the set can be made. Theorem 3.3: Let M = {M1 , M2 , . . . , Mn } be a set of n independent FModXs sorted in a nondecreasing order by the period    M1 M1 M1  M ≡ T , T , T  1 st pr ex        M ≡ T M2 , T M2 , T M2 2 st pr ex ,  ..   .      Mn Mn  Mn ≡ Tpr , Tex , TstMn

M

Mi with Tpr ≤ Tpr j for i < j.

The set M is schedulable in the nonpreemptive context, if and only if ∀Mj ∈ M.1 < j ≤ n,


M M ∃tj ∈ 0, 1, . . . , Tpr j − Tex j M

tj +Tex j −1 j−1

so that



τ =t0

i=1

∆Mj /Mi (τ ) = 0.

(21)

Proof: The theorem states that the set M is feasible if and only if any FModX Mj ∈ M (j > 1) can be scheduled along with the other previous FModXs, with respect to their sorting

MICEA et al.: MAXIMUM PREDICTABILITY IN SIGNAL INTERACTIONS WITH HARETICK KERNEL

in a nondecreasing order by the period (i.e., the other FModXs with indexes lowerthan j). The operation j−1 i=1 ∆Mj /Mi (τ ) from (21) represents the mapping over the period of Mj of all the FModXs in the M set with periods shorter than or equal to that of Mj , Tpr j . Therefore, the theorem states that, if after this mapping there still remains a free time interval within the period of Mj large enough to accommodate the execution of Mj , this FModX can also be scheduled along with the previous ones. Further on, if this fact is successfully verified for all the FModXs in M , then, the entire set is feasible. The reciprocal implication can be derived in a similar manner. This theorem is a direct result of generalizing Theorem 3.2 for a set of more than two FModXs. The proof is similar to that of Theorem 3.2, considering the case of j = n, i.e., the FModX with the largest period in the set. If Mn can be successfully scheduled along with all the other FModXs in M , then the set is feasible and vice versa.
Corollary 3.4: If the set M = {M1 , M2 , . . . , Mn } is M schedulable according to Theorem 3.3 and (21), then Tst j = tj . Proof: The proof is derived directly from the Theorem 3.3.
Corollary 3.5: If the set M = {M1 , M2 , . . . , Mn } is schedulable, then 
M M Mi Mi +Tex j ≤ Di,j = GCD Tpr , Tpr j , Tex

∀ i, j = 1, 2, . . . , n. (22)

Proof: Assuming a pair of the FModXs, {Mi , Mj } ⊂ M , which do not verify (22), according to Corollary 3.3, Mi and Mj cannot be scheduled together. As a result, the set M containing this pair of the FModXs is not feasible (according to Theorem 3.3). This assumption leads to a contradiction with the corollary hypothesis.
Corollary 3.5 states the necessary condition for the nonpreemptive scheduling of a set of n FModXs: The necessary condition for scheduling a set of n independent FModXs in a nonpreemptive context is that the sum of the execution times of any two FModXs in the set must not exceed the greatest common divider of their periods. As opposed to the particular case of sets with only two FModXs, the Corollary 3.5 provides only the necessary condition for the general case (n > 2). Theorem 3.3 facilitates, in conjunction with the Corollaries 3.4 and 3.5, the algorithmic approach for the offline analysis and scheduling, in a nonpreemptive context of a set M = {M 1, M 2, . . . , M n} of the FModXs sorted in a nondecreasing order by the periods. In the start, the algorithm sets a predefined value for the start time of the first FModX M1 (i.e., the FModX with the shortest period in the set). If there are no other restrictions, TstM1 = 0. Further on, the algorithm analyzes the schedulability of the other FModXs of the set in a consecutive manner, using relation (21). If the equation is verified for the M FModX Mj ∈ M , then, its start time will be set to Tst j = tj , according to Corollary 3.4. The algorithm finishes successfully if all the n FModXs in the set M can be scheduled together.

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Along with the feasibility evaluation of the set M , an another important result of the offline algorithm is the computation of the start times of each FModX in the set, within their respective periods: {TstMi |Mi ∈ M , i = 1, 2, . . . , n}. After the set is found feasible, the application can be loaded (along with the resulting temporal parameters of its tasks, including all the start times for the FModXs) into the HARETICK system to be scheduled and executed online. The online scheduler HSCD implements the fixed execution non-preemptive (FENP) algorithm, which basically begins by scheduling each FModX at its corresponding start time. Further on, the procedure calculates the next start time of an FModX by adding its period to its latest schedule. For instance, the effective start time of the FModX Mi during its kth execution cycle will be Mi Mi i calculated as tM st,k = (k − 1)Tpr + Tst , (k = 1, 2, . . .). The resulting time instances are also chronologically ordered. D. Performance Analysis of the FENP-Scheduling Algorithm The behavior and the main performance parameters of the FENP-scheduling algorithm introduced above have been analyzed and evaluated during a total of over 90 000 tests, using a computer network of 12 workstations at the DSPLabs (http://dsplabs.cs.utt.ro). The tests focus on the evaluation of the success ratio (SR) of the schedulability conditions and of the effective scheduling results for the FENP algorithm, as functions of the following parameters: 1) total number of the FModXs in aset n and 2) PU implied by each FModX set Mi Mi /Tpr ), which must be a value within M , PUM = ni=1 (Tex M a user-specified bounded interval [PUM min , PUmax ]. The main temporal parameters of each FModX in a test set are randomly generated using the uniform and the normal (Gaussian) distributions, taking also into account the necessary conditions for a feasible set, stated by Corollary 3.5 and (22). Therefore, a third parameter has been introduced for the evaluation tests: the “GCD_Seed,” specifying the smallest common divider for all the FModX periods in a set. Based on the user-specified parameters presented above, a complete test randomly generates first a set of the FModXs and evaluates its feasibility. Further on, if the necessary condition has been successfully verified, the FENP algorithm is employed for this set, over the schedulability analysis interval TLCM (i.e., the least common multiplier of the FModX periods). The analysis interval has been bounded to a value of 109 . Some of the most interesting evaluation results are presented in Figs. 5–8, for the sets of 10 and 20 FModXs, and for the different values of the “GCD_Seed” parameter. The “FENPCond” represents the SR of the FENP necessary condition, and the “FENP” represents the SR of the FENP algorithm itself. A set of important conclusions can be drawn from the evaluation tests. First, as expected from the theoretic discussions on the FENP feasibility in the previous paragraphs, the SR increases significantly as the greatest common divider of the FModX periods takes higher values. A high-performance improvement of the FENP algorithm can also be noticed when using the uniform distribution for generating the FModX periods, as compared to the normal

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Fig. 5. FENP evaluation for the sets of ten FModXs and “GCD_Seed” = 10.

Fig. 6. FENP evaluation for the sets of ten FModXs and “GCD_Seed” = 30.

distribution. The main reason is that there are greater chances of finding common dividers with relatively high values when using the periods uniformly distributed over a predefined interval than in the case of the period values concentrated around the central point of the same interval. The FENP algorithm, like the other nonpreemptivescheduling algorithms, provides a maximum operating predictability for the HRT systems and applications but with the expense of a low efficiency and flexibility [29]–[34]. This fact is also confirmed in the evaluation results illustrated above, where the FModX sets with the PU values higher than 0.5 have a very low schedulability ratio (below 10%). A partial solution to the efficiency problem is provided by the HARETICK kernel which uses the remaining PU, from the run-time execution of the HRT tasks (ModXs and FModXs), to accommodate the

execution of the SRT application and system tasks within the SRT context. IV. G ENERATING P ERFECTLY P ERIODIC S IGNALS W ITH HARETICK A set of the HRT applications for generating the perfectly periodic signals have been developed and tested on the prototype version of the HARETICK kernel, implemented on the Motorola DSP56307 EVM platform [35], [36]. The target system has been configured to operate at an internal clock frequency of 32 MHz, while its real-time-clock device applies a scaling factor of 1/4 to the core clock ∆tRTC = 4 · ∆tCLK = 125 ns = 1[RTC](8 MHz).

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Fig. 7.

FENP evaluation for the sets of 20 FModXs and “GCD_Seed” = 6.

Fig. 8.

FENP evaluation for the sets of 20 FModXs and “GCD_Seed” = 30.

Table I summarizes the main kernel implementation parameters. The WCET of the system executive (HDIS) is calculated as WCETHDIS = (WCETHDIS_PRE + WCETTILT ) + (WCETHDIS_SUF + WCETTILT ) + WCETRTC_OVR .

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Therefore, the minimum execution time for any ModX in the system is bounded by the value of WCETHDIS (486 CLK). Each execution of the system executive prefix (HDIS_PRE) and of the suffix (HDIS_SUF) is followed by a call to the TILT routine, which logs the events of the start and termination of each ModX into a special reports buffer. The WCET of

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the HDIS also includes the execution time of the RTC-timer overflow interrupt handler (RTC_OVR), which accommodates the operation of the kernel over the time intervals larger than the capacity of the RTC timer. The online HRT scheduler HSCD implements a fully functional version of the nonpreemptive algorithm for scheduling the ModXs with a fixed execution during their respective periods (FModXs); the FENP algorithm described in the previous section. The application consists of an initialization task App_Init, which is an SRT task, and two FModXs M1 and M2 (see Fig. 9). The two FModXs have the main task of asserting a logical high value on an output line (M1 ) and then resetting it (M2 ). The correct behavior of the inter-ModX communication is studied through the use of some I/O parameters for M1 and M2 .

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TABLE I MAIN IMPLEMENTATION PARAMETERS OF THE KERNEL

TABLE II MAIN IMPLEMENTATION PARAMETERS OF THE APPLICATION

3) The total number of the ModXs in the application set is n = 2. 4) The execution time of the system executive WCETHDIS = 486 CLK must also be added to the final execution time of the HSCD. As a result, the execution time of the HSCD is evaluated as WCETHSCD = 8000 [CLK] = 2000 [RTC].

Fig. 9. Application generating a perfectly periodic signal.

The temporal parameters of M1 and M2 have been calculated during the offline application-analysis phase, taking into account the online scheduler (HSCD) with the following characteristics. 1) The HSCD is also considered as an FModX. 2) The scheduler uses a ModX HDis_Tab (see Table I) of λ = 20 records (equivalent to the total number of the ModX schedules during any scheduling cycle and including the HSCD execution at the end of each cycle).

Table II presents the main implementation parameters of the online scheduler and of the application tasks. Fig. 10 depicts the offline-analysis diagram of the extended FModX set, M S ≡ {M1 , M2 , HSCD}. The PU of the extended FModX set is U M s = 0.311, while the PU of the application FModX set is U M = 0.20. The resulting output signal has a rectangular shape with a period of 375 µs and a pulsewidth of 50 µs. Another important result of the offline schedulability analysis is the set of values calculated for the FModX start times (including the HSCD): TstM1 = 0 [RTC], TstM2 = 400 [RTC], and TstHSCD = 600 [RTC]. Fig. 10 also illustrates the scheduling configuration for the first scheduling cycle, as a result of the HSCD execution in the prescheduling mode (P-HSCD, running within the SRT context, after system initialization, see also Fig. 1): the first schedule for FModX M1 (at an instance of zero [RTC]), for M2 (at an instance of 400 [RTC]), and for the HSCD itself, which will be executed during the HRT context (at an instance of 600 [RTC]).

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Fig. 10. Offline application feasibility analysis.

Fig. 11. Signal measurement diagram.

The application measurement results have been acquired with a high-performance digital-instrumentation equipment, including the HAMEG Analog and Digital Scope “HM1507-3” (see diagram in Fig. 11), and the generated signal has been compared to a periodic signal with identical specifications, synthesized with the HAMEG Programmable Function Generator “HM8130.” The measurement results confirm the theoretical predictions previously discussed regarding the behavior of the online scheduler (P-HSCD and HSCD) and of the periodic signalgenerating application: The upper half in Fig. 12 depicts the starting moment of the application with the executions of the HRT scheduler, on the CH I, and the periodic output signal,

on CH II. The lower half of the figure details the P-HSCD execution-time interval, which is obviously shorter than the following regular executions of the HSCD. According also to Fig. 10, the prescheduling cycle contains three schedules (one for M1 , one for M2 , and one for the HSCD), while the regular scheduling cycle contains 13 schedules (six for M1 , six for M2 , and one for the HSCD at the end of the cycle). The upper half of Fig. 13, shows the periodic output signal (CH II), while a full scheduling cycle is measured on CH I. In the lower half, an execution of the online scheduler HSCD (CH I) and a period of the output signal (CH II) are acquired and measured. The upper diagram in Fig. 14 shows the behavior of the kernel executive HDIS (CH I) for an execution of the FModX M1 , which asserts “1” to the output line (CH II), and then for M2 , which resets the generated signal. The two components of the executive [the prefix (HDIS_PRE) and the suffix (HDIS_SUF)] can easily be observed and measured. The lower half of the figure presents the same executive, with its two modules (CH I) framing the executions of all the ModXs currently running within the kernel: M1 , M2 , and also the HSCD (CH II). The output-signal period is measured on CH II, based on the start times of the corresponding executive prefix, which launches two consecutive instances of M1 . V. C ONCLUSION This paper approaches the problem of providing a maximum predictability for the critical digital-signal acquisition and

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Fig. 12. Measurement of the first P-HSCD and HSCD executions (CH I) and of the application execution with the resulting periodic signal (CH II).

processing applications, emphasizing their interactions with signals. A particular version of the HRT tasks, with a fixed execution within their periods (the FModX), has been detailed as a highly predictable solution for interacting with the signals when using the HRT operating platform provided by the HARETICK kernel (e.g., generating the perfectly periodic output signals). The offline feasibility analysis and the online scheduling and execution of the FModX sets have also been studied in detail. The solution proposed is the FENP algorithm, which has been successfully implemented and tested on an evaluation version of the HARETICK. The measurement results for the signal-generating applications implemented on the HARETICK kernel demonstrate, using high-performance digital-instrumentation equipment, that the output signals are perfectly periodic and confirm the correct operation of the entire system, from the computational and temporal perspectives, according to the design and the offlineanalysis specifications. The results also show a discrepancy in the timing behavior of the scheduling cycles considered during the system/application specification phase as compared to the run-time operation of the application on the system: The specifications consider a HDis_Tab for scheduling the cycle containing 20 FModX executions, and hence, the WCET value for the HSCD scheduler is calculated accordingly. On the other hand, at the run-time, the maximum number of schedules during a cycle does not

Fig. 13. Measurement of a scheduling cycle (CH I) and the resulting output signal (CH II).

exceed 13 (see also Fig. 10). Table III summarizes the timing specification of the application and of the HSCD, as compared to the actual run-time case. The case presented above is part of a larger problem commonly encountered when designing and implementing applications with critical requirements: The timing behavior of all the real-time-system tasks must be specified and analyzed in a pessimistic over estimative manner to provide the necessary predictability of the system. This approach brings about a dramatic decrease in the operating efficiency. A solution to the real-time-system efficiency problem is provided by the HARETICK kernel, which uses the remaining PU from the run-time execution of the HRT tasks (ModXs and FModXs), to accommodate the execution of the SRT (or regular) application and system tasks within the SRT context. Being able to interact with the perfectly periodic signals, the HRT kernel demonstrates its abilities to operate with a maximum predictability—one of our key research objectives. Further development of the nonpreemptive-scheduling techniques on the HARETICK kernel, to accommodate more general sets of the ModXs (e.g., ModXs with program dependencies), and the complete integration and evaluation of the HRT and the SRT execution contexts are some of our main prospects in the field.

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Fig. 14. Behavior of the system executive (CH I) during the execution of M1 , M2 , and HSCD (CH II). TABLE III COMPARISON BETWEEN THE SPECIFIED AND THE ACTUAL TEMPORAL PARAMETERS OF THE FMODXS IN THE SYSTEM

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[32] L. George, N. Rivierre, and M. Spuri, “Preemptive and non-preemptive real-time uni-processor scheduling,” Institut National de Recherche en Informatique et en Automatique, INRIA, France, Rapport de recherche, 2966, 1996. [33] S.-I. Kang and H.-K. Lee, “Analysis and solution of non-preemptive policies for scheduling readers and writers,” ACM Oper. Syst. Rev., vol. 32, no. 3, pp. 30–50, Jul. 1998. [34] J. Jonsson, H. Lonn, and K. G. Shin, “Non-preemptive scheduling of real-time threads on multi-level-context architectures,” in Proc. IEEE WPDRTS, PR, 1999, pp. 363–374. [35] Motorola Inc., DSP56300: 24-Bit Digital Signal Processor: Family Manual, Rev. 3/2000, DSP56300FM/AD, Austin, TX: Semiconductor Products Sector, DSP Division, Nov. 2000. [36] ——, DSP56307: 24-Bit Digital Signal Processor: User’s Manual, Rev. 0/1998, DSP56307UM/D, Austin, TX: Semiconductor Products Sector, DSP Division, 1998.

Mihai V. Micea (M’02–A’02–M’03) received the B.Sc. and the M.Sc. degrees, both in computer engineering, and the Ph.D. degree (cum laude) in computer science from “Politehnica” University of Timisoara, Timisoara, Romania, in 1995, 1996, and 2005, respectively. He is currently a Lecturer with the Department of Computer and Software Engineering, “Politehnica” University of Timisoara, where he coordinates the Digital Signal Processing Laboratories—DSPLabs. His research interests include real-time/embedded multiprocessing systems and their applications in the digital-signal acquisition and processing, digital-telecommunication systems, computer-aided engineering of the digital systems, and multimedia. Dr. Micea is a Professional member of the Association for Computing Machinery (ACM).

Vladimir-Ioan Cretu (M’02) received the Ph.D. degree in computer science from Politechnical Institute of Timisoara, Timisoara, Romania, in 1984. He is now a Professor and Head of the Department of Computer Science and Engineering, Faculty of Automation and Computers, “Politehnica” University of Timisoara. His research interests include real-time and distributed systems, software for data acquisition and processing systems for the electrical machines, instrumentation and measurements, data structures, algorithm design and analysis, embedded systems, and software development processes and techniques. Dr. Cretu is a Correspondent member of the Romanian Academy of Technical Sciences and a Professional member of the Association for Computing Machinery (ACM).

Voicu Groza (M’98–SM’01) received the Dipl.Eng. degree in computer engineering and the Dr.Eng. degree in electrical engineering from Polytechnic Institute of Timisoara, Timisoara, Romania, in 1972 and 1985, respectively. He was a Professor in the Department of Computer Engineering, “Politehnica” University of Timisoara. In 1997, he joined the School of Information Technology and Engineering, University of Ottawa, Ottawa, ON, Canada. His research interests include quantization theory, real-time embedded systems, and distributed intelligent instrumentation. Dr. Groza is the Chair of the Ottawa Chapter of the IEEE Instrumentation and Measurement Society.