MBE HgCdTe on Alternative Substrates for FPA ... - Springer Link

Journal of ELECTRONIC MATERIALS, Vol. 37, No. 9, 2008

Special Issue Paper

DOI: 10.1007/s11664-008-0441-4 2008 TMS

MBE HgCdTe on Alternative Substrates for FPA Applications LI HE,1,2,3 XIANGLIANG FU,1 QINGZHU WEI,1 WEIQIANG WANG,1 LU CHEN,1 YAN WU,1 XIAONING HU,1 JIANRONG YANG,1 QINYAO ZHANG,1 RUIJUN DING,1 XIAOSHUANG CHEN,2 and WEI LU2 1.—Research Center for Advanced Materials and Devices, Shanghai Institute of Technical Physics, CAS, Shanghai 200083, China. 2.—National Laboratory for Infrared Physics, Shanghai Institute of Technical Physics, CAS, Shanghai 200083, China. 3.—e-mail: [email protected]

Results of first-principles calculations and experiments focusing on molecular beam epitaxy (MBE) growth of HgCdTe on the alternative substrates of GaAs and Si are described. The As passivation on (2 · 1) reconstructed (211) Si and its effects on the surface polarity of ZnTe or CdTe were clarified by examining the bonding configurations of As. The quality of HgCdTe grown on Si was confirmed to be similar to that grown on GaAs. Typical surface defects in HgCdTe and CdTe were classified. Good results for uniformities of full width at half maximum (FWHM) values of x-ray rocking curves, surface defects, and x values of Hg1-xCdxTe were obtained by refining the demanding parameters and possible tradeoffs. The sticking coefficient of As4 for MBE HgCdTe was determined. The effects of Hg-assisted annealing for As activation were investigated experimentally and theoretically by examining the difference of the formation energy of AsHg and AsTe. Results of focal-plane arrays (FPAs) fabricated with HgCdTe grown on Si and on GaAs are discussed. Key words: Molecular beam epitaxy (MBE), HgCdTe, alternative substrates, uniformity, focal-plane arrays (FPAs), first-principles calculations

INTRODUCTION The demand for HgCdTe focal-plane arrays (FPAs) is moving toward larger formats with small pixel sizes and multicolor sensing capabilities.1 Molecular beam epitaxy (MBE) for HgCdTe has been recognized as a promising technique for the requirements of FPAs. GaAs,2 Ge,3 and Si4 have been used as emerging alternative substrates of choice for growth of HgCdTe. They have potential advantages over the conventional lattice-matched substrates of Cd0.96Zn0.04Te in terms of large area, good crystal perfection, low cost, less impurity contamination, and better mechanical strength. The HgCdTe/Si system has superior mechanical strength being compatible with the standard Si processing line, and it is thermally compatible with the flip-chip bonded CMOS readout circuits. FPA (Received October 24, 2007; accepted February 29, 2008; published online May 31, 2008)

reliability under temperature cycling is expected to be improved by employing HgCdTe/Si. On the other hand, because the lattice mismatch in the HgCdTe/ GaAs system (14.6%) is smaller than that of HgCdTe/Si (19.3%), the growth of HgCdTe on GaAs is less difficult. Obviously, the growth of HgCdTe on Si presents a great technical challenge in terms of obtaining crystals of comparable quality to that grown on GaAs. As the growth for HgCdTe is developing toward larger size, and meanwhile has to endure the lattice and thermal mismatches to the substrates, crystal quality, surface defects, uniformity across the wafer and the capability to control the growth parameters precisely are becoming important issues. Since the report by O. Wu et al.5 of successful incorporation of As by using Cd3As2, extrinsically p-type doping by As has remained an important topic for achieving multicolor or high-performance FPAs as it has been obstructed by complications derived from the amphoteric behavior of As for a Te-rich growth 1189

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He, Fu, Wei, Wang, Chen, Wu, Hu, Yang, Zhang, Ding, Chen, and Lu

mode6 and the low growth temperature at which As may form some defect complexes.7 In an attempt to respond to these technical challenges, a study combining theoretical and experimental efforts devoted to understanding the fundamental mechanisms and to improving the material quality of MBE-grown HgCdTe on alternative substrates of GaAs and Si has been carried out at the Shanghai Institute of Technical Physics, and some of the results are presented in this article. EXPERIMENTAL AND THEORETICAL METHODS Growths were performed in a Riber 32P system. Three-inch wafers of (211) B GaAs and (211) Si were employed as substrates. To reduce the lattice mismatch between HgCdTe and the substrates, a buffer layer consisting of ZnTe and CdTe was grown prior to the HgCdTe nucleation. Compound and elemental sources of CdTe, Zn, Te, and Hg were employed for the growth of CdTe, ZnTe, and HgCdTe. Conventional effusion cells of As and In were employed for p-type and n-type doping, respectively. The mole fraction (x value) and the thickness of Hg1-xCdxTe were evaluated by the infrared Fourier transmission at 300 K. The crystal quality was assessed by using high-resolution x-ray diffraction (Philips XÕPert Pro MRD), high resolution (10 lm) x-ray Berg-Barrett reflection topography (BeDe Bescan) as well as the density of dislocations decorated by etch pits (EPD) for CdTe8 and HgCdTe.9 Features of various surface defects were studied by using scanning electron microscopy (SEM), energy dispersive x-ray fluorescence spectroscopy (EDX), and atomic force microscopy (AFM). The doping concentration of As was quantitatively analyzed by using a Cameca IMS-6f secondary-ion mass spectrometer (SIMS) with an O2+ ion beam at 15 keV. The relative sensitivity factors (RSFs)10 for elements in HgCdTe and CdTe matrices were obtained by using reference samples of a similar composition implanted by As+ at different energy values and dosages. The electrical properties were evaluated by temperature-dependent Hall measurements in a van der Pauw configuration in a temperature range of 300 K to 12 K at a magnetic field strength of 0.2 T. FPAs were fabricated by employing a flip-chip process with In bumps to interconnect the detector arrays to Si readout chips. First-principles calculations were performed for examining the bonding configuration of As passivation on (2 · 1) reconstructed (211) Si, CdTe nucleation on clean and As-passivated Si,11 and As impurity incorporation in HgCdTe.12,13 In the calculations for As passivation on Si, a nine-layer slab, ˚ vacuum region, was used to separated by a 10 A model the Si(211) substrate. Each layer contained and two along ½111. four Si atoms—two along ½011 The dangling Si bonds at the bottom of the slab were saturated with H atoms. The energy cutoff

for the plane waves was set as 270 eV. Here, 2 · 2 · 1 k-points were used for the MonkhorstPack k-point sample. The two lowermost Si layers and the additional H layer were fixed. The As incorporation in HgCdTe was calculated by evaluating the relaxations, bonding mechanism, and the electronic structure of As in HgCdTe or HgTe by constructing a 2 · 2 · 2 supercell (SC) with a total of 64 atoms; for example, Hg0.5Cd0.5Te consisted of an eight-atom quasi-zincblende crystal structure of unit cells (each unit cell containing four Te atoms, two Hg atoms, and two Cd atoms). The defect system was modeled by placing an arsenic atom at the center of a periodic SC. The details of the calculation method can be found elsewhere.11–13 RESULTS AND DISCUSSION As Passivation of Si Surface Employing the atoms of group III or V to modify Si surfaces has been known for decades as an effective way to control the surface polarity of II–VI compounds grown on Si.14 The effect was checked by total electron counting at interfaces for the (111) or (100) orientation, however, the microscopic detail or the mechanism for the passivation has not been well established. In this work, As passivation was performed after oxide desorption of (211) Si at 850C. It was confirmed that the passivation could inevitably initiate the nucleation of CdTe or ZnTe having a B surface. Our theoretical calculations found that the most stable structure of the surface could be obtained when the terrace and trench Si atoms were replaced by As atoms, as shown in Fig. 1. The bond length and bond population of the surface bonds of a clean surface (Fig. 1a) are compared with that of the Aspassivated surface (Fig. 1b). The As passivation enhances the reconstruction of the Si surface. The ˚ to 2.19 A ˚ . The E1–E2 bond shrinks 8.4% from 2.39 A passivation weakens the distortion difference of the surface atoms as well. The edge atoms move downward to form sp hybridization, so the six atoms (T1, T2, E1, E2, 5, 6) are not in the same plane after passivation. The Tr1 and Tr2 As atoms in the perpendicular direction partially recover their normal bonding forms (sp3 hybrid bonding) in solid Si. In our calculation, except the E1–E2 bond, other surface bonds parallel to the ½111 direction are increased by 4% on average compared with those of the clean surface. For bulk material, the mismatch between Si and CdTe is 19.3%. After the surface reconstructs, the mismatch will increase to 25% because of the shrinkage of the Si surface bond length. However, the mismatch will decrease to 18% after As passivation. The passivation of As did not change the periodic arrangement of atoms in clean Si surfaces; it agreed with our experimental observations15 by reflective high-electron energy diffraction (RHEED). The possible absorption modes for one-monolayer CdTe deposition were calculated.11 The process was

MBE HgCdTe on Alternative Substrates for FPA Applications

Fig. 1. Calculated bonding configurations of the surface of (211) Si: (a) the (2·1) reconstructed clean surface, (b) the partially As-passivated surface, (c) the A-face nucleation mode for the simulated one-monolayer CdTe deposited on the partially As-passivated (211) Si substrates and (d) the B-face mode.

found to be different from that of independent Cd or Te atoms. As a result of passivation, As atoms partially saturated the dangling bonds of the Si surface and the Te atoms could only bond to the remaining nonpassivated edge atoms. The Cd atoms could bond to edge Si atoms, however the strong repulsion between As and Te prevented them from bonding, which made the A-surface inaccessible, as shown in Fig. 1c. The Te therefore made it possible for the Cd to be adsorbed by the passivated region. The favorable conditions for the selective growth are caused by As, which saturates the dangling bonds and weakens the surface states to cause the existence of different Si and As atomic regions on the substrate surface. This prohibits the A-face CdTe, but is helpful for the B-face growth (Fig. 1d). Our analyses using the total electron counting confirmed the electron count match for the configuration. Crystal Quality It was found that twinning was easily involved in the epilayers grown on largely lattice-mismatched substrates of either GaAs or Si. To prevent the epilayers from twinning, a procedure15 that consisted of the deposition of a thin layer of ZnTe at a low temperature on the As-passivated Si or clean GaAs and subsequent high-temperature annealing was employed. It was confirmed that the low-temperature deposition of a thin layer of ZnTe was the

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key step to obtaining twin-free epilayers by restraining the migration of surface atoms. The density of threading dislocations in CdTe buffer layers is one of the main factors impacting the quality of HgCdTe. In a highly lattice-mismatched system, the threading dislocations are promoted by the misfit strain16 at the coincidence interface17 (a two-layer composite between the substrate and the epilayer). The density of threading dislocations can be reduced by modifying the coincidence interface to assist strain relaxation. On the other hand, lattice tilting was usually observed at the interfaces of highly lattice-mismatched systems, and the relation between epilayer tilting and misfit strain deserves clarification. As shown in Fig. 2a, the epilayers grown on lattice-mismatched (211) substrates always show some lattice tilting. The surface index of the epilayers deviates from the (211) toward (311) around CdTe ½011//Sub ½011, deviation is proportional to the misfit strain. The result suggests that the tilting is inherently driven by misfit strain, and it scales linearly with the degree of misfit. In an attempt to reduce dislocations by modifying the interface, a series of CdTe samples were grown on (211) Si and (211) B GaAs substrates misorientated by 1 deg to 10 deg towards the [111] direction; the results are summarized in Fig. 2b. It was found that the full width at half maximum (FWHM) values of the x-ray double-crystal rocking curve measurements (XDRC) decreased to a saturation value as the tilt angle between the (211) planes of the CdTe epilayer and Si decreased from 4.2 deg to 2.75 deg. No remarkable change in the FWHM values was observed in the CdTe grown on (211) GaAs, suggesting that the modification was not effective or significant for less-mismatched systems such as CdTe/GaAs. This explains the saturation in the FWHM values as observed in CdTe/Si, which occurred when the strain was reduced to a certain value below which the modification became less effective. The result indicated that the misfit strain could be reduced by employing misorientated Si substrates as manifested by the angle of lattice tilting. This was further confirmed by comparing the crystal quality of the CdTe epilayers grown on (211) misorientated Si with that grown on (211) standard GaAs, as shown in Fig. 3. The values of the XDRC FWHM or EPD obtained on CdTe grown on misorientated Si were reduced to a very similar level to that grown on GaAs. The samples with the (211) planes of CdTe tilted at an angle of 2.75 deg with respect to that of Si exhibited the smallest FWHM value. The tilt angle roughly corresponded to a reduced lattice misfit of 13% as scaled by Fig. 2a. The decrease in the threading dislocations with increasing thickness of CdTe is due to dislocation cancellation driven by the residual stress.18,19 In contrast, the CdTe grown on standard (211) Si showed larger values of EPD (a factor of 5) or FWHM.

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Fig. 2. Lattice tilting of epilayers: (a) dependence of the tilted angle between the (211) planes of CdTe and standard (211) substrates with lattice mismatch, and (b) the dependence of the FWHM value of (422) XDRC on the tilt angle between the (211) planes of CdTe epilayers and the (211) misorientated substrates. The insert in (b) shows the tilting configuration.

Surface Defects

Fig. 3. Dependences of the FWHM value of (422) XDRC and EPD of CdTe epilayers grown on GaAs and Si with the epilayer thickness. The data points of FWHM versus depth were obtained from the epilayers of individual growth runs; EPD points were obtained either from epilayers of individual growth or by etching the samples to different depths.

By refining the substrate misorientation as well as the optimal growth conditions, XDRC FWHM values in a range of 50 arcsec to 60 arcsec (corresponding to EPD values of 9 · 105 cm-2 to 30 · 105 cm-2) were routinely obtained on CdTe grown on Si and GaAs. HgCdTe of different compositions was subsequently grown on the CdTe buffer layer via a graded-composition region to reduce the lattice mismatch (0.2%) between CdTe and HgCdTe. The FWHM values were observed to be in a range of 55 arcsec to 75 arcsec (EPD values of 1 · 106 cm-2 to 5 · 106 cm-2) for growth runs.

The surface defects are directly responsible for the operability of FPAs.20 Voids or craters and hillocks are usually observed on the HgCdTe surfaces; they arise either from improper substrate preparation or growth conditions. The origin of some typical defects in HgCdTe as well as their relation with growth conditions were clarified previously.21 It was identified that, among the observed defects of type 1–5, defect types 1–3 were the most problematic for FPA applications, and the optimal growth window for obtaining a good morphological surface was very narrow. These defects were either substrate or growth related. The defects type 1 and type 2 were related to the Hg-deficient condition; they were large voids from 10 lm (type 2) to 30 lm (type 1) in size, and facets could be identified at the edges. Type 3 defects were the most common, typically 3 lm to 7 lm in size for epilayers 10 lm thick; they are voids or complexes of voids and hillocks with a circular-like smooth boundary at the surface. By a careful effort applied to improve the key processes from substrate preparation to the growth parameters, our accumulated data showed that the densities of the surface defects (‡2 lm) were reduced to levels below 300 cm-2 and 500 cm-2 for HgCdTe grown on GaAs and Si, respectively. Impurity-Related Defects We have observed that the density of type 3 defects could occasionally remarkably exceed our screening limit even if both the substrate preparation and the growth conditions were correct. It was


found that in these unusual samples the void defects were 2 lm to 5 lm in size, gathered as clusters in the center region of wafers, and in the clusters hillock defects of 8 lm to 10 lm were often observed. The hillock defects were actually complexes of voids and hillocks; the agglomerates of particulates inside the void were higher than the film surface. Cross-sectional scanning electron microscopy (SEM) images showed that the defects nucleated inside the HgCdTe epilayer, as shown in Fig. 4a. O, Zn, and Se were traced by EDX analyses only to the regions at the bottom interface between the defects and the underlying HgCdTe. Obviously, the defects were related to impurities. The Hg source is susceptible to impurities because it is operated at a low temperature, and consequently it is more easily contaminated. The impurities melted in Hg can evaporate out easily with Hg during growth. To verify the impurities in Hg, the experiments were performed by regrowing CdTe at 290C on a Hg-exposed clean CdTe. In some cases, hillock-like defects in the surface of regrown CdTe were identified, as shown in Fig. 4b. The

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cross-sectional observations confirmed that these defects nucleated at the exposed interfaces. This procedure unambiguously eliminates the complexity of growing HgCdTe in which various mechanisms of defect formation may account for and make only the effect of impurities observable. We speculate that some of the void defects observed in HgCdTe epilayers may arise from impurities in the Hg beam fluxes. A careful procedure for Hg loading and outgassing was then specified. Defects in CdTe Defects in the surfaces of CdTe buffer layers can propagate into the subsequently grown HgCdTe and consequently impact on the quality of HgCdTe. Typical defects observed in CdTe surfaces are shown in Fig. 4c–f. The defects shown in Fig. 4c, d are often observed in CdTe grown on Si, while the defects in Fig. 4e, f are observed on CdTe grown on both Si and GaAs substrates. For simplicity, we denote the defects shown in Fig. 4c as S1 and those shown in Fig. 4d as S2. S1 defects are attributed as originating from the surface treatment of the Si substrates.

Fig. 4. SEM views of (a) the defect nucleated inside the HgCdTe layer, (b) the hillock-like defect nucleated at the interface of regrown CdTe/Hgexposed CdTe, (c) the defects (S1) speculated as originated from the surface treatment of Si, (d) defects (S2) frequently observed in CdTe/Si, (e) and (f) defects related to the cation-rich growth conditions for CdTe.

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S2 defects are frequently observed defects on CdTe/ Si; they are triangular voids with two sides along ½111 and ½011, respectively. The size is typically 2 lm to 4 lm depending on the thickness of CdTe. Some void defects having edges protruding along ½111 in the subsequently grown HgCdTe grown on Si were found to be related to the S2 defects. Some authors attributed it either as originating from Zn-rich growth conditions for ZnCdTe growth on Si,22 or as being related to the growth temperature of CdTe.23 We have performed a series of growths of CdTe and ZnTe on Si and GaAs with varying parameters of misorientation angles, nucleation method of either MBE or migration-enhanced epitaxy (MEE), growth conditions (temperature, thickness, and flux ratio from cation to anion), and annealing temperatures and durations. The results showed that the S2 defects were only found in CdTe grown on Si, and that the density of S2 defects had no unambiguous relation to the growth conditions or method used. The faceted nature of the defect suggests that S2 defects should not originate from dust particles or contamination in the substrate surfaces. The effect of As passivation is subject to further

study. The defects shown in Fig. 4e, f were found to be related to the cation-rich growth conditions for CdTe by either an improper ratio of cation to anion or improper growth temperature. In the extreme cases, the defect density could reach 105 cm-2, which made the epiwafers appear cloudy to the naked eye. These defects can be completely eliminated by optimizing the growth temperature. Lateral Uniformity A stringent requirement for large-format FPAs is lateral uniformity of the material properties of crystal quality, surface defects, and composition. Examples of the FWHM mapping on 3-in epiwafers of HgCdTe are shown in Fig. 5. The slightly larger FWHM values observed on HgCdTe grown on Si are due to the thinner CdTe buffer of this particular sample, while the slightly larger deviation for HgCdTe grown on Si as compared with that grown on GaAs suggests that some subtle processes for the CdTe starting layers have to be further elaborated. Figure 6 shows mapping data for the density of surface defects in the 3-in epiwafer of HgCdTe grown on GaAs. The size distribution of defects is

Fig. 5. Distributions of the FWHM values of (422) XDRC of (a) HgCdTe grown on Si, and (b) grown on GaAs.

Fig. 6. Distributions of surface defects observed by scanning 385 points on a 3-in HgCdTe grown on GaAs: (a) distribution of defect sizes; the figures denotes the number of defects counted, and (b) radial distribution of the density of surface defects. The dot-dashed line in (b) shows the mean value of the density of surface defects over the wafer. The radial distance is with respect to the wafer center.


shown in Fig. 6a and the radial distribution of defect density in Fig. 6b. The total number of defects is 5529, with a mean defect density of 156 cm-2. The largest amount of defects are 2 lm to 12 lm in size, the smaller defects (