Microprocessors and f nput/Output Interfaces

The B0BBand 8086

Microprocessors and TheirMemoryand fnput/OutputInterfaces INTRODUCTION fiom a Up to thispointin thebook,we havestudiedthe 8088and8086microprocessors point instruction how of view. We have covered their software architectufe, set, software programs in assenbly language, and found that the 8088 and to wdte,execute, anddebug point of view. This is no! lrue of the hardware 8086were identicalfrom the software Now we beginexamining the architectures of the8088and8086microcomputer systems. point view In this chapter, we cover of 8088 and 8086nicrocomputel from the hardwarc the 8088/8086\ signal interfaces,memory interfaoes,inputoutput interfaces,and bus cycles.The chaptersthat fbllow coverotherhardwareand intedacingaspectsof these This chapterincludesthe followingtopics: Focessors. 8.1 8088and8086Microprocessors andMa.{imum-Mode Systems 8.2 Minirnum-Mode InterfaceSignals 8.3 Min;rnum-Mode 8.4 Maxinum Mode InterfaceSignals 8.5 Elecirical Characteristics 8.6 SystemClock 8.7 Bus CycleandTime States 8.8 Hadware organizarionof ihe Memory Addres$Space 8.9 AddressBus StatusCodes

3t5

8.10 Memory Control Signals 8-11 ReadandWrite Bus Cycles 8-12 Memory InterfaceCircuiis 8.13 ProgrammableLogic Arrays 8.14 Typesof Input/Output 8.15 IsolatedInput/Outputlnterface 8.16 Input/OutputData Transfers 8.17 lnput/Ou.putInstructions Bus Cycles 8.18 Input/Ouiput

a 8.1 8088 AND 8086 MTCROPROCESSORS Tte 8086, amounced in 1978, was tLe filst 16-bit miqoprocessorintroducedby Intel Corporation.A secondmemberof rhe 8086 family, fte 8088 midoprocessor followed it in 1979.The 8088 is tuny softwarecompatiblewilh its predecessorthe 8086. The differencebetweenthesetwo devicesis in their hardwarearch;tecture.Justlike the 8086.the 8088is intemally a lGbit MPU. However,extemally the 8086 hasa 16-bit databus,and the 8088 hasan 8-bit databus.This is the key hardwareditrerence.Both deviceshave.he ability 1oaddressup to lMb)te of nemory via their 20-bit addrcssbuses.Moreover they can addressup to 64K of b'te-wide irput/output ports. The 8088 and 8086 are borh manufactued ]usittqhish-petomance metul oide semiconductor(HMOS) technolog), and the circuitry on their chips is equivalent to apFoximately 29,0,mtransistors.They arc housedin a 40 pin dual in line package.This packagecanbe mountedinto a socketthat is solderedto the circuit boardor haveits leads inserteddrough hole.sin the board and soldered.The signalspinnedoui to eachlead arc shownin Figs. 8-1(a) and (b), respectively.Many of iheir pins have multiple funclions. For example,in lhe pin layout diagrarnof the 8088, we see thal addressbus lines A0 drough A? and databus lines Do throughD7 are multiplexed.For this rcason,theseleads arelabeledADo throughAD?. By nubiplered we meanthat the samephysicalpin canies an addftss bit at one time and the databit at anothertime.

EMMPLE8.I At what pin location on the 8088's packageis addressbit A16 output?With what other signal is it multiplexed?What tunction do€sthis pin serveon the 8086?

Solution Looking at Fig. 8-1(a), we find that the signal,t16 is l()catedat pin 38 on the 8088 and that it is multiplexed wirh signal L. Fipre 8 1(b) showsus that pin 38 servesthe same functions on the 8086.

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Mjnimum-Mode an ci MaximumMooesystems

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The signalsof the 8088 microprocesr;or commonto both modesof operation,those uniqueLominimurnmodednddroseuniqu€I to maximummode,are lisLcdnr Figs. 8 2(a). (b), xnd (c). resp€ctively. Hefewe lind the name,tunclion, and type lor each signal.For the signalRD is in ihe commong roup. lt tunctionsas a rcxd control ouiput and example, is usedlo signalmemoryor I/O deviceswl 1enthe 8088'ssystembusis setup to readin data. Moreover, note that the signals ho ld reqnest (HOLD) and hold achowledge (HLDA) a.reproducedonly in the minimun r-modesystern-If the 8088 is set up for marimum mode,they arc replacedby the reque svgrant bus accesscontrol lines RQ/GToand RQ/GT,.

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334

The 808 rg and 8086 Microprocessors Chap. I

EMMPLE8.2 Which pins provide ditrerentsignalfunctionsin the minimun-mode 8088and rninimunnode 8086?

Solution Conparingthe pin layoutsofthe 8088and8086in Fig. 8-i, we find thefbllowing: 1. Pins 2 ihrough 8 on the 8088 are addresslines Ara tbroughAs, but on the 8086 they are address/dalalines ADia throughADs. 2. Pin 28 on rhe8088i' lhe lO,M ourpu,andon $e 8080iri5 lhe M,4-0ourpur. 3. Pin 31 of rhe8088rs $e SSOouFur.aodon lhe 808brhicpin cupplie.rheBHE/\? output.

A 8.3 MINIMUM-MODEINTERFACE SIGNATS When minimum modeoperationis select€d,the 8088 or 8086 itself plovides a[ rhe con, aol signalsne€dedto implementthe memory and I/O interfaces.Fignres 8-3(a) and (b) show block diagramsof a minimum-modeconfigurationof the 8088 and 8086, resp€ctively. The minimum-mode signals can be divided into the following basic groups: address/data bus,status,control. intenupt, and DMA.

Address/DataBus Let us first look at the address/data bus. In an 8088-basedmicrocomputersysten, theselines sene two turctions. As n adnrcssbus, they are usedto carry addressinfor nation to the memory and l/O ports. The addrcssbus is 20 bits long and consistsof signal lines A0 tbroush Are. Of ihese.Are representsthe MSB and A{r the l-SB. A 20-bit addressgivesthe 8088 a lMbyte memory addressspace.However.only addressLinesA0 throughAr5 are usedwhen accessingI/O. This givesthe 8088 an independentyO address spacethat is 64Kbytesin length. The eight ddta ,rr lines D0 though D? are actually multipiexedwith addresslines A0 tbroughA7, respectivell For this reason.they are denotedasADo tlrough AD7. Data LineD7 is the MSB in the byte of data and D0 the LSB. Wben acting as a databus,rhey carry readwrite data for memory input/output data for l/O devices,and interrupttype codesfrom an interruptcontroller Lookine at Fig. 8-3(b), we seethat the 8086 has 16 databus lines insreadof 8 as in the 8088.Data fines aft rnultiplexedwith addresslines Ao tbroughAr5 and aft theretore denotedasADo throughADr5.

5ec. 8.3

Minimum-ModelnterfaceSignals

339

ADo-AD?.A16/S3-Ao/sa !trTA TEST

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Status Signals The foul most significantaddresslines,Are drough A16of both the 8088 atrd8086 are also multiplexed,but in lhis casewilh stdt r stgrals 56 through53. Thesestaos bits are output on the bus at the sametime thal dataare hansfered over the other bus lines. Bits Saand Sr togetherform a 2 bit binary codethat identifieswhich of the intemal segment registerswas usedto geneBtethe physical addressthat was output on the addrcss bus during the cunent bus 'Jycle.The,sefour codesand the regisren they representare shownin Fig. 8-4. Note that the code SaS3= 00 idenrifieslhe extra segmentrcgister as the sourceof ihe segmentaddrcss. Stalusline Sj rcflectsthe statusof anotherinternalchrmcteristicof the MPU- It is the logic levelof theintemalintempt enableflag.The statusbir 56is alwaysat the0 logic level.

Control Signals T\e contml siqnals arc ltrovided to suppod the memory and I/O interfacesof the 8088 and 8086. They control functions such as when the bus carries a valid addrcss, which direcdon data are transferredover lhe bus. when valid write data are on the bus. andwhen to put readdataon the systembus.For example.addrcsslatch etnble (ALE\ is a pulse to iogic 1 that siglals extemalcircuitry when a valid addrcssis on the bus.This addresscan be latchedin extemrl circlitry on the I to 0 edgeofthe pulse at ALE. _ Using the IO/M (lo/nenoO line. D' R (data transmit/receiye\line, and SSO (statusoutput) line, the 8088 signalswhich type of bus cycle is in progressand in which directiondataare to be tsansfenedoverthe bus.The logic level of IO/M tells extemalcncuiry wherler a memory or UO trdnsferis taking placeover the bus.lngic 0 at this output signalsa memory operalion,and logic I signals an VO operatioi. The direction of datatansfer over the busis sienaledby rne logic level ouFut at DT/R- When this line is logic I during the datatransferpan of a bus cycle, the busis in the transmitmode.There fore. dataare either written into memory or output to an UO device.On the other halrd. logic 0 at DT,R signalsthat drc bus is tu the rcceivemode.This conespondsto .eading datafmm memory or inpur of dataftom an input porl ComparingFigs. 8 3(a) and 8 3(b), we find two differencesbefv/e€nthe minimummode8088 and 808b microproce,ssors. Fi^L rhe 8086 s memoryno conFotrMI-Or 'isnal is the complementof the equivalentsignaloflhe 8088.Secondthe 8088\ SSOstatussignal is rcplacedby bdnt /,ish e able (BtE\ M tre 4086.l-ogic 0 on tlis line is usedas a mernoryenablesignalfof r}le nosr sienmcantb)'te har of the databus, Ds drough Drs. This line also carriesstatusbit 57. Sec-8.3

Minimum-ModelntedaceSionals

t4l

The si$als r.€dd(RD) and n/itu (WR) indjcate that a readbuscycle or a write b[s c)cle. respeclel). i, in progress. The MPU suilchesWR-ro log;c0 ro 5ignalexremal devicesthat valid write or outputdataare on the bus On the otherhand,RD indicatestl|i fte MPU is perforning a readof dataoff the bus.During rcad operations,one otherconaol signal,DEN (data €r.rbla), is also supplied.It enablesextemaldevicesto supplydaE to the miuoprocessor. One other control signalinvolved with the memory and I/O interface,the READY signal,can be usedto insert wait statesinto the bus cycle so ihat ir is extendedby a num ber of ciock periods-Th;s signalis providedby way of an extemalclock generatordevice andcan be suppiiedby tbe memoryor I/O subsystemto signal the MPU whenit is ready io pemit the datatsansferto be completed.

InterruptSignals The keyinterrupt interface signals arc intettupt r€q&€rt (INTR) and intenwt acknowledSe(INTA). INTR is an input to the 8088 and 8086 that can be used by an externaldeviceto signalthat it needsto be seNiced.This inpur is sampledduring the final clock period of eachtfftroction acquisition cyck. Logic I at INTR representsan active interrupt request.Wlrcn the MPU recognizesan interupt request,it indicatesthis fact to exrematcircuirs with pulsesto logic 0 at the INTA outpur. The TEST input is also relatedto the exiemal interruptinterface.For example,execulion of a WAIT instructioncausesthe 8088or 8086to checkthe logic level at the TEST input. If logic I is found at this iDput,the MPU suspendsopention and goesinto what is known as the idle rtdt?. The MPU no.longerexecutesinstructions;instead,ir repeatediy checksthe logic level of the TEST input waiting for its transition back to logic 0. As TEST switchesto 0, executionresumeswith the nexi instruction in the program. This feanre can be used to synchonize the opemtion of lhe MPU to an eveni in exremal hardware. There are fwo more inpuis in the irtenupt inretface: nonnaskable interrupt (NMl) and,'€rer(RESET).On the 0{o-1 t ansitionof NMI, controlis passedto a ronmaskableintenupt serv;ceroutineat completionof executionof the currentinstruc, tion. NMI is the interrupt requestwith highesr pdority and cannot be maskedby software.The RESETinput is usedto providea ha.dwareresetfor the MPU. Switchirg RESETto logic 0 initializesthe intemalregistersof ihe MPU andinitiatesa resetser

DMA InterfaceSignals T\e diect memory dcc?rr (DMA) inreface of the 8088/8086minimum-mode microcomputersystem consists of the HOLD and HLDA signals. When an extemal devicewantsto take control of the systembus, it signalsthis fact io drc MPU by switcb ing HOLD to the 1 logic level. For €xample,when the tlOLD inpur of the 8088becomes active, it enten the hold state at the completion of the cnrrent bus cycle. When in the hold state,signallinesADo throughAD7.As tbroughAr5,A16/5rthroughArr/56,SSO,

342

The 8088 and 8086 MicroDrccessofs ChaD.8

IOA4. DT/R, RD, WR, DEN, and INTR are all put into tlle high-Z state.The 8088 signals exremaldevices.hat it is in this stateby switching its HLDA output to the I logic level.

8.4 MAXIMUM-MODEINTERFACE SIGNAIS Wlen the 8088 or 8086 microprocessoris set for the maximum-modeconfigfation, it producessignalsfor implelnentlng^ nuhprccessor/coptuc.ssorslstem enrimnment-By nulnprccessot eNionnen. we mean that multiple microprocessorsexist in the system and that eachprocessorexecutesits own proglam. Usually in this t)?e of systemenvironment, some systemresouces arc commonto all processors.They are caled gldb"l Effu'.er. There are also other resomcesthat are assignedto specitrcpmcessors.These dedicatedresourcesare kt(t\\rn as local or pilate resourcesrn the maximun-mode system,facilities are provided for inplementing allocation of global resourcesand passingbus conFol to other microprocessorssharingthe systen

8288 BusController;BusCommandsand ControlSignals Looking at &e maximum-modeblock diasramin Fig. 8-5(a), we seethat the 8088 doesnot directly provide all the s+nak rnat arerequnedto control ft€ memory I/O, and intenupt inlerfaces.Specifically, the WR, IO/M, DT/R, DEN, ALE, and INTA signals are no_longerproducedby the 8088. Instead,it outputs a statuscode on three signals lines. S0.Sr, and S,, prior to the inidation of eachbus cycle. This 3 bit b!..rrtdt r co./e identifieswhichtype ofbus cycleis to follow. SrSrS0areinput to the extemai,rs cortrollel device,the 8288, which decodesthen to ideniry fte type of MPU bus cycle. The block diagramandpin Iayoutoflhe 8288 are shownin Figs- 8 6(a) and (b), respectively. In response.the bus controller generatesthe appropriatelytimed commandand control sisnals. Figure 8-7 showsthe relationshipbetweenthe busstatuscodesandthe typesof bus cycles.Also shown are the output signalsgeneratedto tefl extemal cncuitry which type of bus cycle is taking place.Theseoutput signalsare neDory read comtnnd (MRDC), nenorJ x)rik comnandO,tw'lc), adrancednenory wik convand (t\MwC\. I/O read comand IORC), I/O wfte conafund (rOwC), advared xO wntu conoMnn (NOWC), audinterrupt acknowledqe(INf A). The 8288 producesone or two of rhesesevetrconunandsignalsfor eachbus cycle. For instance,when the 8088 outputsthe code SrSrS0: 001, it indicatesthat an I/O read cycle is to be perfonned.In turn, the 8288 makesits IORC output switch to logic 0. On the orherhand,if the code 1I I is outputby fte 8088,it is signalingtlat no bus activiry is no commandsignals. to takeplaceithe 8288produces The other contol outputsproducedby the 8288 consi:rtof DEN, DT,R, and ALE. Thesettuee signalsprovidedle sane tunctionsasthosedessibed for the minimum mode. Figure 8-5(b) showsthat the 8288 bus corto er conne€tsto the 8086 in the sameway as the 8088,and it also producesthe sameoutput signals. Sec 8.4

InterfaceSrgnals fMaxrmumMocle

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EMMPLE8.3 ff the bus statrs codeSrSlS0equals101,what g?e of bus activity is taking plac€?Wlich conmand ouFut is Fodrced by the 8288?

Solution Lookingat thetablein Fig.8 Z we seethatbusstatuscode101identifies a readmemory bnscycleandcauses theMRDCoutputof thebuscontrollelto be switchedto logic 0.

344

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Lock Signal To implement a multiprocessorsystem,a signal called lock (LOCK) is provided on the 8088and 8086.This signalis meantto be output(logic0) wheneverthe plocessor wants io lock ont the other processon from using the bus. This would be the case when a sharedresourceis accessed.The LOCK signal is compatiblewith the Mrltibrr, an industry standard for interfacing microprocessor systems in a multiprocessor

sec 8.4

Maximum-lvlode lnterfaceSrgnals

345

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tbt Figure 8-6 (.) Blocl diagrM of the 82E8.lReprjited tith permisjon of lnLelCorporation, E 1919)(b) Pin layout.(Rcprhtedwnh pemissionof htcl O i979) Corporation.

Signals OueueStatus Two orhersignalsproducedby the 8088and 8086.in the naxinum-modemicro computersysrem,are queuestatusoutputsQSoand QSr tharfon ^2bjt queuestatus .,1e, QSlQSo.This code tells lhe extemalcircuitry whal type of informationwas rcmovedtiom the inltructionqueneduringthe previousclockcycle.Figure8 8 shows thefour dillerentqueuesiatuscodes.Note tharQSlQSo= 0l indicatesthatthe first byte of an insfirctioD was taken off the queue.As shown. the feich of the Dextbyte of lhe instmclionis identiliedby the codeil. Whenevefthe queueis reseldueto a t|,tnsferof codc10 is ouiput. control,|hereiniiialization

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O 1979) Figure8-7 Bus staiuscodes.(Repnnbdwnh permisior of l.rel CoiPoratiotr.

t46

The 8088 and 8086 Mjcroprocessors Chap I

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0 Ou€ue Emply.The queue has asa rssultollhe be€nreinilislired sreculionol a transferinslruction. Byte.Thebytelaken Subssqusnl Iromths queuewasa subsequ€nl figure 8-8 Queuestatuscodes. (Reprintedlith pernisslon of lntel byleol theinslrucllon. Corporanon, O 1979)

LocalBusControlSignals In a maximum mode configuration,the minimum-modeHOLD and HLDA interface of the 8088/8086is also changed.Thesetwo signalsarc rcplacedby requen/qrunt l,r€r RQ/CToand RQ/GTj. They provide a prioritized bus accessmechanismfor accessing the local bus.

CHAMCTERISTICS 8.5 ELECTRICAL ln the precedingsections,the pin layout and minimum- and maxinum-mode interface signalsof the 8088 and 8086 microprocessorswere intoduced. Herc we will firsl look at the power supply ratings of theseprocessorsand then their input and output electricel characteristics. Looking at Fig. 8 l(a), we find that poweris appliedbetweenpin 40 (V".) andpins I(GND) and 20(GND). Pins I and 20 should be connectedtogether.The nominal value of V.. is specifiedas +5 V dc with a toleranceof =10EoThis ineansthatthe 8088or 8086 will operateconectly as long as the ditrerencein voltagebetweenV"" and GND is (25oC),bothtbe 8088 greaterthan4-5V dc andlessthan5.5V dc.At roomtemperature and 8086 draw a maximum of 340 mA from the supply. Let us now look at the dc yO characteristicsof ihe microprocessor-that is. its input and output logic levels.Theseratingstell the minimun and ma{imum vollagestor the 0 and I logic statesfor which the circuit witl opente corectly Different valuesare speciliedfor the inputs atd outputs. Figure 8-9 showsthe I/O voliage specificationsfor the 8088 Notice thal the minimumlogic I (highlevel)voltageai an ouQut(VoH)js 2.4V This voltageis speciliedfor a test condition thai identifiesthe arnountof currentbeing sourcedby the ou@ut(IoJ as -,100 pA. Al1 processorsmust be tesledduring manufacturingto ensurethat under ths lest condition the vollagesat all outputswill remain abovethe value of VoH-i" sec.8.5

ElectricalCharacteristics

347

+2.0v +2,4V

v.. + 0.5v Figure 8-9

I/O voltagelevels.

lnput voltagelevels are specifiedin a similar way; exceptherethe raringsidentify the rangeof voltagethat will be correctly identified as a logic 0 or a logic 1 a1an input. = -0.5 V to VL,,"* = +0.8 V represent For inslance, voltagesin therangeVn a vilid ",i. logic 0 (lowerlevel)dt an inputofthe 8088. The I/O voltage levels of the 8086 microprocessorare identicai to ihose for ihe 8088asshownin Fig. 8-9. However, thercis onedifference in theiestconditions. For the 8086,VoL is measuedat 2.5 mA insteadof 2,0mA,

A 8,6 SYSTEM CLOCK The dme basefor synchronizationof the internal and extemal operationsof the micropro.essorin a microcompuiersystemis providedby the cl.rc* (CLK) input signal,At pfesent,the 8088 is availablein two different speeds.Tbe standardpan op€rutesot 5 MHz and the8088-2operales at 8 MHz.On theolberhand,the8086microprocessor is manufactuled in threesp€edsr the s-MHz 8086,the 8-MHz 8086-2,anddle lo-MHz 8086-1.The 8284 clockgenerator anddriverIC generate$ CLK, Figul€8-I0 is a blockdiagramofthis device.

Iigu.e 8-10 Block diagam of the 8284clock generator(Repnntedwilh peF misslonof Intel Corporation.@ 1979)

348

The8088 and 8086 Microorocessors chao-8

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CLK

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IigN E-ll Connetingthe8284lo the 8088. (Reprintedwith penission of lntei Cor?oration.@ 1979)

The standardway in which this clock chip is usedwith the 8088is to connecteither a 15- or 24-MHz crystal betweenits Xr and X2 inputs.This circuir connecrionis shown in Fig. 8 11.Note that a seriescapacitorCL is also required.trs lpical value when used with the 15-MHz crystal is 12 pF The funnanental crystal frcquerry is divided by 3 within tbe 8284 to give either a 5- or 8-MHz clock signal. This signal is internally bufferedandoutput at CLK. The CLK outputof the 8284canbe dnectly connectedto the CLK input of the 8088.The 8284 connectsto the 8086 in exacdythe sameway. Figure 8-12 showsthe wavefom of CLK. Here we seethat the signal is specified at metal onde semiconductorO4os)-compatiblevoltagelevels andnoi transistortransisior logic (TTL) levels.Its minimu.n and maximun low logic levels a.e VLdi : -0.5 V andVlda = 0.6 Y respectively.Moreover the minimum and marimum high logic levels areVs-i" = 3.9 V andVHms : Ve + 1 Y respectively.Thepetrd of the clo€k signalof a 5 MHz 8088 can rangefroln a nininum of 200 ns to a mrximum of 500 ns, and the maxilj.u.mrise andfatl tines of its edgesequal 10 ns. Figure 8-10 shows two morc clock outputs on the 8284i tte peripheml cLock (PCLK) and oscilLdtorclo.* (OSC).Thesesignalsare provided to drive peripheraiICs. The clock signal output at PCLK is half the frequencyof CLK. For instance,if an 8088 is operatedat 5 MHz, PCLK is 2.5 MHz. Also, it is at TTl-compatible levelsratherthan MOS levels.On dre otherhand,the OSC output is at the crystal frequency,which is thre€ times that of CLK. Figure 8-13 illustratestheserelationships. T]le 8284 can also be driven from an extemalclock sourcejhe extemalclock signal is applied to ihe exiemal frequencyinput (EFI). Input F/C is provided for clock sourceselection.Wlen it is strappedto the 0 Iogic level, the crystal betweenXr and X, is used.On the otherhand.applyins logic I to F/C selectsEFI as the sourceof the clock. The clock sync (CSYNC) input can be usedfor extemalsynchronizationin systemsthat employ multiple clocks.

Figue E-12 CLK voltageand timing chdacteristicsfor a 5-MHz processor(Reprintedwilh permissjon of Intel Corpontion, O 1979)

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Figure 8-13 RelationshjpbelweenCLK and PCLK. (Reprintedwith pennission of lntel Coryonrlon, O I 979)

EMMPLE8,4 If theCLK inputofan 8086MPU is to be ddvenby 4 9-MHz signat,wha!speedversion of the 8086mustbe usedandwhatfrequency crystalmustbe attnched to the 8284?

Solution The 8086-l is the versionof the 8086that canbe run at 9 MHz. To createrhe 9-MHz clock,a 27-MHzcrystalmustb€ usedon the 8284,

A 8,7 BUSCYCLE AND TIMESTATES A Dlli c)cb definesth€ basicopemlionthat a microproces$or pertbrmsto communicate with externaldevices,Examplesof bus cyclesare the memorylead, Demoly write, input/outputread,and inpuvoutputwrite.As shownin Fig. 8-14(a),a buscycleco espondsto a sequence of eventsthatstall with an address beingoutputon the systembos followedby a reador write datatransferDuringtheseoperations, the MpU produces a seriesof controlsigralsto conlrolrhedirectionandtinringof thebus. The buscycleof the 8088and8086microprocessors consistsof at leastfour clock p€riods.Thesefour time statesarecalledT , T2,Tj, rnd Td.DuringTr, theMpU puB an addrcss on the bus,For a write memorycycle,dataareput on thebusduringstateT, and maintained throughT3 andTa.Whena readcycleis ro be pedomed,the b s is first pur in the high-ZstateduringT, and thenihe datato be readmusrbe availableon the bus dudngT1 andTa. ThesefoLrrclock staLes gi\e a bus .jlle durationof 125ns X 4 = 500ns in an 8-MHz 8088system. If no bus cyclesare reqxired,the microFocessorperforns whal are knowr as td? rrat€r. During thesestates,no bus activiry takesplace.Eachidle staGis one clock period long,andanynumberol themcanbe inserredberween buscyctes.Figure8-14(b)shows two buscyclesseparatedby idle states.Idle staresare perfomed if the insrructionqueue in.idelhe nicroproce*,'r i. tLll dnd ir aoe.nor neea,o'e,,dor wrireoperrnd.from Waitnoks .al also be insededinto a bus c),cle.This is donein response ro a requestby an eventin extemalhardwareinsteadof an internal evenrsuchas a full queue.

350

The 8088 rnd 8086 MrLroproce\o.\

Chdp. 8

-"-r"t"t"-]*"--l

*-ru

tl --___________x__]@-

JL J _""r","."". "."."*,*....*' J 1-;';y;,".pgi**

FisuE E-r4 (a) Bus cycle ctock periods.(Reprinkn wirh lemisior of Inlel Corporation,O 1979) (b) Bus cycle with idle states.(Retrtured with pemissiotr of Iltel Corporaliorr O 1979) (c) Bus cycle with wait states.(Reprinted wirh pemi$ion of Intel CorpoEtion, O 19?9)

ln fact, the READY input of the MPU is Fovided spe.ificaly for rhis pupose. Figwe 8 14(c) showsthat logic 0 at this input indicatesthar tlle cuneni bus cycle shouldnot be completed.As long as READY is held at the 0 leve], wait statesare inserredberween statesT3 andTa of the curent bus cycle, and the dararhar were or the bus during T3 are maintained.The bus cycle is not completeduntil rhe extemalhardwarereturnsREADY back to the 1 logic level. This extendsthe duration of the bus cycle, therebypermitring the use of slower memory and I/O devicesin the system.

EMMPLE8.5 What is the duration of the bus cycle in the 8088-basedmicrocomputerif the clock is 8 MIIZ and two wait statesare iDserted?

Solution The duration of the bus cycle in an s-MHz systemis give, in generalby ty.=500ns+Nx125ns 5 e c .8 . 7

BusCycleand llme States

35t

In this expressionN standsfor the numberof wait states.For a bus cycle wirh two wair

t y"= 500rs+ 2 x 125ns = 500ns+ 250ns = 750ns

8.8 HARDWAREORGANIZATIONOF THE MEMORY ADDRESSSPACE From a hardwarepoint of view.the memory addressspacesof the 8088 and 8086-based microcomputersare organizedditrerently.Figure 8-i5(a) showsrhat the 8088'smemory subsystemis irnplementedas a single 1M X 8 memory bank. Looking ar &e block dia gram in Fig. 8-15(a), we seethat thesebyte-wide storagelocationsare assignedlo consecutiveaddressesover the rangefrom 0000016throughFFFFFT6.During rnemoryoperations,a 20,bit ad&essis appliedto the memorybank over addresslines Ao ttuoughA,, It is this adahess that selecrsthe storagelocation thar is to be a.cessed.Bltes of dataare trdnsferredbeiweenihe 8088 and memory over databus lines Do throughD7. On the other hand, the 8086's lMbyte memory addressspace,as shown in Fis. 8 l5(b), is implenented as rwo independenr512Kbyte banks: the torr (et)en)bank and 6e high (odd) bank Data.bltes associatedwith an evenaddress(0000016,0000216.etc.) residein thelow bant, andthosewith oddaddresses (0000116, 0000316, etc.)residein rhe hish bank. .]IMSYTES

2

5 1 2 tl Y t E s

srrEs t12r(

!

i 0

(b) Fisur€ 8-15 (a) lM x 8 hemory bank of rhe 8088. (b) Hish and low memory banks of tle 8086. (Reprintedwirh permision of Intel Corporation, o 1979)

352

The4088 and 8086 Microorocessors ChaD.8

The diagramin Fig. 8 l5(b) showsthat for the 8086 ad&essbits, A1 throughAre selectthe storagelocation that is to be accessed.They are appliedto both banksin parallel. A0 and bank high enable(BHE) are usedas bank-selectsignals.lngic 0 at A$ idennbyte of dataandcausesthe low bant of memoryto be enabled.On fies an even-addressed byte of the othgi hand,BHE equalto 0 enablesthe high bank to accessan odd'adahessed Notic€ that data. Eachof the memorybanl6 provideshalf of the 8086's 16-bi! databus. the lower bank transfersbytes of dataover datalines Do throughD7,while datatransfers for a high bant(useDs throughD,5. We iust saw that the memory subsystemof the 8088-basedmicrccomputersystem is actuallyorganizedas 8_bitbytes,not as 16-bit words However'the contentsof any two b)4e consecutivebyte storagetocationscan be accessedas a word The lower-addressed byte is its most signifiis the least significantbyte of the word. and the higher-addressed capt byte- I€t us now look at how a b)4e and a wod of dataare readfrom memory. Figure 8-16(a) showshow a byte-memoryoperationis perfomEd to the storage Iocation at addrcssX. As shown in the diagram,the adahessis suppliedlo the memory

(x+1t

(b1

Sec-8.8

Figue E-16 (a) B}'te trdsfer bY the 8088. (b) word tmsfer by the 8088

Space HardwarcOrganjzationof the MemoryAddress

35

bank over lines A0 throughAre, and the byre of datais wrilten into or read from storage locarion X orerline.Do-hrough D-. D cdJries rhe\4SBo, rheoyteotdara.dnd D0c;riestheLSB. This showsthara byteof datais accessed by rhe 8088jn onebuscvcle.A memorycJ(le lor an F088rLrnning ar 5 MH,, w t- no $aiL.rare.rate. 800n.. When a word of data is ro be transfer"edberweenrhe 8088 and mernorv.we must Derformrso acce$e.ofremor). readjogor sriling a bytFin eacnacce-. Figure8 r6lbl illustates how the word storagelocarionstartingal addressX is accessed. Two bus cycles are requred ro accessa word of data.During the fusr bus cycle, the leastsignificanrbyte of the word, locatedat addressX. is accessed. Again the addressis appliedro the mem oD banxoverA. lhroughAro.and.heb)reot datai. Fan.feredto o, irolnuo"g.'o.u. tron X over Do tbroughD?. Next, the 8088 automaticallyincrementsrhe addressso rhat it now points to bvte dddre$X + L hi. addre$poin..lo lhene\rcon.ecutive b)re.lorage tocalion in men ory, which conespondsro the most significantbyte of the word of daraat X. Now a second memory buscycle is initiated. Durirg rhis secondcycte,daraare writren inro or read l?om the storagelocation at addressX + 1. Sinceword accesses of memorytake two bus cyclesinsteadof one,it takes1.6ms to access a word of datawhenthe 80S8is oDerarins dr r 5 MH,, cloc,(ralew h ao wail !!ares. The 8086 .nicroprocessorperforms byte and word data transfe$ differently from the 8088.Lel us next examinethe daratransfersthar can take placein an 8086-based Fignre 8 17(a)showsthat whena byte-memoryoperarionis pedorhed ro addressX, an even-addrcssed storagelocarion in dle low bank is accessed.Therefbre.A" is sei ro .ogic0 ro enJblerhe lo$ bant of nemoD drd BHE-lo togrc I ru di.abrernehrshbao*. 45 \houn ia rheblockdiJgran.d d arenan.renedro or rromrhe toser bdnl ;\ er ddrd buslinesD0tbroughD?.Line D? carriesrheMSB of thebyte,andDo rheLSB. On the other hand.to accessa byte of dataat an odd addresssuchas X + I in Fig. 8 l7,br.q0 r".el lo log,cI andBHFro logic0. Thi. enable,rnehighbanxof memor) and disablesthe low bank. Daia are transfered betweenrhe 8086 dnd the hish bant over Du,rine(DsdTough D.. He? Dr, repre.enrr rheMSB andDRrheLSB. Wheneveran even,addressed word of datais accessed,both the high andtow banks areaccessed at the sametime.Figure8-17(c)iltusrraies how a wordar evenaddress X is accessed.Nole that both A0 and BHE equat0; therefore,both bants are enabled.In rhis case,bytes of data are ransfefed from or to borh banks at rhe samerime. This l6_bit word is aansfeffed over the comp]etedata bus Do through Dr5. The byres of an even_ addressedword are said io be aligned and can be rransfenedwith a memorv oDeration _ndlale\,rst onebuscycte. A word at an odd-addressed boundaryis said to be unaligned.That is, the leastsig_ nificanl byte is at the lower addresslocation in rhe high memory bank. This is demonstratedin Fig. 8 17(d).Here we seethat the odd byte of the word is locaied ar ad&ess X + I andthe evenbyreat address X + 2. Two buscyclesarerequiredto accessan unalignedword. Dwing the first buscycle, theoddbyteof ihe word,whichis locaredaraddrcss X + 1 in thehish bank.is accessed. Pr'. h rccompan'eJ b) \etecr.ignaloAo- t andBtU - 0 anda Jararan,reroverD" throughDr5. Even thoughrhe datatransferusesdatatines Ds throughDr5, to the proces" ,or ;_i. thelow b\te of lhedddre,,ed oard$uro

354

The 8088 dna 8086 V.(rop.o.es\or5

Chap. 8

(d)

Figue 8-17 (a) Even-address byte transfd by the 8086.(Reprlnredwith per nision of Intei Corporariotr,O 1979) (b) Odd'addres byte tmsfer by ihe 8086. (Reprinted with permision of Inte] Corloetion. O 1979) (c) Even addres word transferby the 8086.(Reprintedwith permision of Iniel Corloration, O i979) (d) Odd addres wod iransfer by ihe 8086. (Reprhted wilh pemission of Int€l Cor?oration.O 1979)

355

Next, the 8086 auromaricallyincrementsthe addressso tharA. = 0. This reDresenrs lhe nerl addreq,in memoryuhich ,s eren.Thena \econdmemon bu. c\cte L iniridred. Duringrhi,,econdclcle.rhee\enb)re localed ar X - 2 in rheto\ banl is acces,ed. The datatransfertakesplace over,buslines D0 throughD7. Tbis tansfer is accomDanie.d b)& 0and BHE - l. lo rheproce.soj. dri, ie rhehighblreofrheuordol daia.

EMMPLE 8.6 Is theword at memoryaddress 0123116 of an 8086basedmicrocompurer atignedor mis aligned?How manybus cyclesare requiredto read it ftom memory?

Solution The first byte of the word is rhe secondbyre ar the aligned-wordaddress0123016.There_ fore, the word is misalignedand requirestwo bus cyclesto be read from memory

8.9 ADDRESSBUS STATUS CODES Whenevera memory bus cycle is in plogress,an addressbus statuscode S,S. is outDut b) rl'eprccessor The5rdru,coders n utripte\ed wirhaodre..birsAr- andqr".'ftr. ruo. bit codeis outpur aathe samerime the daraare caded ov€r the daralines. Bits Sr and53 togetherfom a 2,bir binary codethar idenrilieswhich one of the four segmentregrters was used to generaterhe physical addressthar was oumur duinq ihe addresrperiodin rhecurrenrbur c)cle. The tow add,"ssbut snru,,oae, are lisreain Fig. 8-4. Here we find thar codeSaSr= 00 idenrifiesthe exrrasegmenrregister 01 ide.r tifies the stacksegmentregister,l0 identifies the code sesmentregisret and 11 identifies the datasegrnentregisrer Thesestatuscodesare ourput in both the minimum and rhe maximum modes.The codes can be examinedby external circuifty. For example,they can be decodedwith extemal circuirry ro enableseparatetMbyte adatressspacesfbr ES, SS, CS, and DS. In this way, the menory addressreachof the microprocessorcan be expandedto 4Mbytes.

8.I O MEMORYCONTROLSIGNATS Earlier in the chaprerwe saw rhat similar control signatsare producedin rhe maximum andminimum mode.Moreover,we found ihat in rhe ninimum mode,the 8088 and 8086 microprocessonproduceall the conrrotsignals.But in the maximum mode,the g288 bus contoller producesthem. Here we wiil look morc closely ar each of thesesisnais and rbeirtunctjonsu irh re,pecrlo memoryinlerfaceoperdrion.

Minimum-Mode MemoryControlSignals In the 8088 rnicrocompurersysrernshown in Fig. 8_18, which is configurealfor Lheminimummodeotoperarion. $e tindlhartheconnotsrgnat( prorjdedro.upDonrhe inrerfacero rhe memory\ub\ysremare ALL, tOA4, Dt/R, RLi. WR. arl nf|,r. T|*"

356

The80aa and 8086 Microprocessors Chap.I

8@8

Io/i DEN

sso

Figure8-18 Mininun-no.le 8088remory hterface. control signalsarerequiredto tefl the memorysubsysiemwhen the bus is carrying a va]id address,in which dircction dataarc to be tansfen€d over the bus, when valid write data are on the bus,and when to pur read dataon the bus.Fot example,ad.dresslatch enable (ALE) signalsextemal circuit y that a valid addressis on the bus. It is a pnlse to the I logic level alrd is usedto latch the addressin extemalcircuitry. T\e input-ouput/memory AO/ll{) and d^ta tnnsmit/rece e (DT/R) lines signal extemalcircuitry whethera menory or I/O buscycle is itr progressand whetherthe 8088 will transmit or receivedataover the bus-Dudng all memory bus cycles,IO/M is held at the 0 logic level. The 8088 switchesDT/R to Iogic I during the datatransferpart of the buscycle, the bus is in the transmitmode,anddataare written into memory On the oaher hand, it setsDT,.Rto logic 0 to signal that the bus is in the rcceive mode, which corlespondsto readingof memiry. The signarsr"d/ (RD) and lrn& (WR) identit that a read or write bus cycle, respectively,is in progess. The 8088 switchesWR to logic 0 to signal memory that a write cycle is taking place over the bus. On the other hand, RD is svritchedto logic 0 whenevera read cycle is in progess. During a[ memory operations,the 8088 produces one other control signal, ddta [email protected]:,c O at &is outPutis usedto enablethe databus. Slrtus l;n" SSOis alsopart ofthe minimum-modememoryinterface.The logic level is tbat outputon this line during Iead buscyclesidentfies whethera codeor dataaccessis in progress.SSOis setto logic 0 wheneverinstmctioncodeis readfrom memory The contol signalsfor the 8086'smidmum-node memoryinterfacediffer in three ways.First, the 8088's IO/M signal is replacedby the m€mory/input-output(M/IO) signal. Whenevera memorybuscycle is in plogress,ihe M/IO output is switchedto logic 1. Second,the si$al SSO is removedfiom the interface.Thftd. a new signal, ,anft tlgll enable(BHE), hasbeen addedto the interface.BHE is usedas a selectinput for the high bant of memory in the 8086'smemory subsystem-That is, logic 0 is output on this line Sec.LI0

MemoryControlSignals

357

during the ad&esspart of all rhe bus cyclesin which darai, the hish-bank Darrof mem ory is to be accessed.

Maximum-Mode MemoryControlSignals W}len the 8088 is conligured to work in rhe maximum mode. it does nor diectlv pro\ideall rl.econtrol.ignal( ro supponrhe memor)inrerface. Incread.an exremalbu' controllet the 8288,providesmemoryconmandsandcontol signats.Figure 8 19 shows an 8088connected in thiswav Specificalt). rhe WR. tOA4. DT,R.bLN. ALE. andSSOrignat rine.on rhe8088 are Lhanget.The) dre replacedvirh nultiproce\\ot /or* rlOCKr signat.a b,l \rdrar !94e (SrS1SJ,anda 4rar? rrarrr cod?(QSreS0).The 8088stitl doesproducerbesisnal RD.whichprovides lhe.amelJnclionasil did in minimummode The 3-bil busstatuscodeqS,Sn is nutputprior to the iritiation of eacbbuscycle. It identjfieswhichlype ofbus cycleis to follow This codeis inputto the g2ggbuscon_ troller Here it is decodedto identify which type of bus cycle commandsignalsmust be generaled, Figure8-20 showsthe relationship belweenthe busstatuscodesandthe typesof buscyclesproduced, Also shownin this chartare the namesof the co$esDondins commandsignalsrharare generaedar the ourputsof the 8288.For instance,rhe inprircode S:SrSoequalto 100fldicaresrhatan inerruction ferchbuscycleis ro takeplace.Sincefie insructionferchis a memoryread.lhe 8288makesthenenory readconnand (fr-RDC1 outputswitchto logic0. Anorherbuscommandprovrdedtbr thememorysubsystem is SrSl56equalro I J0. This represents a memorywrite cycleand it causesboth the memorywrite conmand

8288

Figure E-19 Mdimun-mod€ 8088menory interface.

358

The8088 and 8086 Microprocessors Chap. 8

s! 0

sr I

0

iflrA toRc rovc-,A-i6Fa

I

I

MRDC MIDc Mwlt. AMwc

Figure 8-20 Memory bus cycle stalus codesp.oduc€d in ffiimum (Reprintedwith pemission of lntel Corporation,@ 1979)

mode.

(MWTC) and advancedmenary \rfte command(|\NN{C) outputs to slvitch to the 0 logicle\e'. The other control oulputs producedby the 8288 arc DEN, DT,/R.andAlE These signalsprovidethe sane tunctionsasthoseprcducedby dle conespondingpins on the 8088 in the minimun systemmode. The two statussignals.QSoand QSr, lorm an instruction queuecode This code tells the exlernalcircuitry what type of infomation was removedfrom the queueduring the previousclock cycle. Figure 8-8 sholvsthe four diffetent queuestatuses-For instance' = Ol indicatesthat the lirst byte of an instructionwas ta.kenfrom the qneue The QSTQSo nextbyte of the instructionthat is letchedis identifiedby queuestatuscode 1l Whenever the queueis reset(e.g.,due to a transferof control) the reinitialization code 10 is output Simitarly, il no queueoperatio occurred,statuscode00 is outpur. The bus prioriD lock (LOCK) signal, as shownin the inteface, can be usedas an input to a bus arbiter.The bus arbiier is usedto lock otherprocessoffoff the systembus of conmon sysGmresourcessuchas glordl nendD' in a muldprocessor during accesses system.The READY signalis usedto intedaceslow memory devlces. A11of the memorycontrol si$als we just describedfor lhe 8088'basedmicrocomputer systemservethe samefunction in the maximum-mode8086 microcomputerHow ever thereis one additionalcontol signalin the 8086'smemoryinlerface,the BHE. The BHE performs the samefunction as it did in fie ninimum-mode svstem That is, it is usedas an enableinput to the high ban&of memory'

8.I1 READAND WRITEBUSCYCLES In the precediry sectionwe introducedlhe slatusand contml signalsassociatedwith tl'e memory interface.Here we continueby studyingthe sequencein which thev occur during the read and write bus cyclesof memory sec.8.1I

Readand write Buscycles

35t

ReadCycle Figure 8-21 showsthe memoryinterfacesignalsof a minimum-mode8088 system. Here their occurenceis illustraredrelarivero the four time staresTr, Tz, Tr. andT1 of the 8088'sbus cycle. Let us trace ihe eventsthat occur as dataor instructionsare read from The rcad bus q,cle begtnswith srateTr. During this period, the 8088 ourputsrhe 20'bit addressof fie memorylocation to be accessedon its mulriplexedaddress/data bus ADo through AD?, As throughAr, and multiplexed lines A6/51 tbrough Arr/56. Nore that al the sametime a pulseis also producedat ALE. The rrailing edgeor the high level of this pulse shouldbe usedto latch the addrcssin extemll circuitry. Al.o \^e ceelhalar he {a1 ofT.. siCnal,lO/\4lld DT,Rare,et to rhe0logic level. This indicaresto circuitry in rhe memory subsystemihar a memory cycle is in p,!,sre\\anarha,,he8088; lornr ro recei\ed d from,bebu..Srdru. SSOr. at.oour-

IO/M RO

DT/F

-- -t

figure E-21 Minimum,modememoryreadbus rycte of the 8088.(Reprinted with lemision of intel Corporation,O I 979)

360

The 8088 and 8086 MicroDrocessors Chao. I

Dut at this time. Noie thai all tkee of thesesignalsare maintainedat theselogic levels ihroughoutall four periodsof the buscycle. Beginning with stale T2, statusbits 53 through 56 are outPut on the upper foul ad{tressbus lines A16throughArr. Rernemberthat bits 53 and S1identifv to extemalcircuitry which segrnentregister was used to generatethe addressjust output. This status information is maintainedttuough periodsT3 and T+ The part of the ad&essoutput on addressbuslines As tlrough Ars is naintained tfuough statesTr. Tr, andT4. On the other bus lines ADo throughAD? are put in the high-Z statedu.ing Tr' hand.address/data ro $e memoDsrbslsLarein penodT. RD i. 'qilchedro logic0 Ttu' indjcarec 'o enable erkmal circuirr) re.rl|ndrr rerd clc,e r' in progess DE\ I' ssirchedro'ogic 0 daia bus. to allow the datalo move from memory onto the midoprocessor's As shownin the lvaveforms,input data are readby the 8088 during T3. The memory must provide valid dataduring T3 and maintainit until after the processorterminates the rcad operation.As Fig. 8-21 shows,ir is in T! that the 8088 switchesRD to the inactive I logic level to lerninate the read operation.DEN retums to its inactive logic level late during Ta to disablethe exiernalcircuitry, which aliows datato move from memory ro the processor.The readcycle is now complete. A timing diagramfor the 8086'smemoryreadcvcle is Sivenin Fig 8-22(a) Comparing thesewaveformsto lhoseof the 8088 in Fig. 8-21' we ind just four differencesi BHE-is output along with lhe addressdudng Tr; the datarcad bv the 8086 during T3 can be carriedover a[ 16 databus lines; M,4O. which replacesIOA4, is switchedto logic I

Fisur€ s-22 (a) Minimum-mode memory read bus cvcle of dre 8086' o loTq''b' \4drmum_mode I R ; o r i ne d + t r np e m i . . i o no l l n r e l C o r p o r a l i O mr:^ry ead bu, cycleof .he d08{-.,ReprInredwirl. Derris,ionol lnrelCoF poralior O 1979) Sec.8.1 I

Readand Write Bus Cycles

361

FigureS-22 (continued)

at the beginningofTr andis held at this levelfor the durationof the buscycle;andthe SSO statussignal is not produced. Fignre 8-22(b) showsa read cycle of s-bit data in a Ina\ilnum mode 8086 based microcomputersystem.Thesewavefoms are similar ro those given for the minimunwe seethatthe modereadcyclein Fig. 8 22(a).Comparingthesetwo timingdiagrams, addressand datatnnsfers that take place are identical. In fact, the only differencelbund in the maximummodewaveformsis that a buscycleslatuscoite,SrSrS0,is outputjFsr prior to the beginningof the buscycle. This statusinformation is decodedby the 8288to producecontrol signalsALE, MRDC. DT/R, and DEN.

V/riteCycle Figure8-23(a)illustratesrhetnite bus clcie trmingofthe 8088in ninimummode. It is similarto thatgivenfor a rcadcyclein Fig. 8-21. Lookjngat the write cyclewaveforms. we find that dudng Tr the addressis output and latchedwitb the ALE pulse.This is identical to lhe read cycle. Moreover,IO/l'{ is set to logic 0 to indicate that a memory cycle is in progressand statusinformation is ouiput at SSO.However.this time DT,&. is switchedto logic L This signalsextemal circuits that lhe 8088 is going to tansmit data

362

The8088 and 8086 Microprocessors Chap.I

ro/ti w3

ora__j

L.

DEN

_-J

--1

sso

r,

r(a)

Figure E-23 (a) MitriDDmmodemmory wite b6 cycle of the 8088. (Repiinledwith p€missionof Intel Corporatior@1979)(b) Mdimum-node with penission of IntelCoF memorywrile buscycleof the 8086.(Reprinted poration,@ 1979)

As T, starts,the 8088 switchesWR to logic 0. This tells the memorysubsystemthat a write operationis to follow over the bus. The 8088 puts the dataon the bus late in T, and maintainsthe data valid though Ta. The writing of data into memory startsas WR becomes0, and continuesas it charyes to I early'in Ta. DEN enablesthe extemal circuitry to provide a path for data ftom the processorto the memory.This completesthe Just as we describedfor the readbus cycle, the write cycle of the 8086 ditrers from that of the 8088 in four ways; agaia SSOis not prcduced!Bm isiutput along with the addressidata ,re canied over a 16 databl]s lines: and fnally, M/IO is the complement of dle 8088'sIO/M signal.The wavefoms in Fig. 8-23(b) ilustrate a wrjte cycle of word datain a ma,\imum-mode8086 system.

sec. 8.1 I

Readand Write Bus Cycles

363

FiguE E-23 (co lnued)

^' 8.i2 MEMORYINTERFACE CIRCUITS This section describesthe memory interface circuits of an 8086-basedmicrocomputer system.The 8086 systemwas selectedinsteadof an 8088 microcomputerbecauseit is more complex. Figue 8-24 shows a menory interface diagram for a ma,\imum-mode 8086-basedmicrocomputersyslem.Here we find that the interfaceincludesthe 8288bus contoller, addressbus latchesand an addressdecoder.data bus transceiver/buffers.and bank read and w.jte control logic. The 8088 microcompuGris simpler in that the interfacedoesnot rcquire bank wdte control logic becauseits addressspaceis organizedas a sinelebanl. Lookingat Fig. 8 24, we seethatbusshruscodesignalsSz,Sr, andSo,whicharc outputs of the 8086, are supplied direcdy to the 8288 bus controller. Here ftey are decodedto producethe commandand conhol signalsneededto coordinatedatatransfers over the bus.Figure 8-2o]ighlights the slaluscodesthat reiateto the memoryinterface. : 101indicatesthai a datamemoryreadbus cycleis in For example,the codeS2S]S0 progress.This codemakesrhe MRDC conmand output of the bus control logic slvitch to logic 0. Note in Fig. 8-24 that MRDC is applied to the banh read control logic. Next let us look at how the addressbus is latched,buffered,and decoded.Looking at Fig. 8-24, we seethat addresslines Ao throughAD are latchedalong with contlol signal Bm in the ad&ess bus latch. The latched addrcsslines AjrL tlrough ArrL are

t64

The8088 and 8086 Microprocessors chap. 8

-cE" cE-,

BHE

wR, WR.

Fd

Figure8-Z

Memoryinterfaceblockdiagram.

eE . Notice$ar lhe 8288buscondecodedlo producechip enableoutpubCq Lhrough troller producesthe addresslatch enable (ALE) control signal from SrSlSo.ALE is appliedto lhe CLK input of the lalchesad strobesthe bits of the addressand bank high €nablesignalinto the ad&essbuslatches.The addresslatch devicesbuffer thesesignals. linesArL tbmughAr6LandCq tuough CE7areapplieddirectlyto the Latchedaddress memory subsystem. Du.ing readbuscycles,the MRDC ouqut of the buscontrol logic enablesihe bytes of dataat the outputsof the memorysubsystemonto databus lines Do tbroughD15.During read operationsfrom memory fte batrk read control logic determineswhether the dataare readIiom one of the two memorybanksor ftom bolh. This dependson whether a byt€- or word-datatransferis taling place over fte bus. Similarlyduring wrile brtscycles.rhe IvfwTC ourpurof he bu. coDtrollogic erablesbyt€sof datafrom the databusDo drough DE to be written into the memory.The bank wnte conaol logic determtuesto which memory bank the da(aare wdtten5ec.8.12

Memory lnteriaceCjrcuits

t6t

Note in Fig. 8 24 that in ihe baDl write control logic the latched bad( high enable and address l;ne AoL are galed wilh lhe memory $rile conmand signa] {g4LBmL MWTC toTroduce 4 leparale wrile enable signal for each bank. These signals are denotedas WRL' and WRL. For dample, if a word of dala is Io be wriLlcn|o memory over data bus lines D0 tbrougl Drr, both WRu and WRL-are switched to their acrive 0 logic level. Similarly the memory read control logic uses MRDC, AoL. and BIIEL to gene te RDu and RDL sisnals for bank read control. The bus transceiven conirol the direction of dala ransfer between the MPU md memory subsysten In Fig. 8 24, we see that the opoation of the t ansceiver is con trolled by the DT/R and DEN ouFuts of thc buJi controllcr DEN is applied to the EN input of the transceiverjdnd enablesthen fo. operatioD.This happensduring all read and wriie bus cycles. DT/R selects the direction of data transfer ttuough the devices. Note that it is supplied ro lhe DIR input of lhe dala bus ransceiYels- W})en a read cycle is in progress. DT/R is \et to 0 and dala are passed from thc memory subsystem 10 the MPU. On dre other hand. when a write cycle is taking place. DT/R is switched to logic I and data are carried from the MPU to the memory subsyslem.

AddressBus tatches and Buffers The 7,lFl73 is xn examplc of an octal latch dcvicc that can be used to implement the ddr.€rr /d.., section of the 8086 s memor) i erface circuit. A block diagram of this device is shown m Fig. 8-25(a) and fts intemal circuit] is shown in Fig. 8-25(b). Note that ii accepF eight inpuis: lD through SD. As long as the clock (C) inpnt is ar logic I, the outpxts of fte D-t-vpe ltip-flops follow fte logic level of the data applied to their cor respondinginputs.When C is swilchedro logic 0, fte current contenlsof tbe D type fiip flops de latched. The laiched inrbmation in the flip flopr is not output at data outputs 1Q through 8Q unless the output'control (OC) irpu. of the buffers that fo ow dre larches is at logic 0.IfOC is at logic l, fte outpulsare in ihe high-impedancesrare-Figure 8 25(c) summdizes this operation. In the 8086 microcomputer system, the 20 addresslines (ADo AD 5, A 6 Ar,) and the bank higlr enable signal BHE a.e nomally la.ched;n ihe addressbus latch. The circuit configuration shown in Fig. 8 26 can be used to latch these signals.Fixing OC at the 0 logic le\€l permanendyenableslalched outputs AoL rhrough AreL and BHEL. Moreover. thc addressinformation is latched at the outputs as the ALE signal ffom the bus controller returns to losic 0 that is, when the CLK itrput of all devices is switched io logic 0. In general.it is importail to m;nimize the propagationdelay ofihe addresssignals as they go through the bus in erface circuit. The switching propeny of the 7,1F373latches that deternine this delay for.he cncuit of Fig. 8 26 is called enableao-output propagation d?ldJ and has a maxirnum value of 13 ns. By selecting fasi latches that is, iatches with a shoner Fopagation delay time a maximum amount of the 8086's bus cycle tirne is preservedfor fte accesstimc of the memory deviccs.In this way slower. lower cost memory ICs can be used. These latches also provide bulTering for the 8086 s address lines. The outpuis of the latch can sint a maxnnum of 2,1 lnA.

356

lhe 80aa and 4086 Microorocesso6

Chao I

0c iD

10

m

20

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30

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m ao

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Enabl€C

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LHL

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z

Figure 8-25 (a) Block diaSm of d @ta] D'rype latch. (b) Circuit diagm of the 74F373. (CouJtesyof Texas lnstrumentsIncorporated)(c) Operation of the 74F373. (Courtesyof TexasInstrum€ntshcorpoFted).

''lll t-Tv oc

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tl Ir* I

t

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iLl

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Addresslatch cjrcuit.

Bank V/rite and Bank ReadControl Logic The memoryof the 8086 nicrocomputer is organizedin upper andlower banks.Il requiressepdratewrire dnd read control signaisfor the rwo banks.The logic circuit in Fig. 8 27 showshow the bank wdte contlol signals.wRu lbr the upper bank and wR! for the lower bank can be generaiedfrom lhe bus controller signalsWRTC, the address buslarchsignalsAoLandBmL. Two OR gatesareusedfor thispurpose. Similar io the bank wdte conirol logic circuit. the bant rcad contol logic circuii can be designedto generaleRDu. the read for the upperbank of memory.and RDb the readfor the lower bank. Figure 8 28 illustratessuch a circuit. Note that ihe circuit uses the MRDC signalfrom the bus controller

DataBusTransceivers 'lhe

dala bush lnsceiNerblock of the busintertacecircuir cm be implementedwith 74F245octalbustransceiver ICs-Figure8 29(a)showsa blockdiagramof this device. Nole thati1sbidirectional input/ourput IinesarecauedAj throughAs andB I drough Bs. Lookingat the circuitdiagramin Fig. 8 29(b).we seedut the G inputis usedto enable

t6a

The 8088 and 8086 Microprocessors Chap. I

1432

Figurc 8-27 Ba'k wite controllogic. the buffer for op€ration.On the other h'ind, the logic level at the direction (DIIR) input selectsthe direction in which data are transfen€dthroughthe device.For instarrce,logic 0 at this input setsthe transceiverto passdata{iom the B lines to the A lines. Siwitching DIR to logic I reversesthe direction of datatlansfer. Figure 8-30 showsa circuit that implementsthe databus transceiverbl,ock of the businterfacecircuit using the 74F245.For the 16-bit databusof the 8086micr(rcomputer, two devicesarerequired.Here the DIR input is ddven by the signaldatatransr"ioit/receive (DT/R), and G is supptiedby data bus effable(DEN). Thesesignalsaie outlputs of the 8288 busconholler Another key function of the data bus hansceivercircuit is to buffer t.loe &ta bus lines.This capability is definedby how much currentthe devicescan sint at rheir outputs. Ihe IoL rating of the 74F245is 64 mA.

BHEL MRDC

7432 FigureE-2E Banl readcontrollogi..

5e..a.l2

Memory Interface Circuits

36t

Figure 8-29 (a) Block diaeramof the 74F2450cl2l bidirecrionalbus tmsceiver (b) Circuir diagramof tle 74F245.(Coudesyof Texaslnstro-

Addft 3ssDecoders A s shownin Fig. 8-31, the adnrcssdecodern Ae 8086 micrdcomput€rsystemis located at the output side of the addrcsslatch. A typicat device used to pelfolm this de.ode1:unctionis fte 74F139dual2line to 4line decoderFigures8 32(a)and(b) show a block diagrarnand circuit diagram for tbis device, respectively.When the enable(G) input is r at its actrve0 logic level, the output conespondingto the code at the BA inputs

t70

The 8088 and 8086 Micfoprocessors Chap. 8

:N

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Mic,op@s$d d.ta b6

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74F245

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Databustransceiver circuit.

switches.o the 0logic level. For instance,whenBA : 01, outputYr is logic 0. The table in Fig. 8-32(c) summarizesthe operationof the 74F139. The circuit in Fig. 8 33 employsthe addrcssdecoderconfigurationshown in Fig. 8 31. Note that addressLinesArTL and ArsL are applied to the A and B inputs of the /,1flJq decoder.fte addressline Aror i( usedro erableone ol rbedecoders and {r,r. obtainedusing an inverter,enablesthe seconddecoderol the 74F139.Eachdecodergeneratesfour chip enable(CE) outruts. Thus both decodersof the 74F139togetherFoduce the eight outputsCEottuough CE7.

M crop'@e$r

dddr*

bus

Figure 8-31 Sec.8.12

Addressbus connguation with ad.liessdecoding.

Memory Inteface Circuits

371

Y2 Y3

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L2B

Ftgure 8-32 (a) Block diasrm of th€ 74F139 2line to 4line decoder/ denu|iplexer (b) circuit diagrm of the 74F139. (Counesy of TexasInslrunents Incoryorated)(c) oleration of the 74F139 de.oder. (counesy of Texas InstrumentsInco@rated)

372

c& cEr cEr 1Y3

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cE5

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cE€

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74F139 .

Figur€8-33 Add.ress de.odercircuit.

The block diagram of anothercornmonly used d€coder,the 74F138,is shown in Fig. 8-34(a). The 74F138is similar to the 74F139,exceptthat it is a single three-Iineto eight-line decoder The circuit usedin this deviceis shown in Fig. 8-34(b). Note that it can be usedto produceeight CE ouQuts.The table in Fig. 8-34(c) descdbesthe opera tion of the 74F138.Here we find that when enabled,only the output that corespondsto the codeat rhe CBA inputs swirchesto the active0 logic level. The circuit in Fig.8 35 usesthe 74F138to generatechip enablesignalsCEotbrough CE7by decodingaddresslinesAr7L.ArsL, andArrL. Connectingthe enableinputsto +5V and groundpermanentlyenablesthe decoder.The advantageof using the 74F138overthe 74F139for decodingis that it does not re4uire an extra inverto to genemteeight chip enablesisnals.

sec.8.12

MemorylnterfaceCkcuits

313

YO

\2 Y3

Y5

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Y6 Y7

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(c)

ol-:T::: 8-34 Frsure - d' qb.kdT.cr-al,' rcorp"rar'"' '''lf .ff"iJ,i'"T'iii tc;unes\ of Te\as Ins!ruments | licorPonre! ln\mments (CounesyofTe\as "ifll,T

cBz cE3 cE4

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Figure E-35 Addres decodercircuit using74Fi38.

B. i3 PROGRAMMABLE LOGICARMYS In the last section we found that brsic logic devicessuch as latches,tiansceivers.and decodersare rcquired in the bus interfacesectionof the 8086 microcomputersystem.We showedthat thesefunctionswercperformedwith standardlogic devicessuchasthe 74F373 octal imnsparenilaich,74F245 ocral bus tansceiver and 74F139 two-tne ro four-line decodet respectively.Todayprcgrunnable logic aftay (PLA) devicesare becomingvery impotant ir the desigr of microcomputersystems.For example,addressandcontrolsignal decodingin the memoryinterfacein Fig. 8-24 canbe inplemenled with PLAS.insteadof with sepaEtelogic ICs. Unlike the earlier mentioneddevices,PLAS do not implementa specificlogic function.Instead,rlEy arc general-purpose logic devic€sdlat havefie abiliry to perfonn a wide variety of specializedloglc tunctions.A PLA containsa general-purpose AN'D OR NOT aray of logic gate circuits. The user has the ability to interconnectthe inputs to the AND gatesof this array.The defnition of theseinputs determinesthe logic functionthat is implemented.The processusedto connector disconnectinputsof lhe AND gateanay is known asprosldnm,n& which leadsto the nameprogrammablelogic array.

PLA5.GAt"s.and EPLD5 A variety of different types of PLA deviceslre available-Early deviceswere atl manufacturedwith the bipolar semiconductorprocess,Thesedevicesare referred to as PALi aDdrenain iD usetoday.Bipolar devicesarc programmedwith an interconnectpal tem by burningout fuse links widin the device.ln the initial state,all of thesetuse links are intact. During pmgramming.unwantedlinls are open-circuitedby injecting a current sec 8.13

ProgrammableLogicArrays

375

tlmugh the fuse to bum it out. For this reason,once a device is programned it cannot be reused.If a design rnodificaiion is required in the pattem, a new device must be prograrnrnedand substitutedfor the original device.Since PALSare madewith an older bipolar technology,they lre limited to sinpler funcrions and characrerizedby slower operatingspeedsandhiSh power consumption. Newer PLA devicesare manufacturedwith the CMOS process.With this Focess' very complex, high-speed,low-power devicescan be made.Two kinds of CMOS PLAS arein wialeusetoday; the GA, andthe tPrD. Thesedevicesdiffer in the type of CMOS technologyusedin their design.GALS are designedns:j..gekcti&ll, erasableftttd'onlv r1?r,orl (E':ROM) technology.The inpuroutput operationof this device is determined by rhe p.ogranming of cells. Theseetectricallyprogrannnablecells are also electricallv efasable.For this reason,a GAL can be used for one apPlication'erased,and then reprogrammedfor anotherapplication.EPLDS are similar io GALS in that thev can be programmedreraseal,and reused;however,the erasemechanismis different. They are manufacturedwith electricallr prcSrannable read onb memory(EPROM) technologv That is, they employ EPROM cells inst€adof E'zROMcells. Therefore,to be erasedan EPLD must be exposedto ultraviolet lighi. GALS and EPLDS are cunently the mosa rapidly growing segmentsof the PLA marketplace.

Block Diagram of a PLA The block diagramh Fig. 8 36 rcprcsentsa typical PLA Looking at this diagram, we seethal it has 16 input leads,marked Io through IL5 There are eight output leads' labeledF0 lhrough F7.This PLA is equippedwith ttue€-stateoutputs For this reason.ii hasa chip-enableconaol lead.In the block diagram.fiis control input is narked CE. The logic level of CE determinesif the outputsare enabledor disabled. When a PLA is used to implement random logic firnctions. the inPuts represent Booleanvariables,and the outputsare usedto provide eight separaterandomlogic func_ tions. The intemal AND OR-NOT army is programmedto definea sum-of-productequation for eachof lheseoutputsin tems of the inputs and their complemenlsln this way,

Figure E-36 Block diacIm of a PLA. (Reprlited wilh the permission of WalterA. Tri€bel)

376

The 8088 and a086 Microprocessors chap. 8

we seethat the logic levels applied at inputs I0 tbrough Ir5 and the Progaaming of the AND arraydeterminewhat logic levels areproducedat outpul'tFotbroughF7.Therefore, the capacityof a PLA is measwedby thee Fopertiesr the numberof inputs,the number of outputs,and the numberof productterms (P-tems).

Architectureof a PtA Wejust pointed out that the circuitry of a PLA is a generalpurPoseAND-OR-NOI aray. Figue 8 3?(a) showsthis architecture.Herc we seethat the input buffen supply input signalsA andB andtheir complemenisA andB. Programmableconnectionsin the AND aray permit any combinationof these inputs to b€ combinedto form a product term. The Foduct term outputs of the AND array are supPliedto fixed inputs of the

*".,1 *t t-

I I

F=AB+AB

= (b) 44E l!:_37 G) BasicPLA archilectue. Inllenenting the losic tunctionF (AB + AB). sec.a.l3

Programmable LogjcAfays

317

OR array.The output of the OR gateproducesa sum-of-productsfutction. Finally, the r n l e r t e fc o m p l e m e n ttsh i s f u n d j o n .

The circuit in Fig. 8 37(b) showshow dre functionF - (AB + AB) is implemented widl the AND OR NOT aray. Notice that an X markedinto theAND arraymeansthat th€ fuseis left intact,andno markingmeans!ba!it hasbeenblown to folm an opencircuii. Rr ihis reason.the upperAND gateis connectedto A and B and Foduces the productterm AB. The secondAND gatefrom the top connectsto A andB to producethe Foduct term AB. The bottomAND gaG is markedwith an X to indicatefiar it is not in use.Cateslike this that arc not to be activeshouldhaveaI of their input tuseLinksleft inlact. Figurc 8 38(a) shows the circuit structurethat is most $ridely used in PLAS. It differs from the circuit shownin Fig. 8-37(a) in two wals. First, the inverterhas a programmablethre€-statecontrol and can be usedto isolate the logic function Aom the oul_ put. Second,the bnffered output is fed back to fbnn anolherset of inputs to the AND array.This new output conligumlion permitsthe outputpin to be progJallllrcdto wo* as ^ standardautput, standad input, or logic-cantrcllzd inputlor,tput For instance,if the upperAND gate.which is the control gatefbr the output buffer is set up to permanendy enablethe inverter and the fuse links for ils inputs that arc fed back from lhe outputsare all blown open,the output functions as a standardoutput.

OIJTPUT

Kt-

CLOCK

INPUT

(b)

FEEOSACK

rigu.e 8-38 (a) Tylical PLA archltecture.(Counesy of Teaaslnslrunents IncorpoEted) (b) PLA *nb output larch. (courlesy of TexasI.strunent$ Incorporated)

374

lhe 8088 dnd 8086 Vr.'op.ocessoA

Chcp. 8

PLAS are also available in {'hich the ou9uts are Iatched with registers Figure 8-38(b) showsa circuit for this rypeof device.Here we seethat the ouFut of $e OR gate is appliedto the D input of a clockedD t)?e flip-flop In this wav' the logic level produced by the AND OR array is not presentedat the ouiput until a pulse is first applied at the CLOCK input. Futherrnore,the feedbackinput is Foduced ftom the complement€dout pui of ihe flip-flop, not the outputofthe inverterThis configurationis known asa PL4 unn re|isteredoutputs atrdis designedto sirnpliry implenentationof state,?4.*r,e designs'

StandardPALruDevices Now that we bave introducedthe rypesof PLAS, block diagram of tlle PLA' and internal drchitectureof the PLA, let us continueby examini4 a few of the widely used PAL devices.A PAl, or a programmableanay logic, is a PLA in which the OR arav is fixed; only the AND array is programmable The 16L8 is a widely used PAL IC. lts intemal circui.rv and pin numberingare shown in Fig. 8-39(a). This device is housedh a 2Gpin package'as shown in Fig 8-39(b). Looking at this diagam. we seerhat it employsthe PLA drchitectue illustrated in Fig. 8-38(a). Note that it has 10 dedicatedinput pins. All of.hese pins are labeledI' There are also two dedicatedoutputs,which are labeled with the letter O' and six pro grarnmableI/O lines,which are labeledyO Using fte programmableI/O lines' rhe num ber of input lines canbe expandedto as many as 16 inputs or the Nmber of outputscan be increasedto a5 many as eigh. linesAll the 16L8's inpuLsare bufferedand produceboth the original form of the signal and its complement.The outputsof the butrer are appliedto the inputs of the AND arrav' This array is capable of producing 64 product terms- Noie that the AND gates are arrangedinto eight groupsof eiglt. The outputsof sevengatesin eachof thesegoups are usedas inputs 1oan OR gate, and the eighth ouFut is used to p.oduce an enablesignal for the correspondingtlEee-stateoutputbuffer' In this way. we seethd rhe 16L8 is capable of producingup to sevenFoduct termsfor eachourpu! andthe Foduct ierms canbe formed using any coqbination of lie 16 inputs The l6L8 is manufacturedwith bipolar t€chnology-It operates{iom a +5V :l:109' dc power supply and drawsa maximum of 180aA. Moreover,all it! inpuis and outputs are at TTL compatiblevoltagele\€ls. This deviceexhibitshigh-speedinpui-outputpropagationdelays.In fact, the maximum l-to-O Fopagation delay is ratedas 7 ns Anotherwidely usedPAL is the 20L8 devic€.l-ooking at the circuitv of this device in Fig. 8-40(a), we seethat it is similar to that of the 16L8jusr described Howeve! the 20L8 has a maxim m of 20 inputs, eight outpuls, and 64 P terms. The device's24-pin packaseis sllown in Fig. 8 40(b) The 16R8is also a popular20 pin PLA. The circuit diagramal}dpin lavout for this device;re shown in Figs. 8-41(a) and O), rcspectively.FIom Fig. 8 41(a), we find that its eight fixed I inpursand AND-OR array are essedially the sameas thoseof the 16L8' Thereiii oDechnge. The outputsof eight AND gates.insteadof seven,are suppliedto the inputs of eachOR gare. A numberof changeshavebeenmadeat the ouiput side of the 16R8-Note thai the outputsof the OR gatesare fiIst latchedh D type flip-flops wirh the CLK signal Thev are then bufferedand suppliedto the eight Q outputs-Another charge is tbat the enable Sec.8.l3

ProgrammableLogicAffays

37t

tE vo

tll] "o

!l 'o

rigure 8-39 {a) l6L8 circuit diaSrd. (Counesy of Texar lnslrumentsIncor?orated) (b) 16L8 pin layout. (Couliesy ofTexas Ilstrumenis Incorporated)

380

Figure 8-40 (a) 20L8 ctcuit diagram. (Courtesyof TexasInstrumentsIncorporated) (b) 20L8 lin layout. (Courtesyof Texashstrumenls lncorporaled)

3Al

6,:':

Figure 8-41 (a) 16R8 cncuir dia81am.(Couresy of TexasInstrutnerts lncorporated) (b) 16R8pin layout. (Couresy of TexasInstrunents lncorporated)

342

srgnalsfor the ootput invertersale no longer prognmmable. Now the logic level of the OE control input enablesa[ three-stateoutputs The last changeis in the part of the circuit that Foduces the feedbackinpuis ln the 16R8,theseeight inpu! signalsare derivedftom ihe complementaryoutput of the collespondinglarch insteadof the output of the buffer' Fo. this rcasoq the ouq)utleadscanno longer be pro$ainmed to work as direct inputs. The 20R8is the registeroutputvenior of the 20L8 PAl Its circuit dia$am andpin layout are give! in Figs. 8 42(a) atrd(b). respectively

ExpandingPtA CaPacity Sone appiicationshaverequimmentsthat exceedthe capacityof a singlePLA IC- For instance,a 16L8 devicehasthe abiliry to supply a rnaximumof 16 inputs' 8 outputs.and 64 productterms.ConDectingseveraldevicest€erher canexpandcapacityLei us now look a! the way in which PLASare intercomectedto expand$e numberol inputsandoutputs. ff a single PLA does not have enoughoutputs,two or more devicescan be connectedtogelher into the configurationof Fig. 8 43(a) Here vr'esee that the inputs I0 through Ir5 on the two devicesare individualy connectedin parallel This connection doesnot changethe numberof inputs. On the olher hand, the eight outputsof the two PLAS are separatelyusedto form the upper and lower btaes of a 16-bit output word. The bits of this wod are denotedas OothroughOr5.So with this conneciion,we havedoubledthe numberof outputs. \vhetr data are appliedto the inputs, PLA I outputsihe eight leart significantbits of data.At the sameinstantPLA 2 outputsthe eight most significantbits Theseoutputs can be usedto representindividual logic tunctions. Another limitation on the apPlicationof PLAS is the numberof inplrts-The ma,\r mum numberof inputs on a single 16L8 is 16.Howevet additionallcs can be connecled to expandthe capacityof inputs Figue 8-43(b) showshow oneadditionalinput is added This permits a 17-bit input denoredasIo through116The new bit 116is suppliedtbrough invertersto the CE inputs on the two PLAS.At the output side of the PLAS, outputsOo through 07 of the two devicesare individually connectedin paralel. To inplemenl this ourpulcmuslbe rsed or three-\tale coMeclion.PLA detrce'$i!h open-colle{lor the devicefor operation' This embles PLA 1 is logic 0. When 116is logic 0, CE on at Ootbrough07- At the I0 tfuough Ir5 are output andthe oulput functionscodedfor input Making the logic level of rernains disabled sameinstant,CE on PLA 2 is iogic 1 and it through Ir5 causes input at Io 116equalto 1 disablesPl-A 1 aDdenablesPLA 2 Now ihe this con07 Actually, the output function definedby PLA 2 to be output at Oo through inputs the number of nection doublesthe numberof Foduct terms as well as increases

OF INPUT/OUTPUT 8,I4 TYPES The input/output system of the microprocessorallows peripheralsto provide data or receiveresults of processingtbe data.This is done using I/O ports The 8088 and 8086 microcomputerscan employ two diffemnt types of input/output (I/O): isolakd I/O at].d menory-mappedI/O. Thesel/O methodsdiffe. in how I/O pofts are mappedinto the 8088/8086'saddressspaces.Somemicrocomputersystemsemploy both kinds of I/Osec 8.14

Typesof Input/Output

383

3{

6---i--i----1t--

t;

(a)

{b)

Figure 8-,12 (a) 20R8 circuit diaelam. (Couiresy of TexasInstrumentsIncorporated) (b) 20R8 pin lalour. (Courtesyof Te{as Insrtunents Incorporated)

344

:

llL ..-i_ I I

(a)

outPutwordlength.(Reprifiedwirh tbepenis; Figure8-43 (a)ExPanding sid of WarlerA. Tnebel)(b) Exlandingin?ut woid len$l. (Reprirtedwith of WalierA. Triebel) thepermission

that is, some peripherallcs are treatedas isolaied I/O devicesand oihers as memoryrnappedI/O devices.Let us now look at eachof theseryPesof I/O.

lsolatedInput,/OutPut Wlten using isolatedI/O in a microcomputersystem,the I/O devicesare treated separatefrom memory.This is achievedbecausethe so{iwarcand hardwaxearchitectures oithe 8088/8086supportsepamtememory and I/O addressspaces.Figure 8-zg illustratesthesememory and I/O addressspaces. In our study of 8088/8086softwarearchitectue in Chapter2, we exarninedthese addressspacesfrom a softwarepoint of view.We found that infbrnation in memoryor at sec.Li4

Typesof lnput/Output

345

nemoryand Figure8-44 8088/8086

I/O pofs is organizedas bytes of data; that lhe memory addressspacecontainslM con,".uilu" Uyt" iaa..ttes io the range 0000016through FFFFFL6Iand that the I/O address In Ineran8e0000r' tuoughFFFF" blre add'e'se. .o,...oniuin' O+K.on..cuLi\e of rhi' l/O add'e'csp:ce Herc$e find map more derailel] iho\\s a 45,ar Figure8 that the;ltes of data in rwo consecutiveI/O addrcssescould be accessedas word-wide canbe treatedas and 000316 000216, 000016,000116' data.For instance,l/O addresses byte-widel/O ports.ports0. 1, 2, and3, or pons0 and 1 mavbe considered independenr togetheras word-wide Pot 0. Note that the pan of the I/O ad&essspacein Fig 8-45(a) from address000016 nhrough00FFr6is refered to aspdg€ a Cedain UO inslructionscan only perform operations'topots in this part ofrhe addressrarge Olher I/O instruciionscaninput or output datafor pons anywherein the I/O addressspace This isolatedmerhodof I/O offers someadvantagesFirst, the complete lMbyte memory addressspaceis available for use urith memory' Second' special instuctions havebeenprovided in *re instruction set ol the 8088/8086to perforn isolated I/o inp'rt pedorand ouD; operations.These instruciions have been tailored to maximize I/O musl data transfers output input and all I/O is that of mance.i dis;dvantageof this rype port UO and dre register take piacebetueen the AL or AX

lnPut/OutPut Memory-MapPed I/O devicescan be placedin the memory addressspaceof the microcomputeras pon well as in the independentI/O addressspace.In this cdse,lhe MPU looks at the UO as though it is a storagelocation in memory.For this reason'the methodis known as netnory napped I/O. ln a microcomputersystemwith menory-mappedI/O' someof the memoryaddress m spaceis dedicatedtol/O ports For example'in Fig. 8 45(b) the 4096 memoryaddresses tire rangefrom E0000r6throltgh E0FFFL'jare assignedto I/O devices Here the contents E0000t6 of a