Modeling and Design Optimization of Capacitor ...

Modeling and Design Optimization of Capacitor Current Ramp Compensated Constant On-time V2 Control Yingyi Yan, Fred C. Lee, Shuilin Tian and Pei-Hsin Liu Center for Power Electronics Systems The Bradley Department of Electrical and Computer Engineering Virginia Tech Blacksburg, VA 24061 USA E-mail:[email protected] Abstract — Constant on-time V2 control for point-of-load Buck converters has instability issue in the cases that the output capacitors RC time constants are small. This paper intensively studies the proposed solution using capacitor current ramp compensation, which is a superior solution featuring fast response and universality. A frequency domain small signal model based on describing function method is proposed. The time domain large signal response to the load step change is analyzed. The analysis illustrates the unique transient response behaviors of the capacitor current ramp compensated V2 control. The design optimization methodology based on frequency domain and time domain analysis is presented. The proposed model and the design guidelines are verified by the experimental results.

I.

INTRODUCTION

V2 control is a popular control scheme in Point-of-Load Buck converters and Voltage Regulators for microprocessor [1]. Typically, the inner loop of V2 control feeds the instantaneous output voltage back to the PWM comparator, while an optional outer loop improves the accuracy of output voltage regulation [2]. Constant on-time modulation is preferable for most applications due to the high light load efficiency. Figure.1 shows a constant on-time V2 controlled Buck converter. The equivalent-series-resistor (ESR) of output capacitor plays a critical role in the control loop. Using the output capacitor with sufficient ESR, constant on-time V2 control features fast load transient response [3]. However, the fast feedback loop of a V2 controlled Buck converter with low ESR output capacitors has stability issue [4][5]. The fundamental reason is that the beneficial current sensing signals are diminished and overwhelmed by the ripple at the pure capacitor.

Figure.1 Constant On-time V2 controlled Buck converter

To stabilize the V2 control with low ESR capacitor, there are several viable methods. The first method is compensating the direct feedback loop by adding the inductor current to the output voltage signal. The summed signal is compared with control signal vc to trigger the PWM signal. It has been proved that, using the inductor current ramp compensation, a proper ramp slope to achieve desirable damping factor always exist [6]. However, the inductor current feedback changes the property of the output impedance. The low frequency output impedance is not zero but a resistive impedance. It results in an undesirable droop of output voltage dependent on the load current. The second method is compensating the direct feedback loop by external ramp, as discussed in [7]. The summed signal of vc and external ramp se is compared with output voltage to trigger the PWM signal. This solution does not require the inductor current sensing, and the output voltage droop is eliminated. However, for the constant on-time V2 control, this method cannot achieve proper damping for the control loop in the cases with large duty cycle [7]. Figure.2 shows the controlto-vo transfer function of V2 controlled Buck converter operating at large duty cycle. It is seen that, increasing external ramp cannot effectively damp the double pole effect. Instead, it pushes the high-Q double poles to lower frequency.

Figure.2 Transfer function vo(s)/vc(s) of constant on-time V2 control operating at D=0.9 and compensated by external ramp (se_k is a normalization constant defined in [7])

There are some other solutions based on the modifications of the methods mentioned above. Reference [8] combines external ramp and inductor current ramp compensation. It does not eliminate the droop issue and make the controller more complicated. Reference [9] inserts a DC blocking high pass filter in the current feedback path to eliminate the droop of output voltage, but the design of the high pass filter is a dilemma. This method hardly achieves a well-damped and fast transient response. Conceptually, V2 control is equivalent to a current mode control with load current feedback. Sensing the capacitor current by ESR is equivalent to sensing both the inductor current and the load current simultaneously [3]. The inductor current feedback stabilizes the loop while the load current feedback provides the fast transient response. The common problem of the aforementioned solutions is violating this nature of V2 control, since the added signals are not the capacitor current signal, so the outcomes are not as good as V2 control with large ESR capacitors. Section II will describe the V2 control with capacitor current ramp compensation. The small signal model will be presented in section III. The time domain analysis and the design optimization methodology are discussed in section IV. Section V is the experiment verification. II. V2 CONTROL WITH CAPACITOR CURRENT RAMP COMPENSATION People have paid attention to the feedback of load current since three decade ago. The load current signals were added to the current mode control [10][11][12] and voltage mode control [12][13] for the load transient improvement. Recently, the techniques of sensing the capacitor current non-invasively have been proposed [14][15][16]. The calibration techniques further made it possible to precisely sense the instantaneous capacitor current [17][18]. As a result, the capacitor current compensation of V2 control is becoming a viable and attractive solution [14][15][16]. In order to differentiate with the V2 control, these solutions are referred to as V2Ic control in [14][16]. The concept of the capacitor current compensated V2 control is illustrated in Figure.3, where Ks is the capacitor current signal amplification gain. Compared with other compensation methods, the capacitor current compensation for constant on-time V2 control improves the loop stability for all duty cycle while the property of ultra-low output impedance is preserved. The output capacitor current is added to the output voltage, and the summed signal is fed to the PWM comparator.

Figure.3 Conceptal diagram of V2 control with capacitor current ramp compensation

The capacitor current injection benefits the V2 control scheme in several aspects. With the enhanced capacitor current information, the total feedback ripple is dominated by the virtual ESR ripple. Since the sensed capacitor current ripple can be sufficiently amplified, the jittering issue can be improved by this method. As capacitor current does not have DC bias, it is easy to see that the output voltage droop is eliminated. The capacitor current can be estimated in different ways. Redl [10] used a current sensing transformer to sense the capacitor current. The true sensing is reliable but the transformer is bulky. Yousefzadeh [13] and Liu [21] used an A/D converter and a digital counter to estimate the capacitor current. No external component is needed; however, the delay is undesirable. Peterchev [12] and Yan [15] used a passive branch in parallel with the output capacitor to extract the capacitor current waveform. It is a real time estimation but requires the ESL effect is minimized. M. del Viejo [19] proposed an active operational amplifier circuit to observe the capacitor current. This method cancels the ESL effect by the inductive input impedance of the amplifier. Another way by Cortes is the V1 implementation integrating the fast loop and the slow loop proposed. It is cost effective and flexible [20]. The prior arts did not provide a completed control loop design guideline V2 control with capacitor current ramp compensation. This paper would focus on the frequency domain and time domain modeling and provide the design guidelines. In order to thoroughly understand the small signal properties of the constant on-time V2 control with capacitor current ramp compensation, a small signal model is proposed and presented in section III. III. SMALL SIGNAL MODELING The nonlinear entity consists of switches, the output voltage, the comparator, and the on-time generator. A sinusoidal perturbation with a small magnitude at the frequency is injected through the control signal; then, based on the perturbed

output voltage waveform, the describing function from the control signal to the output voltage can be found by mathematical derivation.

Figure 4 Pertrubed waveforms of V2 control with capacitor current ramp compensation

Following the modulation law of constant on-time control, the duty cycle and the output voltage waveforms are shown in Figure

4.

Since

the

on-time

(Ton)

is

fixed,

the

off-time

is

modulated

by

the

perturbation

signal:

vc (t )  r0  rˆ sin( 2f m  t   ) , where r0 is the steady-state dc value of the control signal, rˆ is the magnitude of the perturbation, and θ is the initial angle. Based on the modulation law, it is found that

vc (ti 1  Toff (i 1) )  snTon  s f Toff (i ) 



ti Toff ( i )

ti1 Toff ( i 1)

[iL (t ) 

vo (t ) ]dt RL

(1)

Co

 vc (ti  Toff (i ) ) where Toff(i) is the ith cycle off-time, Ls is the inductance of the inductor, the up and down slopes of the total ESR feedback signal are Sn=(Vin-Vo)(1+Ks)RCo/Ls, Sf=Vo(1+Ks)RCo/Ls, where Co is the capacitance of the output capacitors, RCo is the ESR of the output capacitors. RL is the load resistor, iL(t) is the inductor current, and vo(t) is the output voltage. Based on (1), Toff(i) can be calculated. The perturbed duty cycle and the perturbed inductor current can be expressed. Then, Fourier analysis can be performed on the inductor current to derive the Fourier coefficient cm(iL) at the perturbation frequency for the inductor current. Further, the Fourier coefficient of the output voltage cm(vo) can be calculated. Therefore, the describing function (DF) from the control signal to the output voltage can be calculated as:

cm ( v ) cm (i ) vo ( f m ) R ( R C j 2f m  1)    j o   j L  L Co o vc ( f m ) re /(2 j ) re /(2 j ) ( RL  RCo )Co j 2f m  1







In the s-domain, the control-to-output transfer function can be expressed by:

vo ( s )  vc ( s )

1 ) RLCo s V RL ( RCoCo s  1)    in Toff Vo Ton  Tsw  sTsw Ls s ( RL  RCo )Co  s  1 R 'Co (1  )  (1  )e Ls 2Co R 'Co 2Co R 'Co f s (1  e sTon )(1  e sTsw )(1 









where R'Co  RCo  K s RCo A similar method in [6] is used to simplify the transfer function as follows: vo ( s) ( RCoCo  s  1)  vc ( s) [1  s  ( s ) 2 ]  [1  s  ( s ) 2 ] 1Q1 1 2Q3 2

(4)

Tsw where 1   , Q1  2 , 2   , Q  3 Ton  Tsw ( R'Co Co  Ton / 2)

The simplification is valid for up to half of the switching frequency. When the duty cycle is relatively small and the ESR zero of output capacitor is well beyond half of the switching frequency, the transfer function can be further simplified as: 

vo ( s )  vc ( s) 1 

 1 s s 2 ( ) 2Q3 2

 





(5)

From the transfer function, it is clear that the double poles at half of the switching frequency may move to the right halfplane according to different parameters of the capacitors. The critical condition for stability is R’CoCo>Ton/2, which clearly shows the influence of the capacitor current sensing gain. The output impedance can be also derived based on a similar methodology. A sinusoidal perturbation with a small magnitude at the frequency is injected through the output current; then, based on the perturbed output voltage waveform, the DF from the output current to the output voltage can be found out by mathematical derivation.

(a) vo(s)/vc(s)

(b) Output impedance Zo

Figure 5 Small signal transfer functions with different Ks(Vin=12V, Vo=1.2V, fsw=300kHz, Ls=600nH, Co=8∙100μF, RCo=1.4mΩ/8=0.175mΩ)

In the s-domain, the output impedance is derived as (6) and simplified as (7) as follows: fs 1 (1  e sTon )(1  e sTsw )( R 'Co  ) sf Co s Vin 1 Z o (s)  [  1]  ( RCo  ) Toff 2Ton  Toff  sTsw Ls s Co s (1  )  (1  )e 2Co R 'Co 2Co R 'Co [

( R 'Co Co s  1) 1  1]  ( RCo  ) s s 2 s s 2 C os [1   ( ) ]  [1  ( ) ] 1Q1 1 2Q2 2

(6)

When the duty cycle is relatively small and the ESR zero of output capacitor is well beyond half of the switching frequency, the output impedance can be further simplified as: T T (1  D 2 ) Z o ( s )  { on [ on  RCo (1  K s )]  2 } 2 2Co 2 Co

s 1

s Q32



s2

22

(7)

The Bode plot of the output impedance is shown in Figure 5(b). The quality factor of double poles (Q3) reduces as Ks increases, so the double pole peaking of output impedance at half of the switching frequency is damped. When Q3 is too low with over designed Ks, the double poles are over-damped and become two split single poles. The pole at lower frequency determines the settling time of transient response. Using the Low-Q approximation, the low frequency pole is at:

 L  Q32  1/(R'Co Co )

(8)

In this example, when Ks is much higher than 8.57, the split low-frequency pole causes Vo/Vc gain in (5) reduces, and it also becomes the dominant single pole of Zo in (7).

Based on the small signal model, selecting a Q around 0.6 to 1 is reasonable. As a voltage regulator, it is desired that the output voltage exactly tracks the reference up to highest possible frequency. A high Q double pole has peaking effect, while a low Q double pole makes the gain roll off at lower frequency. From output impedance point of view, high Q peaking leads to large transient deviation, but too low Q is also undesirable due to the long settling time. Overall, a medium Q around optimal damping (0.707) is a reasonable choice.

IV. LARGE SIGNAL ANALYSIS AND THE DESIGN OPTIMIZATION A.

The characteristics of the load transient response

The small signal model indicates that the system is a second order system, and predicts the stability boundary and the stability margin. The small signal model implies that increasing the capacitor current amplification gain would increase the damping the system double poles at half of the switching frequency. The proper Ks providing optimal damping always exist, which is supreme to the external ramp compensation [7]. Overdesigning this gain leads to a long settling time according to Eq.(8). This time constant would be also explained in time domain according to the control law given the duty cycle is not saturated. In average sense, the control law is keeping the sum of capacitor current and capacitor voltage a constant. It is easy to find out the settling time constant R’CoCo by solving this differential equation Eq.(9).

R'Co Co

dvCo  vCo  Const. dt

t(us) Figure.6 The 5A load step transient with different capacitor current sensing gain (Vin=12 V, Vo=1.2 V, Ls=600 nH, fsw=300 kHz, Toff_min=800nS, Co= 100 μF×8, RCo=1.4 mΩ/8, RL=0.1 Ω, load steps occur at the beginning of on-pulses)

(9)

However, for design purpose, small signal model has limitations. Small signal model is justified around an operating point, but large signal response involves multiple operating points. Meanwhile, small signal model ignores the time variant nature of the switching converter, so that the behavior in switching period scale is not modeled. The V2 control is so fast that the large signal response to the load step transient cannot be fully depicted by the small signal model. Some literatures even considered it as a combination of liner and non-liner controls [22]. First, Figure 7(a) shows that the load step response overshoot magnitudes vary dramatically, depending on the instant of transient current applied in a switching period. The impact of switching acting latency on load transient response has been reported in [16][25], and a solution for constant frequency V2Ic control was proposed in [16]. Second, the settling pattern of the transient response is dependent on the magnitude of the load current step change. Figure 7(b) shows that the output voltage response to a small load step is wellbehaved but the response to a large step is oscillatory. Third, the step up response is very different from the step down response in magnitude and shape for a given design. Fourth, Figure.6 shows an interesting phenomenon that the overshoot magnitudes are not changed with Ks, although Figure 5(b) shows that the peaking of small signal output impedance is reduced by increasing Ks. For these reasons, it is necessary to study the optimization not only in the frequency domain, but also in the time domain [23].

(a) vo response to load steps at different instants

(b) vo response to load steps with different magnitudes(KsRCo=3mΩ)

Figure 7. The nonlinearity of load transient response

B.

Time domain analysis In this section, the load step up and load step down responses will be analyzed respectively. In the rest of the paper,

the parameters and symbols defined here will be used. As illustrated by Figure.8, the symbols Irip, sni, sfi denote the half of the capacitor current ripple, the current ramping-up slew rate during on-time and the ramping-down slew rate during offtime. Due to the practical implementation reasons, most of the constant on-time controllers have a minimum off-time

Toff_min between adjacent on-pulses. sni_a is the current ramping up slew rate when the off-time reaches to minimum offtime, while Isu denotes the incremental current in a period of Ton+ Toff_min. When the on-time saturates during load transient responses, the current waveform is a zig-zag waveform. Figure.8 illustrates this waveform in the load step up response. The capacitor current is the thin solid line. In order to simplify the calculation, it will be equivalently represented by the thick dash-dot straight line, which has the same slew rate sni_a and an offset If .

Figure.8 The illustration of the capacitor current waveform and symbols

The Irip, sni, sfi, sni_a, If, Isu are calculated by the following equations:

I rip 

sni _ a 

(Vin  Vo ) / Ls  Ton 2

sni  (Vin  Vo ) / Ls

(11.1)

s fi  Vo / Ls

(11.2)

(Vin  Vo ) / Ls  Ton  Vo / Ls  Toff _ min

First, the load step up response is investigated.

(10)

Ton  Toff _ min

(12)

I f  Toff _ min  (s fi  sni ) / 2

(13)

I su  Ton sni  Toff _ min  s fi

(14)

In the worst case, the load step occurs at the end of a steady state period as the energy stored in the circuit is minimum. Ideally, with the load step change Istep, the converter can settle to the new steady state with one “on” interval and one “off” interval. Figure.9(a) illustrates the ideal transition process under the load step up perturbance. At t0, the load step occurs and the vFB=R’Co∙iCo+vCo immediately drops below vc, so the modulator is saturated to maximum duty cycle. The capacitor current ramps up to zero at t=t1 and continues to saturate the on-time until t=t2. The top switch is turned off when the iCo equals to Ip_ideal at t2. The vo continues to slew up and iCo ramps down until t=t4 . In the ideal scenario, the charge taken out from Co between t0~t1 and t3~t4 equals to the charge supplied between t1~t3, while the current at t4 is the same as the current at t0-. Then, the system enters the new steady state after t4. Based on the capacitor charge balance [24], this process is described by the following equation:

I P _ ideal 2sni _ a

2



( I P _ ideal  I f ) 2 2s fi



( I Step  I rip  I f ) 2 2sni _ a



I rip

2

2s fi

(15)

However, generally, the current trajectory does not stop ramping up at t2, because the constant on-time pulse would not be truncated in the middle. As a result, the Co is over charged and it results in a ringing of vo, as shown in Figure.9(b).

Figure.9 The illustrations of the load step transient responses

The practical optimal design without oscillatory response can be achieved by the practical optimal capacitor current trajectory with two “on” intervals and two “off” intervals, which is illustrated by Figure.10.

Figure.10 The optimal capacitor current trajectory of step up response

In order to get the minimum undershoot and the shortest settling time, the optimal response turns on the top switch from t0 to t5, which contains Non constant on-time. Non is the greatest integer keeping the peak current Ip_actual below Ip_ideal:

 I P _ ideal  I rip  I step  I f  N on  Floor   I su  

(16)

I P _ actual   I rip  I step  I f  N on I su

(17)

After t5, the top switch is off until the summed signal VFB intersects the vc and initiates a constant on-time at t6. After this on-time expires, the capacitor current ramps down to –Irip at t7 and the comparator also triggers an on-time at the same moment. It means that the converter enters a new steady state at t7. In order to allow the capacitor current trajectory follows this optimal curve, the current value Ivu at t6 is determined by:

I vu  Tsw 

I P _ ideal 2sni _ a

2



( I P _ ideal  I f ) 2 2s fi

 I P _ actual 2 ( I P _ actual  I f ) 2     I rip  Tsw  2s fi  2sni _ a 

According to the condition that an on-time is triggered at t6, the optimal R’Co_up for step up response is derived:

(18)

I P _ actual  ( I rip  I step  I f ) R'Co _ up 

2

N on (Ton  Toff _ min ) 

I P _ actual  I f  I vu I P _ actual  I f  I vu 2

( I vu  I rip )  Co

s fi

(19)

Second, the load step down response is investigated in a similar way. The worst case is the load step occurs at the beginning of an on-pulse. Figure.11(a) illustrates the optimal scenario of the vo response. At t0, the load step occurs but the top switch does not turn off until the on-time expires. Then, the modulator keeps the top switch off and the capacitor current ramps down to zero at t=t1 while the vCo reach to its peak overshoot. The iCo continues to ramp down until vFB=iCo∙RCo’+vCo equals to vc at t=t2. In the optimal response with shortest settling time, the top switch will turn on at maximum duty cycle after t2. The charge is balanced right when the capacitor current equals to –Irip at t=t3.

Figure.11 The illustrations of the load down transient responses

The charge balance condition is described by:

I stepTon 

( I step  I rip ) 2 2 s fi

2 I vd  I rip I vd  I rip I vd  ( If ) 2 s fi 2 sni _ a

(20)

Since an on-time is triggered at t2, the optimal virtual ESR for step up response is derived by:

 ( I step  I rip ) 2 I vd 2  1 R'Co _ dn    I stepTon   ( I vd  I rip )Co  2s fi 2s fi 

(21)

If the R’Co is smaller than the optimal value, the iCo has ramps down to a lower value after t=t2 in order to trigger an ontime. As a result, the capacitor will be over discharged even the top switch saturates the maximum duty cycle. This results in the ringing of vo as shown in Figure.11 (b). If the R’Co is over designed, the settling is longer than the optimal design. C.

Design Guidelines

As a fast control architecture, the capacitor current compensated V2 control exhibits some unique properties, which are not observed in the conventional linear controls, as shown in Figure 7. First, the voltage deviation of transient response is dependent on the timing of load step. The maximum load step Istep_max occurs at the beginning of an on-pulse causes the maximum transient deviation. Second, the overshoot of load step down response is almost independent on the Ks design, as shown in Figure.6. The time domain analysis above explains that as long as the fast feedback control saturates the duty cycle to zero in the time period t 0 to t1, the overshoot

Vo _ max is only determined by the load step size, the inductor and the output capacitor, according to

Eq.(22).

Vo _ max

2  1  ( I step  I r )   I stepTon   Co  2s fi 

(22)

Third, for a given design, the step up and step down responses may have different settling patterns. Moreover, the settling pattern of the transient response is dependent on the magnitude of the load current step change. In order to optimize the step up and step down responses to a given load step size, R’Co_up and R’Co_dn are derived respectively and generally they are not equal. Figure 12 shows the R’Co design values derived by the equations in this section verse the load step size. It is interesting that a larger load step up may not necessarily need a larger R’Co_up. The physical reason is, the on-pulses can only provide quantized energy to the output. As the pulse number changes by one, the R’Co value has to be adjusted discontinuously to control the energy transfer process.

Figure 12. The R’Co design values verse the load step size

The design of the Ks may follow the following steps. The target of the design is non-oscillatory response for both load step up and step down at any possible step size, while small signal stability is sufficient. First, from small signal point of view, for simplicity, Q3=2/π is chosen. According to (4), the corresponding R’Co is:

R'C o _ ss  (Tsw  Ton ) /(2Co )

(23)

Second, from large signal point of view, (19) and (21) suggest the optimal R’co_up and R’co_dn repectively. In order to achieve sufficient small signal stability and good large signal response for both load step up and step down, it is suggested to design the R’Co equals to the maximum one among the R’Co in (19), (21) and (23), considering all the possible load step magnitudes. Therefore, the suggested optimal Ks is:

K s  max( R'Co _ ss , R'Co _ up , R'Co _ dn ) / RCo  1 In the normal design with high step down ratio,

(24)

R'Co _ up is larger than R'Co _ dn because the current ramp up slope is

much steeper, and the constant on-time architecture is not able to immediately turn off the top switch when the load steps down. The load step down transient response with an “over designed” R’Co has the settling time constant τ=Rco’Co, which is predicted by the small signal model. V. SIMULATION AND EXPERIMENTAL RESULTS

The modeling results presented in section III are verified by the SIMPLIS simulations. As shown in Figure 13, the proposed model is accurate up to half of the switching frequency. The system parameters are as follows: Vin=12V, Vo=1.2V, fsw=300kHz, Ls=600nH, Co=8∙100μF, RCo=1.4mΩ/8=0.175mΩ.

(a)

(b)

Figure 13. Simulation verifications of vo(s)/vc(s) transfer function and zo(s) transfer function

The Figure 12 in the previous section concluded that the R’co design is dependent on the load step size. Based on the proposed model, the 18A load step requires R’Co= 19mΩ, the 20A load step requires R’Co = 15mΩ.A comparison of the simulation transient responses with four combinations of load step size and R’Co values are shown in the

Figure 14.

It is seen

that R’Co= 19mΩ is the optimal design for 18A load step, but the R’Co= 15mΩ leads to an under-damped response. However, R’Co= 15mΩ is sufficient for 20A load step, while R’Co= 19mΩ design slightly sacrifice the settling time.

(a) 18A step up, R’Co= 19mΩ

(b) 18A step up, R’Co= 15mΩ

(c) 20A step up, R’Co= 19mΩ

(d) 20A step up, R’Co= 15mΩ

Figure 14. Simulation transient response of 18A and 20A load step with different R’Co

Experiment is done on a Buck converter prototype. In the experiment, switching frequency fsw≈250 kHz, Vin=12 V, Vo=1.05 V, Ls=0.47 μH, Co are three 1210 size 100 μF ceramic capacitors with 2mΩ ESR per capacitor. The capacitor current is non-invasively sensed by the passive branch paralleled with the output capacitor. Based on the proposed small signal model, R’Co_ss=12mΩ. According to the time domain analysis, R’Co=17mΩ and R’Co=3.4mΩ are the optimal design for 12A load step up and step down respectively, so R’Co=17mΩ is chosen. For the load step up transient, the time domain model predicts that the number of adjoining on-pulses is Non=2. The predicted valley current Ivu is -1.428A. In the simulation waveform shown in Figure 15, adjoining on-pulses number is 2 and Ivu is -1.51A. The optimal transient response trajectories settle to the new steady state at the second switching action as predicted.

(a) Step up and step down responses

(b) Zoomed in waveform of load step up response

Figure 15. Simulated transient response with optimal design for 12A load step

The experimental optimal transient response is shown in Figure.16. Both load step and step down occur at the worst instants, i.e. the leading edge of a steady on-pulse. The R’Co=17mΩ is optimal for load step up response, but the settling time of the load step down has to be sacrificed.

Figure.16 Experimental transient response with optimal design for 12A load step

Figure 17 chooses R’Co=3.4mΩ, which is optimal for load step down response. Although the settling of step down response is the shortest, this is an under design for load step up response, so the load step up response has a ringing over shoot. With a

smaller current gain, the jittering of Figure 17 is larger than Figure.16. One of the reasons is the smaller signal to noise ratio. The other reason is, the small R’Co results in a high Q second order system as predicted by the proposed small signal model. With disturbance, the under-damped system takes many cycles to settle while the ringing period is two switching cycle, which is mapped from the double pole at half of switching frequency. The proposed design guidelines consider not only large signal response but also small signal model. The proper design following the guidelines would avoid the high Q system and minimize the jittering.

Figure 17. Transient response of a design optimized for load step down

Figure 18 compares the load step down overshoots caused by the load step at different instants. The maximum overshoot is the response to the step at the leading edge of the on-pulse.

Figure 18. The transient responses to the load steps at different instants

Figure 19 compares the load step up and step down responses with different capacitor current sensing gains. The unloading overshoot is determined by the energy stored in the inductor. The optimal R’Co can minimize the settling time. If the current gain is further reduce, an undesirable oscillatory response appears. As predicted, the load step up transient becomes oscillatory first as the R’Co decreases.

(a) R’Co=17mΩ (b) R’Co=3.4mΩ (c) R’Co=2.4mΩ Figure 19. The unloading transient responses with different gain

Figure 20 compares the time domain current sensing waveform and the load transient response. The capacitance mismatch does not obviously change the frequency domain response and time domain waveform. The ESL results in a spike during transient. The current sensing waveform has a positive spike at the beginning of the on-time and off-time, which are the results of the square waveform across the ESL. This square waveform passes through the current sensing high pass filter and exhibits as a spike at the current sensing waveform. As the spike settles far before the decision making point----the end of off-time, the spike does not change the length of off-time. Figure 21 and Figure 22 show the vo(s)/vc(s) and the output impedance with non-ideal current sensings.

(a) ideal sensing (b) ESL=0.2nH (c) sensing capacitor 10% larger Figure 20. The current sensing waveform and transient responses with non-ideal current sensings

(a) ideal sensing

(b) ESL=0.2nH (c) sensing capacitor 10% larger Figure 21. The vo(s)/vc(s) with non-ideal current sensings

(a) ideal sensing

(b) ESL=0.2nH (c) sensing capacitor 10% larger Figure 22. The zo(s) with non-ideal current sensings

VI. SUMMARY V2 control with small RC time constant capacitor has stability issue due to the insufficient capacitor current signal. Compensating the loop by inductor current ramp increases the output impedance while compensating the loop by external ramp cannot always achieve desirable damping. The capacitor current ramp compensation for V2 control provides desirable damping to the loop while maintain ultra fast load transient response. This paper proposes a small signal model based on the describing function method, which indicates that the closed loop system is a second order system. The absolute stability boundary is predicted by the model and the margin is implied by the damping factor. The capacitor current sensing gain controls the damping factor of this second order system. As the small signal model is not able to fully predict the large signal, this paper further studies the load step response and finds out the optimal equivalent ESR values for load step up and step down respectively. Generally, these values are different and dependent on the load step size. Based on the frequency domain and time domain analysis, the design guideline is proposed and verified.

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