1990 two more converter stations were added to the existing two-terminal HVDC system. In 1992 another terminal was added to this MTDC system [7]. For very ...
Modeling and Simulation of 800 kV Multi-terminal UHVDC System in India Wajid Ahmed, Student Member, IEEE, Balachandra M. Hegde, Pavan R. Manvi, Avinash S. S., and Premila Manohar, Senior Member, IEEE M. S. Ramaiah Institute of Technology, Bangalore, India Abstract—The World’s third Multi-terminal and first UHVDC system in India is planned to be commissioned in the year 2016. This system is designed for ± 800 kV, 6000 MW and transmits power over a total distance of 1728 km. A detailed modeling and analysis of the multi-terminal HVDC system is needed to ensure proper satisfactory operation of the system. The present paper deals with the detailed modeling of the upcoming MTDC system. The complete system is developed, modeled in PSCAD/EMTDC environment and transient simulation studies are carried out. The present study is aimed to gain an insight into the system operation and develop expertise needed to design the system parameters for reliable and stable operation. Keywords—HVDC, UHVDC, MTDC, multi-terminal, modeling, simulation, transient analysis, ± 800 kV, bulk power transmission.
I. INTRODUCTION The rising demand for power in urban areas and abundance of power in remote places demands a clean and efficient transmission of power. Over the last few decades the HVDC power transmission is being used and is the only efficient power transmission system for longer distances at higher power levels. There are a number of point to point HVDC links in India and many world-wide. The interconnections of DC systems forming Multi-terminal HVDC (MTDC) systems will improve the system operation and reliability. The potential applications of MTDC systems are bulk energy transfer from cheap energy sources to remote load centers, efficient wheeling of power, interconnection of several AC systems with different frequencies, and improvement in the stability of highly loaded AC systems. The MTDC systems pose serious problems and in order to achieve the efficient operational performance of these systems one has to overcome several specific difficulties. In the early stages, the lack of simple and field proven HVDC circuit breakers was a major hurdle in the development of MTDC systems. Also, these systems require a wellcoordinated and complex control system for their successful operation. Various researchers have been working on different aspects of MTDC system operation [1-5]. The result of which is the first MTDC system in the form of a tap at Corsica on the existing Sardinia Italy HVDC link, in 1991 [6]. The two-terminal HVDC system between Quebec and New Hampshire was built in 1986 which connected the asynchronous power grids of North-East US and Quebec. In 1990 two more converter stations were added to the existing
two-terminal HVDC system. In 1992 another terminal was added to this MTDC system [7]. For very long distances, the transmission losses can be reduced by operating the HVDC link at ultrahigh voltage levels (800 kV). The CIGRE working group in [8] has outlined the technical feasibility of 800 kV HVDC applications. This includes converter configurations, ratings, transformer ratings, ground electrodes, reactive power compensation and requirement, control and protections, line lengths and losses for it to be a successful technology in operation. In UHVDC system insulation levels are very high and the major challenges associated with these systems are the converter configuration, line and converter isolation during faulty conditions, complex controls involved, importance of telecommunication, and line lengths. These are discussed in [9-10]. In India a number of high capacity long distance HVDC systems are in operation and few more systems are planned for execution in near future [11-13]. In order to transmit hydro power available in North Eastern Region of India, the World’s third multi-terminal and first Ultra HVDC system in India is under construction and is planned to be commissioned in the year 2016. The Power Grid Corporation authorities of India along with ABB and BHEL are involved in the design and successful operation of the project. The upcoming four terminal UHVDC system in India is ± 800 kV, 6000 MW transmission capacity and transmits power from North East Region (NER) to the city of Agra, at a total distance of 1728 km. Since no practical/ true working MTDC system exists in the world, a detailed model of the multi-terminal HVDC system is needed to ensure proper system design, understand and asses the behavior of complex controllers involved, commissioning and satisfactory operation of the system. Based on the modeling and simulation studies the parameters of converter configurations, transformer ratings, ground electrodes, reactive power compensation, controls needed and protections, transmission losses, etc., can be explored for various modes of operation. In this context, the present paper deals with the detailed modeling of the upcoming multiterminal UHVDC system. The complete NER-Agra MTDC system is developed and modeled in PSCAD/EMTDC environment. The transient simulation studies are presented. The results of the present study is aimed to help gain an insight into the system operation, possible improvements needed and expertise needed to design the system parameters for its reliable and stable operation.
Fig. 1. Schematic diagram of NER–Agra ± 800 kV, 6000 MW MTDC System
II. MULTI-TERMINAL UHVDC SYSTEM IN INDIA TABLE I
A. NER-Agra MTDC System The upcoming Multi-terminal (four terminal) UHVDC system in India (referred as NER–Agra MTDC) is designed for ± 800 kV, 6000 MW transmission capacity and transmits power from North East Region to the city of Agra at a total distance of 1728 km. Figure 1 shows the single line diagram of complete NER–Agra MTDC System. This system consists of two sending end rectifiers placed one at Alipurduar station (Eastern Region of India in the state of West Bengal), second at Biswanath Chariali station (North Eastern Region of India in the state of Assam), the two parallel connected inverter stations at Agra city. Rectifiers are connected to different AC sources and are separated by 432 km. Each Rectifier is a bipole with one pole positive and another negative. Similarly each Inverter is a bi-pole with one pole positive and another negative. Totally the entire MTDC system has four bi-poles. Each monopole is rated for 1500 MW, 800 kV, 1.875 kA. B. Modeling and representation of MTDC System In the present study, the ac supply network is represented by a Thevenin equivalent circuit consisting of equivalent voltage and impedance. Two three phase two winding transformers are used with each monopole of each rectifier and inverter. One of the transformer uses grounded WyeWye connection and other with grounded Wye-Delta connection. The AC filters for each monopole are provided to remove the harmonics generated by the converters and to supply reactive power to the converter. The filter design considered is same as that of CIGRE benchmark system described in [14-15]. The reactive power compensation is taken as 60% of dc power. Accordingly filter values are calculated.
Detailed System Parameters of MTDC System
Parameters
Rectifier 1
Rectifier 2
Inverter 1
Inverter 2
AC system parameters Source voltage (kV) Frequency (Hz) Bus voltage (kV)
425 50 400
425 50 400
375 50 400
Short Circuit Ratio
4 84 ̊ 13.33
4 84 ̊ 13.33
4 75 ̊ 6.66
3000 1500 3000 ± 800 1.875
3000 1500 3000 ± 800 1.875
Source Zac (Ω) DC system parameters Total Power (MW) Monopole power (MW) power (MW) Bipole Voltage (Bipole) kV) DC Current (kA)
3000 1500 3000 ± 800 1.875
3000 1500 3000 ± 800 1.875
Transformer parameters for each 6 pulse converter of Monopole Transformer MVA 900 Leakage reactance 0.18 (p.u) Primary voltage (kV) 400 Secondary voltage 340 (kV) Control parameters of each Monopole Alpha α (deg.) Gamma γ (deg.)
20.23˚ -
900 0.18 400 340
900 0.18 400 340
900 0.18 400 340
20.37 ˚ -
142.32 ˚ 15.19˚
142.24 ˚ 15.47˚
DC line parameters (R = 0.036 Ω/ km Quad lapwing conductor) DC lines Line length (km) Line resistance (Ω) Smoothing reactor (H)
Line 1 1296 11.66 1.2
Line 2 1296 11.96 1.2
Line 3 432 3.88 1.2
Line 4 432 3.88 1.2
Reactive power compensation for each Monopole (900 MVAR) Type of the Filter Sharing in % Actual Value (MVAR)
C 40 360
High freq. filter 30 270
Low freq. filter 30 270
The dc side of each converter pole consists of smoothing reactor with series dc line resistances. The converter unit of each monopole of rectifier and inverter is represented by 12 pulse configuration which consists of two 6 pulse bridges in series. The transformer is connected to each 6 pulse bridge. The different system parameters for each pole of rectifiers and inverters are calculated and the detailed values of multiterminal UHVDC system are given in Table I. The complete NER Agra MTDC system is developed and modeled using PSCAD/ EMTDC environment.
The current at the voltage controlling station is algebraic difference of current demand and the current margin. If the ceiling dc voltage at one of the stations, operating on constant current drops, then that station would become the voltage controlling station and its current would decrease by the current margin.
C. MTDC Control strategy adopted The control strategy adopted here is the current margin method. This is basically an extension of the control philosophy of two terminal HVDC system [5,9]. One of the converter station controls the voltage while the remaining stations operate in current control mode. Current commands (I1, I2…) having an algebraic summation equal to current margin ∆I, as given in Eqn.(1), are sent from control station to the respective converter stations. …….. (1) Rectifier currents are considered to be positive while inverter currents as negative. The station having lowest ceiling voltage (Vdo Cosα or Cosγn) controls the line voltage. This station is normally, one of the inverters operating at constant extinction angle. The other three converters operate in constant current mode. The control characteristics of the system are shown in Fig. 2.
(a). Vdc at Pole 1 Rectifier 1
(b). Idc at Pole 1 Rectifier 1
800 1
0
0.5
1.5
0
2
0
0.5
1
1.5
0
2
(e). Idc at Pole 1 Inverter 1
800
1
0
0.5
1.02
1
1.5
1 0
2
0
0.5
1
1.5
Gamma
0
2
1
1.5
2
150
Deg.
kA
0.5
(i). Alpha of Pole 4 Rectifier 2
1.875
kV
2
Alpha
90
(h). Idc at Pole 4 Rectifier 2
0
1
-800
90 20
0
0.5
1
1.5
0
2
0
(j). Vdc at Pole 4 Inverter 2
0.5
1
1.5
0
2
(k). Idc at Pole 4 Inverter 2
0
0.5
1
Time (sec.)
1.5
2
Deg.
1 0
1
1.5
2
142
-800 0
0.5
(l). Alpha and Gamma of Pole 4 Inverter 2
1.875
-400
kA
kV
1.5
15
(g). Vdc at Pole 4 Rectifier 2 -400
1
(f). Alpha and Gamma of Pole 1 Inverter 1 Deg.
kA
800
0.5
142
1.875
400
90 20
1.02
1
1
(d). Vdc at Pole 1 Inverter 1
kV
(c). Alpha of Pole 1 Rectifier 1 150
Deg.
kA
kV
400
0
Satisfactory operation of MTDC system also requires a reliable central Current Reference Balancer (CRB) that operates at all time. This requires two way communication between a central station and each converter station. Under steady state condition, rectifiers R1, R2 and inverter I2 operate in constant current control and inverter I1 operates in voltage control mode. VDCOL is included in all the converter stations. A current margin of 10% is included for inverter1 which is acting as voltage controller. Further the transformer tap changers are employed on each rectifier pole to keep the firing angle within limits and on inverter transformers they are used to maintain the rectifier dc voltage (to control extinction angle).
1.875
800
0
Fig. 2 Current Margin Method of control for MTDC system
Alpha 90 Gamma 15
0
0.5
1
1.5
2
0
0.5
Time (sec.)
Fig. 3. Steady state results for voltages, currents, and control parameters of different poles of MTDC System
1
Time (sec.)
1.5
2
From the results it is observed here that there were some initial transients that subsided within about 0.75 sec. The system reached its steady state values of ± 800 kV, 1.875kA and control parameters also reached their steady state values.
III. DYNAMIC ANALYSIS OF MTDC SYSTEM The aim of present study is to investigate the steady state and transient behavior of the upcoming MTDC system in India. Initially the steady state and transient behavior of each monopole of each rectifier and inverter are simulated and compared with the HVDC CIGRE benchmark system to make sure that the converters and controllers are behaving properly and the values are within limits.
B. Single line to ground fault on inveter ac bus In order to study the unbalanced condition in MTDC system, a single phase to ground fault is created at the inverter AC bus at t = 1.2 sec with fault duration of 0.06 sec. The system is simulated for a duration of 2 sec. As both the inverters are connected to a single AC bus, the effect of fault is same on both the inverters (I1 and I2). The various voltages, currents, and control parameters are indicated in Fig. 4. During the fault period the dc voltages polarities have been reversed and the dc currents reaches peak values (about 5 kA from 1.875 kA). During this period, α of each pole of Rectifier and γ of each pole of Inverter reaches the maximum values, and α of each pole of Inverter reaches the minimum value, there by blocking the system for the fault period. After the fault duration the recovery is smooth without any hitches.
Initially the MTDC system is studied for different parameters like short circuit ratio (2.5 and 4), smoothing reactor (0.3 H to 0.6 H on each pole side), ac filters (different types and 50 to 60 % compensation), control parameters (with and without VDCOL and interchanging current and voltage control on different pole), etc., to understand the behavior of the system. Based on this the appropriate parameters are chosen. The details are listed in Table I. For the parameters given in Table I, the transient simulation results using PSCAD/EMTDC package are presented here. In all the cases simulated here, the time step chosen for the simulations is ∆t = 50 µs. The various dynamic ac/ dc fault conditions are created at 1.2 sec for a fault duration of 3 cycles (0.06 sec). Due to space constraint only results of the 4 poles out of 8 poles of MTDC system are shown. The results on the other poles are similar to the results presented here.
C. Three phase to ground fault on inveter ac bus The three phase to ground fault results are depicted in Fig. 5. Here, the voltages and currents are much disturbed and also the current peak (about 6 kA) is much higher than that for single phase fault. During the fault period the commutation failure occur, resulting in temporary drop down of dc voltage. This causes VDCOL to limit the dc current to minimum. The behavior of control parameters is also indicated in the results. After fault duration the system reaches steady state values.
A. Steady state operation The complete NER Agra MTDC system modeled using PSCAD/EMTDC environment. Figure 3 shows the steady state simulation results of the MTDC system. The system is simulated for duration of 2 sec.
(a). Vdc at Pole 1 Rectifier 1
(b). Idc at Pole 1 Rectifier 1
1
1.2
1.4
1.6
1.8
3 1.875 0
2
D eg.
0 -800
1.6
1.8
2
1
0
1.2
1.4
1.6
1.8
1.2
1.4
1.6
1.8
1
(h). Idc at Pole 4 Rectifier 2
1
1.2
1.4
1.6
1.8
1.2
1.4
1.6
1.8
1
(k). Idc at Pole 4 Inverter 2
1
1.2
1.4
1.6
Time (sec.)
1.8
2
2
1.2
1.4
1.6
1.8
2
(l). Alpha and Gamma of Pole 4 Inverter 2
1.875 0
1.8
142
D eg.
kA
-800
1.6
90
2
5
0
1.4
20 1
(j). Vdc at Pole 4 Inverter 2 800
1.2
(i). Alpha of Pole 4 Rectifier 2
3 1.875 0
2
2
150
Deg.
kA
800
1.8
90 60
2
5
0
1.6
15 1
(g). Vdc at Pole 4 Rectifier 2 800
1.4
(f). Alpha and Gamma of Pole 1 Inverter 1
1.875 0
2
1.2
142
D eg.
kA
kV
1.4
(e). Idc at Pole 1 Inverter 1
-800
kV
1.2
5
1
90 20
1
(d). Vdc at Pole 1 Inverter 1 800
kV
(c). Alpha of Pole 1 Rectifier 1 150
5
kA
kV
800
90 60 15
1
1.2
1.4
1.6
Time (sec.)
1.8
2
1
1.2
1.4
1.6
Time (sec.)
Fig. 4. Single line to ground fault at inverter ac bus results for voltages, currents, and control parameters of different poles of MTDC System
1.8
2
(a). Vdc at Pole 1 Rectifier 1
(b). Idc at Pole 1 Rectifier 1 3 1.875
-800 1
1.2
1.4
1.6
1.8
150
D eg.
kA
kV
0
0
2
1.2
1.8
2
1
1.2
1.4
1.6
1.8
0
2
1.2
1.4
1.6
1.8
1
1.2
1.4
1.6
1.8
0
1.2
1.4
1.6
1.8
1
(k). Idc at Pole 4 Inverter 2
1.2
1.4
1.6
1.8
0
2
1.2
1.4
1.6
1.8
2
(l). Alpha and Gamma of Pole 4 Inverter 2 Deg.
kA 1
2
142
1.875
-800
1.8
90
2
6
0
1.6
20 1
(j). Vdc at Pole 4 Inverter 2 800
1.4
(i). Alpha of Pole 4 Rectifier 2
3 1.875
2
2
150
Deg.
kA 1
1.2
(h). Idc at Pole 4 Rectifier 2
-800
1.8
90 60
2
6
0
1.6
15 1
(g). Vdc at Pole 4 Rectifier 2 800
1.4
(f). Alpha and Gamma of Pole 1 Inverter 1
1.875
-800
1.2
142
D eg.
kA
kV
1.6
(e). Idc at Pole 1 Inverter 1
0
kV
1.4
6
1
90 20
1
(d). Vdc at Pole 1 Inverter 1 800
kV
(c). Alpha of Pole 1 Rectifier 1
6
800
1
1.2
Time (sec.)
1.4
1.6
1.8
2
90 60 20 1
1.2
Time (sec.)
1.4
1.6
1.8
2
Time (sec.)
Fig. 5. Three phase to ground fault at inverter ac bus results for voltages, currents, and control parameters of different poles of MTDC System
(a). Vdc at Pole 1 Rectifier 1
(b). Idc at positive pole Rectifier bus
1
1.2
1.4
1.6
1.8
3.75 0
2
150
D eg.
kA
kV
0 -800
1.6
1.8
2
1
0
1.2
1.4
1.6
1.8
1.2
1.4
1.6
1.8
1
(h). Idc at negative pole Rectifier bus
1.2
1.4
1.6
1.8
1
(j). Vdc at Pole 4 Inverter 2
1.2
1.4
1.6
1.8
1
(k). Idc at negative pole of Inverter bus
1
1.2
1.4
1.6
Time (sec.)
1.8
2
1.8
2
1.2
1.4
1.6
1.8
2
(l). Alpha and Gamma of Pole 4 Inverter 2
3.75 0
1.6
142
D eg.
kA
0 -400 -800
1.4
60 20
2
11
800
1.2
(i). Alpha of Pole 4 Rectifier 2
3.75 0
2
2
150
D eg.
kA 1
1.8
90
2
11
0 -400 -800
1.6
15 1
(g). Vdc at Pole 4 Rectifier 2 800
1.4
(f). Alpha and Gamma of Pole 1 Inverter 1
6 3.75 0
2
1.2
142
D eg.
kA
kV
1.4
(e). Idc at positive pole Inverter bus
-800
kV
1.2
11
1
90 20
1
(d). Vdc at Pole 1 Inverter 1 800
kV
(c). Alpha of Pole 1 Rectifier 1
11 8
800
90 15
1
1.2
1.4
1.6
Time (sec.)
1.8
2
1
1.2
1.4
1.6
1.8
Time (sec.)
Fig. 6. DC line to ground at positive pole of inverter dc bus results for voltages, currents, and control parameters of different poles of MTDC System
2
D. DC line to ground fault at positive pole of inverter dc bus The dc line to ground fault at positive pole of inverter dc bus is applied at 1.2 sec for duration of 0.06 seconds. The results are shown in Fig. 6. Immediately after the fault, the current rises sharply and reaches a maximum value (about 11 kA). The dc voltage of affected poles has gone down to zero. The controllers force α of each pole of Rectifier and γ of each pole of Inverter to reach their maximum values, and α of each pole of Inverter reaches the minimum value. This results in reduction of the dc current. VDCOL also limits the dc current to minimum value until the dc voltage is improved. IV. CONCLUSIONS In the present paper the complete upcoming NER Agra Multi-terminal UHVDC system in India is developed, modeled and simulated in PSCAD/EMTDC environment. The study carried out here has investigated and presented the detailed steady state and transient behavior of the MTDC system. The controllers used are the extension of the two terminal systems. The results presented in this study are aimed to help gain an insight into the system operation, data, possible improvements needed, understand and asses the complex controllers involved and expertise needed to design the system parameters for its continuous, reliable and stable operation.
REFERENCES [1]
[2]
[3]
[4] [5]
[6]
[7]
[8]
[9]
[10]
V. DISCUSSIONS AND FUTURE WORK The results of dc line fault conditions are shown in Fig. 6. During faulty situation, the aim is to quickly minimize the peak values of dc currents within the rated values and this demands the operation of MTDC system with HVDC circuit breakers. Without any protective devices for a long duration or sustained/ permanent fault the whole MTDC system has to be shut down and restarted once the fault is rectified.
[11]
Employing fast acting HVDC circuit breakers can quickly extinguish the dc fault current and isolate the HVDC link. The fast acting commercial HVDC circuit breakers are still in prototype status[16-18]. There is a strong need to design HVDC protection schemes with available technologies and in this direction various researchers are suggesting the different possible solutions to overcome dc line fault conditions, methods for realizing HVDC circuit breakers, and different ways of clearing and isolating dc line faults. One of the solution in this direction is the application of superconducting fault current limiter (SCFCL) [19-20]. The SCFCL can be technically and economically viable alternative, for the problems encountered in MTDC system operation. In a future work by the present authors the application of SCFCL in upcoming NER Agra MTDC system will be studied.
[15]
[12] [13] [14]
[16]
[17]
[18]
[19]
[20]
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