Modeling of Failure Probability and Statistical Design of Spin-Torque

16.2

Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) Array for Yield Enhancement Jing Li, Charles Augustine, Sayeef Salahuddin, and Kaushik Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA

{jingli, caugust, ssalahud, kaushik}@purdue.edu combines all desirable memory attributes e.g., nonvolatility, unlimited endurance, low power, high speed and high memory density. Therefore, STT MRAM has gained lots of attention in today’s memory community. Fig. 1 shows the structure of a typical STT MRAM bit-cell. It consists of a transistor, a spintronic device (Magnetic Tunneling Junction), word line (WL), bit line (BL) and source line (SL). The basic building block of MRAM cell is the magnetic tunneling junction (MTJ) (Fig.2). Each MTJ consists of two ferromagnetic layers separated by a very thin tunneling dielectric film. Magnetization in one of the layers (referred as pinned layer) is fixed in one direction by coupling to an antiferromagnetic layer. The other ferromagnetic layer (referred as free layer) is used for information storage. By controlling the direction of magnetization of free layer with respect to the pinned layer (i.e., anti-parallel or parallel), MTJ can be configured to high-resistance state (RAP or RH, “1”state) or low-resistance state (RP or RL, “0”state) (Fig. 3). For example, when writing a “0” to a cell storing “1”, the bit line is pre-charged to VDD and source line is grounded. After turning on the NMOS transistor, current flows from bit line to source line. If the current is larger than the switching threshold current (IHL) of MTJ, magnetization of free layer is switched from anti-parallel to parallel by the spin polarized current. The voltage polarities applied to bit line and source line are switched while writing a “1” to a cell storing “0”. One of the quality metrics for an MTJ device is Tunneling Magneto-Resistance (referred as TMR) ratio [2]. TMR of MTJ (defined as (RH-RL)/ RL) has strong voltage dependence and it reduces with increase in bias voltage. MTJ with high TMR ratio is desirable due to significantly improved state change. In read operation, cell effective resistance can be measured by applying a small bias voltage and sensing the current. If TMR is high, the two states can be easily distinguished due to larger state change (∆R=RH-RL). Comparison with reference current value determines whether the state is high or low. During write operation, MRAM cell is written to one of the states (high or low) and cell can retain state without any external supply power. Two major issues associated with conventional MRAM are (a)

Abstract: Spin-Torque Transfer Magnetic RAM (STT MRAM) is a promising candidate for future universal memory. It combines the desirable attributes of current memory technologies such as SRAM, DRAM and flash memories. It also solves the key drawbacks of conventional MRAM technology: poor scalability and high write current. In this paper, we analyzed and modeled the failure probabilities of STT MRAM cells due to parameter variations. Based on the model, we developed an efficient simulation tool to capture the coupled electro/magnetic dynamics of spintronic device, leading to effective prediction for memory yield. We also developed a statistical optimization methodology to minimize the memory failure probability. The proposed methodology can be used at an early stage of the design cycle to enhance memory yield.

Categories and Subject Descriptors: B.3.3 [Memory Structures]: Performance Analysis and Design Aids – statistical design

General Terms.: Algorithms, Design, Performance Keywords: STT MRAM, Yield 1. Introduction The demand for on-chip embedded memories has grown significantly over the last few decades. On-chip memories can be accessed fast (contrary to large miss penalty associated with offchip memories) and hence, increases the bandwidth of high performance processors. Several memory technologies have been explored by researchers in the past. Static-RAM (SRAM) provides excellent read and write properties but the cell size is relatively large (6-T structure) and limits the amount of memory that can be integrated within the die. On-chip DRAMs have been explored as a possible alternative to SRAMs due to its small cell size (1-T or 3-T structures). However, leakage of information is severe in such memories and periodic refresh rates make them undesirable for portable electronics with limited battery life. In contrast to SRAMs and DRAMs, flash memories do not require external power to store data due to its nonvolatile nature. However, high-voltage, slow-write operations with limited read/write endurance overshadow its inherent advantages such as high integration density and simple architecture. Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) is orthogonal to all previous memory technologies [1]. It

Bit line

Sense Amp.

Iref

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MTJ

Free layer

Band structure

τ

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Free Layer

Tunneling Oxide

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(a)

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Read Bias generator (V)

Fixed Oxide Free layer barrier layer

Source line

Fig. 1 An STT MRAM cell includes 1) Spintronic device: MTJ; 2) bit line; 3) source line; 4) word line; 5) NMOS and 6) read drive circuitry

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“1” state

Fig. 2 MTJ structure in (a) anti-parallel (RH state) and (b) parallel (RL state) configurations

1.5

1

0.5 -1

RP

-0.5 0 0.5 Applied voltage (V)

I>ILH 1

Fig. 3 Resistance vs. voltage response of MTJ with τ= 1nm and A= 100 × 150 nm2. (All values are normalized to RL with bias voltage of vMTJ=0)

R

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Fig. 4 MTJ resistance (R) vs. τ in parallel and anti-parallel configurations under different VMTJ (normalized to RL with τ=1.0nm; vMTJ=0.1V).

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Fig. 5 MTJ resistance (R) vs. A in parallel and anti-parallel configurations under different VMTJ (normalized to RL with τ=1.0nm; vMTJ=0.1V).

high write current and (b) poor scalability [1][2]. Conventional MRAM uses external current induced magnetic field to switch the magnetization direction of free layer from one direction to the other during write operation [2]. As MRAM scales, the magnetic field strength required for switching magnetization increases, resulting in significantly increased write current and high power dissipation. In contrast to conventional MRAM, STT MRAM uses the direct injection of spin polarized current by spintronic device (MTJ) itself to switch the magnetization of the free layer and hence requires much less write current. More importantly, in STT MRAM, switching threshold current (IHL or ILH) reduces with MTJ scaling, making it low power and highly scalable. However, with scaling, STT MRAM is facing a set of new challenges. Since the resistance-area product (RA) of MTJ device is invariant with scaling in order to maintain or increase the readout speed, it is essential to keep MTJ resistance under control. This is done to maintain reasonable RC delays. There are two possible ways to reduce the area while maintaining low MTJ resistance: (1) reduce the dielectric barrier height (Eb) (2) reduce the barrier thickness (τ) (Fig.1). Reduction in barrier height can be achieved by using different barrier material in MTJ which could be a challenging task when pushing MRAM design from generation-to-generation [2]. The alternate solution is to reduce τ by controlling the oxidation time of dielectric material in the MTJ [2][3]. Although the overall performance can be improved by scaling, statistical parametric variation is a serious concern which may potentially cause failure of the cell during read or write operations. The major sources of process variations in MTJ include (a) variations in tunneling oxide thickness (τ) and, (b) variations in cross-sectional area (A) [3]. These parameters affect the static as well as the dynamic behavior of MTJ, resulting in possible failure of the cell ─ read failure (flipping of the cell data while read/incorrect read); and inability to write to the cell. The problem is further aggravated in scaled technology due to the reduced switching threshold current and lithography challenges. Hence, accurate analysis of parametric failures in STT MRAM cell is necessary to estimate memory yield and to optimize STT MRAMs for higher yield. The failure mechanism in embedded memories (e.g. SRAMs) have been well studied and successfully modeled by researchers [4] to reduce the memory failure probability and to improve the yield. However, no attempts have been made to analyze STT MRAM failure mechanisms. Over-designing of memory can improve the yield, but it results in wastage of silicon area and power. To hasten successful STT MRAM commercialization, it is imperative to develop a methodology to guide the designer for optimal design of STT MRAM cell, drive circuitry (i.e., the bias voltage and reference current, read/write operation frequency, etc)

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Fig. 6 Frequency dependency of switching threshold current density (JHL and JLH) of MTJ [5].

and memory organization (i.e., number of columns, rows and redundant columns) in order to minimize memory failures. In this paper, we propose a statistical design methodology to minimize the parametric failures in STT MRAM under process variation. The proposed methodology provides insight in designing read/write circuitry considering parametric variation of the MTJ (τ, A) and its bias dependence. In particular, we have: 1) Analyzed the impact of the parametric variations on failure probabilities of STT MRAMs; 2) Presented theoretical analysis for modeling the read and write failures of a cell due to the parametric variations; 3) Developed a tool to estimate failure probability of memory (considering the memory architecture and redundant columns) and to predict the yield; 4) Proposed a statistical-design strategy to reduce the memoryfailure probability and to improve the yield of STT MRAMs. The rest of the paper is organized as follows. Section 2 describes the read/write failure mechanisms in an STT MRAM cell. The analytical modeling of the different failure probabilities in an STT MRAM cell is explained in Section 3. In Section 4, we have presented analytical estimation of the memory yield and our statistical simulation results. We also propose a statistical design methodology to improve the yield. Finally, we conclude the paper in section 5.

2. Preliminaries: Sources of variations in MTJ The sources of variations in process parameters of MTJ include variations in (a) tunneling oxide thickness (τ) and (b) crosssectional area (A). These parameters not only affect the static but also the dynamic behavior of MTJ. The first successful fabricated STT MRAM has been reported by Hosomi et al. [5] using 0.18 µm CMOS technology. The tunneling oxide thickness of MTJ is of the order of 1.5nm. To further increase the memory density for new generation STT MRAMs, MTJ has to be scaled (both τ and A) in accordance with the CMOS technology scaling to achieve maximum benefit. However, fabricating ultra thin dielectric thickness ( I HL ( t R , A )

where I HL ( tR , A) is the switching threshold current of MTJ from

Fig. 9 Statistical design procedure of STT MRAM MTJ geometry is carefully scaled from the parameters given in [5] using 180nm CMOS technology. For circuit simulation, in the following sections, we use the above device models for the nominal (i.e. mean τ and mean A) case. The spread of the variation (σ/µ) is assumed to be 2% and 5% in τ and A, respectively (τ and A are assumed to follow Gaussian distribution).

“1” state to “0” state at a particular read operation frequency (fR=1/tR). Similarly, read failure probability for anti-parallel direction reading can be written in similar way.

3.2.2 Simulation and discussion 3.2.2.1 Simulation Setup To accurately capture the static and dynamic behavior of MTJ and the combined magnetic/circuit response in the presence of NMOS transistor, we developed an efficient simulation tool using Response Surface Method (RSM). RSM uses a statistically designed N-dimensional matrix to estimate the response of a function of N independent input vectors [7]. The basic structure of the tool is illustrated in Fig. 9. Two RSM functions are constructed for MTJ and NMOS, respectively. For simulation of MTJ, we use the Spin-Torque Transfer model proposed in [6]. The IV characteristics of MTJ are calibrated with experiments shown in [5]. The I-V characteristics of NMOS are extracted for 130nm technology node using BPTM [8]. Based on the two RSM functions, the static and dynamic behavior of the entire memory cell is obtained by numerically solving the circuit response of MTJ and NMOS self-consistently. Using this simulation tool, we design STT MRAM in 130nm CMOS technology. The MTJ device has cross-sectional area (A) of 100 × 150 (nm2) and tunneling oxide (τ) of 10 Å. Note that this

3.2.2.2 Result and discussion Based on the simulation setup, we perform Monte-Carlo circuit simulations (~100,000) to estimate current distribution of a memory cell for read bias voltage varying from 0V to 0.5V. Read margin: The distance between the reading point and the trip point (switching threshold) of parallel state (Fig. 7b) shows the amount of immunity to disturbance. It is seen that the read margin for “parallel direction reading” is larger than “anti-parallel direction reading” (Fig.7b, 8). To better illustrate this effect, we plot the measured current distribution of an STT MRAM cell (Fig. 10), using parallel direction reading and anti-parallel direction reading, respectively. It is observed that at the same bias voltage (say, 0.3V) the current distribution of state “1” and state “0” overlaps with each other in anti-parallel direction reading, resulting in significantly increased failure probability compared to parallel direction reading.

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Degraded current drivability in AP reading

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Frequency:400MHz Frequency:60MHz

Insensitive to NMOS size and Frequency

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Fig. 10 Distribution of sensed Fig. 11 Variation of read passing success probability (1-PRF) current (vR=0.3V) through a memory cell in parallel with NMOS size at different and anti-parallel direction frequencies reading NMOS sizing: We note that the required switching current is of the order of hundreds µA for MTJ, which cannot be provided by a minimum sized transistor. Thus, the memory cell size is dominated by the area of the NMOS. Hence, to increase the memory density, the size of NMOS should be reduced. Reducing NMOS size degrades its current drivability, thereby reducing read disturbance. Consequently, reducing NMOS size will reduce read failure probability (Fig. 11). However, since the bias voltage for read operation is typically low, read failure due to read disturbance is small. It is seen from Fig.11 that the read failure probability is not sensitive to the NMOS transistor size (for given NMOS size range 1µm), the write failure probability that column is given by is low and does not vary with the sizing of NMOS transistor. NR (13) P {at least 1 cell fail} = 1 − (1 − PF ) However, as NMOS size is reduced (