MSc THESIS - CiteSeerX

Computer Engineering

2010

Mekelweg 4, 2628 CD Delft The Netherlands http://ce.et.tudelft.nl/

MSc THESIS Design and Simulation of Single Electron Tunneling Circuits for Brownian Motion Based Logic and Arithmetic Computation Innocent Okwudili Agbo Abstract In this thesis, the implementations of Single Electron Tunneling (SET) circuits for Brownian Motion Based Logic and Arithmetic Computation were investigated. Random fluctuations and noise are major factors interfering with the operation of nanometer scale electronic devices and circuits, as the feature size decreases. In SET technology, one of these interfering effects, namely quantum tunneling, is actually utilized for computations by controlling the transport of individual electrons. However, at the single electron level, random fluctuations are largely unavoidable. In previous research, Brownian Motion based building blocks were proposed which take advantage of random fluctuations to function.i.e, Conservative Join (CJoin)and Hub. However, the SET design of the CJoin had two major limitations when taking industrial implementation into account. Firstly, it had long diagonal wires that appear on the design literally. Secondly, the circuit parameters of the tunnel junction capacitances fell short of the industrial standard. In this research we present a new design for the CJoin,i.e, the Redesigned CJoin. In the Redesigned CJoin the CE-MS-2010-02 long diagonal wires that cause routing problem are eliminated and additionally the circuit parameters are industrially realizable, while meeting the same functionality. Secondly, we construct networks of the Redesigned CJoin design and the Hub and show that the two blocks can be used to build computational units. We investigate networks of two Hubs and one redesign CJoin, three Hubs and two redesign CJoin and network of four Hubs and four redesign CJoin. Third, we propose logic and arithmetic computation with 2-by-2 CJoin Brownian circuit Network. We investigate the logic and arithmetic computation with 2-by-2 CJoin based NAND-gate, NOR-gate and Half-Adder. Finally, we utilized a buffering scheme from previous research to improve the functionality robustness of the Half-Adder. We also investigate static buffer with circuit parameters at 1K. We investigate a static Buffered 2-by-2 CJoin based Half-Adder. All designs in this thesis are verified through simulations. This thesis establishes a concrete design platform for complex Brownian motion Based logic and arithmetic computation.

Faculty of Electrical Engineering, Mathematics and Computer Science

Design and Simulation of Single Electron Tunneling Circuits for Brownian Motion Based Logic and Arithmetic Computation THESIS

submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in

COMPUTER ENGINEERING by

Innocent Okwudili Agbo born in Amechi-Awkunanaw, Nigeria

Computer Engineering Department of Electrical Engineering Faculty of Electrical Engineering, Mathematics and Computer Science Delft University of Technology

Design and Simulation of Single Electron Tunneling Circuits for Brownian Motion Based Logic and Arithmetic Computation

by Innocent Okwudili Agbo Abstract n this thesis, the implementations of Single Electron Tunneling (SET) circuits for Brownian Motion Based Logic and Arithmetic Computation were investigated. Random fluctuations and noise are major factors interfering with the operation of nanometer scale electronic devices and circuits, as the feature size decreases. In SET technology, one of these interfering effects, namely quantum tunneling, is actually utilized for computations by controlling the transport of individual electrons. However, at the single electron level, random fluctuations are largely unavoidable. In previous research, Brownian Motion based building blocks were proposed which take advantage of random fluctuations to function.i.e, Conservative Join (CJoin)and Hub. However, the SET design of the CJoin had two major limitations when taking industrial implementation into account. Firstly, it had long diagonal wires that appear on the design literally. Secondly, the circuit parameters of the tunnel junction capacitances fell short of the industrial standard. In this research we present a new design for the CJoin,i.e, the Redesigned CJoin. In the Redesigned CJoin the long diagonal wires that cause routing problem are eliminated and additionally the circuit parameters are industrially realizable, while meeting the same functionality. Secondly, we construct networks of the Redesigned CJoin design and the Hub and show that the two blocks can be used to build computational units. We investigate networks of two Hubs and one redesign CJoin, three Hubs and two redesign CJoin and network of four Hubs and four redesign CJoin. Third, we propose logic and arithmetic computation with 2-by-2 CJoin Brownian circuit Network. We investigate the logic and arithmetic computation with 2-by-2 CJoin based NANDgate, NOR-gate and Half-Adder. Finally, we utilized a buffering scheme from previous research to improve the functionality robustness of the Half-Adder. We also investigate static buffer with circuit parameters at 1K. We investigate a static Buffered 2-by-2 CJoin based Half-Adder. All designs in this thesis are verified through simulations. This thesis establishes a concrete design platform for complex Brownian motion Based logic and arithmetic computation.

I

Laboratory Codenumber

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Committee Members

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Computer Engineering CE-MS-2010-02

Advisor:

Sorin Cot¸ofan˘a, CE TU Delft

Chairperson:

Koen Bertels, CE, TU Delft

Member:

Jaap Hoekstra, ELCA, TU Delft

Member:

Arjan van Genderen, CE, TU Delft

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Contents

List of Figures

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List of Tables

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Acknowledgements

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1 Introduction 1.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Objectives and Contributions . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SET Background 2.1 SET Concepts . . . . . . . . . . . . 2.2 Related Work . . . . . . . . . . . . 2.2.1 SET Electron Box . . . . . 2.2.2 SET Transistor . . . . . . . 2.2.3 SET Buffer . . . . . . . . . 2.3 Brownian Motion Circuit Concepts 2.4 Dual Rail Coding logic . . . . . . . 2.5 Conclusion . . . . . . . . . . . . .

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3 SET Based Brownian Circuit Building Blocks 3.1 Hub Circuit . . . . . . . . . . . . . . . . . . . . 3.2 Original Conservative Join Circuit . . . . . . . 3.3 Implementable Building Block for CJOIN . . . 3.3.1 The Redesigned CJOIN Circuit . . . . . 3.3.2 Discussion . . . . . . . . . . . . . . . . . 3.4 Conclusion . . . . . . . . . . . . . . . . . . . .

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4 Networks of SET Based Brownian Circuit Building Blocks 4.1 One Redesigned CJoin and Two Hubs . . . . . . . . . . . . . 4.2 Two Redesigned CJoin and Three Hubs . . . . . . . . . . . . 4.3 Two-By-Two CJoin . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Two-By-Two CJoin Based NAND gate . . . . . . . . . . . . . 4.5 Two-By-Two CJoin Based NOR gate . . . . . . . . . . . . . . 4.6 Two-By-Two CJoin Based HALF-ADDER . . . . . . . . . . . 4.7 Static Buffered HALF ADDER Based Computation . . . . . 4.8 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

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5 Conclusion and Discussion 77 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2 Future Research work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Bibliography

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List of Publications

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List of Figures 2.1 2.2 2.3 2.4 2.5 2.6 2.7

Quantum tunnel junction circuit symbol . . . . . . . Equivalent circuit for determining the critical voltage The Electron Box circuit . . . . . . . . . . . . . . . . The SET transistor circuit . . . . . . . . . . . . . . . Static Inverting buffer . . . . . . . . . . . . . . . . . Static Inverting buffer simulation results . . . . . . . Dual-rail Data transfer . . . . . . . . . . . . . . . . .

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3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

Hub Module . . . . . . . . . . . . . . . . . . . . . . . . . Hub Circuit . . . . . . . . . . . . . . . . . . . . . . . . . Hub simulation result . . . . . . . . . . . . . . . . . . . Symbol of Conservative Join . . . . . . . . . . . . . . . . Original Conservative Join Circuit . . . . . . . . . . . . Original conservative Join simulation result . . . . . . . ReDesigned Conservative Join Circuit . . . . . . . . . . ReDesigned Conservative Join circuit simulation results

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4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25

Network of Two Hubs and One ReDesigned CJoin . . . . . . . Network of 2 Hubs and 1 Redesigned CJoin simulation result . Network of 2 Hubs and 1 Redesigned CJoin . . . . . . . . . . . Network of Three Hubs and Two ReDesigned CJoin . . . . . . Network of 3 Hubs and 2 Redesigned CJoin simulation results . Network of 3 Hubs and 2 Redesigned CJoin simulation results . Network of 3 Hubs and 2 Redesigned CJoin simulation results . Network of 3 Hubs and 2 Redesigned CJoin simulation results . Two-By-Two CJoin Circuit Design . . . . . . . . . . . . . . . . Network of 2-by-2 Redesigned CJoin first simulation results . . Network of 2-by-2 Redesigned CJoin second simulation results . Network of 2-by-2 Redesigned CJoin third simulation results . Network of 2-by-2 Redesigned CJoin fourth simulation results . NAND gate Based Two-By-Two CJoin . . . . . . . . . . . . . . First Input of NAND gate . . . . . . . . . . . . . . . . . . . . . First Output of NAND gate . . . . . . . . . . . . . . . . . . . . Second Input of NAND gate . . . . . . . . . . . . . . . . . . . . Second Output of NAND gate . . . . . . . . . . . . . . . . . . . Third Input of NAND gate . . . . . . . . . . . . . . . . . . . . Third Output of NAND gate . . . . . . . . . . . . . . . . . . . Fourth Input of NAND gate . . . . . . . . . . . . . . . . . . . . Fourth Output of NAND gate . . . . . . . . . . . . . . . . . . . Two-By-Two CJoin Based NOR gate . . . . . . . . . . . . . . . First Input of NOR gate . . . . . . . . . . . . . . . . . . . . . . First Output of NOR gate . . . . . . . . . . . . . . . . . . . . .

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4.26 4.27 4.28 4.29 4.30 4.31 4.32 4.33 4.34 4.35 4.36 4.37 4.38 4.39 4.40 4.41 4.42 4.43 4.44 4.45 4.46 4.47 4.48 4.49 4.50 4.51 4.52 4.53

Second Input of NOR gate . . . . . . . . . . . . . . . . Second Output of NOR gate . . . . . . . . . . . . . . . Third Input of NOR gate . . . . . . . . . . . . . . . . Third Output of NOR gate . . . . . . . . . . . . . . . Fourth Input of NOR gate . . . . . . . . . . . . . . . . Fourth Output of NOR gate . . . . . . . . . . . . . . . Two-By-Two CJoin Based Half Adder . . . . . . . . . First Input of the HalfAdder . . . . . . . . . . . . . . First Output of the HalfAdder . . . . . . . . . . . . . Second Input of the HalfAdder . . . . . . . . . . . . . Second Output of the HalfAdder . . . . . . . . . . . . Third Input of the HalfAdder . . . . . . . . . . . . . . Third Output of the HalfAdder . . . . . . . . . . . . . Fourth Input of the HalfAdder . . . . . . . . . . . . . Fourth Output of the HalfAdder . . . . . . . . . . . . Static Buffered Half Adder . . . . . . . . . . . . . . . First Input of Static Buffered HalfAdder . . . . . . . . First Output of Static Buffered HalfAdder . . . . . . . First Output of Static Buffered HalfAdder continues . Second Input of Static Buffered HalfAdder . . . . . . . Second Output of Static Buffered HalfAdder . . . . . . Second Output of Static Buffered HalfAdder continues Third Input of Static Buffered HalfAdder . . . . . . . Third Output of Static Buffered HalfAdder . . . . . . Third Output of Static Buffered HalfAdder continues . Fourth Input of Static Buffered HalfAdder . . . . . . . Fourth Output of Static Buffered HalfAdder . . . . . . Fourth Output of Static Buffered HalfAdder continues

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List of Tables 2.1 2.2 2.3

Static Buffered Circuit parameters . . . . . . . . . . . . . . . . . . . . . . 16 Four (4) Phase handshaking Dual-rail Encoding . . . . . . . . . . . . . . . 19 Two (2) Phase handshaking Dual-rail Encoding . . . . . . . . . . . . . . . 20

3.1 3.2 3.3

Hub circuit parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Original CJoin circuit parameters . . . . . . . . . . . . . . . . . . . . . . . 27 Redesigned CJoin circuit parameters . . . . . . . . . . . . . . . . . . . . . 31

4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21

Adjusted Hub circuit parameters . . . . . . . . . . . . . . . . . . . . . . . Adjusted Hub circuit parameters for 2 RedesCJoin and 3 Hubs . . . . . . Adjusted Hub circuit parameters on the row of RedesCJoin . . . . . . . . Adjusted Hub circuit parameters on the column of RedesCJoin . . . . . . NAND gate Based 2-by-2 CJoin truth table . . . . . . . . . . . . . . . . . First adjusted Hub circuit parameters for NAND gate Based 2-by-2 CJoin Second adjusted Hub circuit parameters for NAND gate Based 2-by-2 CJoin NOR gate Based 2-by-2 CJoin truth table . . . . . . . . . . . . . . . . . . First adjusted Hub circuit parameters for NOR gate Based 2-by-2 CJoin . Second adjusted Hub circuit parameters for NOR gate Based 2-by-2 CJoin Half-Adder Based 2-by-2 CJoin truth table . . . . . . . . . . . . . . . . . First adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder Second adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder Third adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder Fourth adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder First adjusted Static Buffered Half Adder circuit parameters . . . . . . . Second adjusted Static Buffered Half Adder circuit parameters . . . . . . Third adjusted Static Buffered Half Adder circuit parameters . . . . . . . Second adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder Third adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder Fourth adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder

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Acknowledgements

The work presented in this thesis represents the outcome of my Master thesis at the Computer Engineering (CE) laboratory of the Electrical Engineering department, Delft University of Technology, Delft, The Netherlands. First I want to return my unparalleled thanks and adoration to My Lord and Saviour, JESUS CHRIST, for His mercy, strength, courage, providence, and wisdom through out this master study. I want to sincerely thank my advisor, Sorin Dan Cot¸ofan˘a for his confidence, belief, continuous support, patience and his invaluable advices that have enormous contribution to my thesis work. His deep insight into problems has exceptionally inspired and enriched my growth as a student. I would like to thank these persons, Sandra Ijeoma Irobi and Dr. Ir. A. N. Ajah who have contributed in my coming to the TU Delft, The Netherlands for Master study. I want to thank all colleagues at CE Laboratory: Saleh Safiruddin for finding time to read and correct my thesis, Mottaqiallah Taouil for valuable academic discussions, Pavel Zaykov for his readiness to assist, Karthik Chandrasekar, Madhavan, Armin, Cor Meenderinck, Kazeem Gbolagade for his encouragement right from start, Ann Nkeng, Fredrick Ezeh, Andre, Halil Kukner, Zaiyan e.t.c. I want to thank Ir. Beckley, Ir. Alex Dawotola, Pastor Hycinth and Helena Nwosu, Chimdi, Okpanachi, Ayo, Eguono, Mike, Kehinde, Deborah, David, Sam Ani, Solomon Agbo, Aaron, Roel, that have assisted me in one way or another. Again, I want to thank my family friends, Alex Ogonna Ogbodo, Chukwudi Agbo, and Gabriel Ugwuchukwu for their kind words. I want to thank Nkiru Ede for her kind encouraging words. Last and not the least, I want to thank my family for their love, support, and understanding through out my days for Master studies.

Innocent Okwudili Agbo Delft, The Netherlands February 25, 2010

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1

Introduction

Reduced power consumption of integrated circuits may continue for decades and this has attracted a lot of research interest. Devices are being switched with fewer numbers of particles. We can see that this lower energy consumption will ultimately result in reduced heat dissipation which is advantageous to VLSI systems as it affects cost. On the other hand it is less reliable, since thermal noise will exceed binary switching operation. Hence, the major problem in the operation of nanometer scale electronic devices is the interference of noise and fluctuations. Noise and fluctuations have been considered undesirable in VLSI systems. As a result of this undesirability, several techniques to tackle this problem have been studied by turning this noise and fluctuation into an asset for arithmetic computations. Techniques have been proposed that have been of interest in exploiting fluctuations for computation. This is the fundamental direction which this research will take.

1.1

Problem Statement

In the past several years the processing power of logic and arithmetic circuits have increased dramatically. This increase is because of advances in the complexity of computer programs. It is because of this ongoing increase in the complexity of computer programs that has led to the need for powerful computer machines. This is followed up by the Moore’s law [22], [23] that stated the processing power would double every 18 months. This law has remained true up and untill date from the period of prediction since 1965. CMOS has been the basis on which circuit technology has developed and it has maintained feature size down-scaling and will remain to do so in the near future as predicted by Moore resulting in CMOS technology being the dorminant technology today. The International Technology Roadmap for Semiconductors [1],[2], has made predictions that the gate lengths of MOS-FET will reach 10 nm. Again, the prediction continues that devices with electrical current will shrink gradually towards requiring the transportation of individual electrons. Today’s circuits have errors largely in the form of undesired tunnel currents via thin oxides [16]. This continuous scaling has merits as follows: higher package densities, lower power dissipation, faster circuits, and lower cost. However, it is obvious that CMOS technology cannot be shrunk indefinitely, this is because of fundamental physical limitations [1], and as a result scaling will no more be possible. More so, scaling into the sub-micron region is predicted to be very difficult, since undesired effects would begin to dominate. The Quantum Effect is notable among 1

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CHAPTER 1. INTRODUCTION

all these effects, which causes electrons to penetrate potential barrier by tunneling phenomena. This causes leakage in current CMOS technology nodes and is the source of errors and extra power consumptions [27]. As CMOS technology is drawing to the end of its regime, several other emerging technologies are currently being investigated [1], such as: Single Electron Tunneling (SET), Molecular devices, Spintronics, Ferromagnetic logic, Carbon Nanotubes, Rapid Single Flux Quantum (RSFQ), Resonant Tunneling Diodes (RTD), and Magnetic Spin devices. Single Electron Tunneling (SET) technology has a number of merits over the current CMOS technology, and they are as follows; firstly, it has greater scaling ability than CMOS technology; secondly, it has the ability to realize circuits that have ultra low power consumption than it’s counterpart CMOS technology circuitry. However, in addition to other future candidate technologies, Single Electron Tunneling (SET) technology displays a switching behaviour that is different from traditional MOS devices [8],[9]. The introduction of quantum tunnel junction that enable the control of single or few electrons has opened a broad range of possibilities for calculations in Single Electron Tunneling (SET) technology. Hence, while quantum mechanics effects have been a source of error in CMOS technology and are limiting its scalability, SET utilizes them efficiently as basis for computation. Moreover, the power consumption of SET circuits can be reduced drastically with single electron transport based computations. This has opened up novel computational paradigms avenues. In the past few years, considerable research interest has emerged with techniques to effectively utilize the fundamental SET features. Instances of such efforts have emerged in two schemes, and they are Single Electron Encoded Logic and Electron counting schemes [24], [10], [18], [17], [21]. In this scheme there is lowered energy consumption, which results in substantially reduced heat dissipation. It is, however, ultimately restricted by the thermal limit [19], [25]. One of the most important challenges for implementing circuits based on quantum tunneling thus far has been the stochastic nature of the tunneling process [9]. When the tunnel junction’s actual voltage Vj exceeds the tunnel junction’s critical voltage Vc , tunneling through the tunnel junction is possible, Vj > Vc else tunneling is not possible. The circuit delay cannot be analyzed in the traditional sense rather each transported electron affects the switching delay. The direct utilization of SET-based computation in building synchronously timed arithmetic unit has been hindered by this probabilistic delay, since the exact time of tunneling of an electron is not ascertained. Therefore, extensive error correcting schemes are needed and lengthy switching times. Based on the foregoing, research motivation has emerged for SET architectures and circuits based on delay-insensitive computations so as to eliminate the problems of un-ascertain delays. The exploitation of the weak points of Single Electron Tunneling (SET) technology, i.e, the sensitivity to noise and fluctuations, into an asset has been proposed, and this has been used in the simulated annealing scheme in Boltzman machines [30]. Single

1.2. OBJECTIVES AND CONTRIBUTIONS

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Electron Tunneling (SET) technology is appropriate for implementing the token-based nature of this architecture. Hence, the circuit’s ability to exploit fluctuations rather than employ classical noise-suppressing techniques, offer the potential to work closer to the thermal limit. This therefore results in the relaxation of the limitations on operating temperatures of nanometer scale devices toward room temperatures. In [35] the potential fluctuation utilization in the arithmetic circuit operation implemented by Single Electron Tunneling (SET) technology was investigated. The two SET circuits: the Hub and the Conservative Join building blocks that were designed with fluctuations in mind were presented. The proposed building blocks resulted from the concept of Brownian circuits [25], [19]. They have proved to form a universal set from which any desired functionality can be designed. In Brownian circuit systems, circuits function correctly despite any delays, thus showing the power of Brownian motion on its searching potentials which permits a circuit to backtrack out of deadlock situations. Hence, one of the major demerits of Single Electron Tunneling (SET) technology, its stochastic behaviour, is turned into an asset in Brownian circuit system in realization of logic and arithmetic computations. Computations are then made through the random scheme, in which Hub acts as a fluctuation building block, repeatedly offering tokens at its output terminals and taking them back when they are not delivered. The key to the operation of Brownian circuit is the fluctuations of the token that is injected into the wire. Due to this fluctuations this token will search for a match by looking through any connected wires. Though, we emphasize that this circuit can only operate correctly when tokens are subject to fluctuations. The circuit may end up in a deadlock in the absence of fluctuations. Calculations are made based on arriving tokens rather than with absolute values as it is the case with synchronous logic. With the unique ability of Single Electron tunneling (SET) technology to control the individual electron, we target utilizing the transport of single electrons to arrive at the desired functionality of Brownian circuits efficiently. The input and output signals of Brownian circuits can be represented by a single electron charge. The arrival of an input at one of the building blocks is then in the form of a quantized charge [27]. The functionality of the block and the charges arriving at the inputs determine the charge placement at the output. Single Electron Tunneling (SET) technology topologies are proposed as a function of the required functionality that could potentially transport this charge around the circuit in a way that would result in a charge or token being available at the output to enable basic computations.

1.2

Objectives and Contributions

Several techniques have been proposed in alleviating the problems of random fluctuation’s factor interfering with the operation of nanometer scale electronic devices. Such techniques stems from noise suppression, to detection and correction of errors via the encoding of information in a redundant way, to advocating limiting applications to those

4

CHAPTER 1. INTRODUCTION

that have inherent robustness to noise, as image processing and probabilistic algorithms and to exploiting noise and fluctuations inspired by biological schemes. The goal of this thesis assignment is to exploit randomness of Brownian motion schemes in Single Electron Tunneling (SET) technology for logic and arithmetic computations. The Hub and the Conservative Join are two building blocks for SET circuits designed with fluctuations in mind [29],[28]. These building blocks were proposed within the Brownian circuits context. More so, circuits based on these designs functions as expected in simulations but are not implementable industrially. This is because of the Conservative Join circuit parameters and routing wire not meeting with the manufacturing constraints. Though, Hub design does meet the manufacturing constraints. The two major constraints are as follows; first, the Conservative Join has a long diagonal wires that appear on the design literally. Second, the circuit parameters of the tunnel junction capacitances fall short of the industrial standard [31] More particularly; we investigate the following research questions: • Is it possible to realize an industrially implementable Conservative Join, CJoin (redesignCJoin) where long diagonal wires are eliminated and realize circuit parameters O(0.1aF ) for tunnel junctions that conform to the industrial standards? • Is it possible to realize a network of implementable Conservative Join, CJoin with fluctuation based building block, Hub and form larger networks composed out of such SET-based building blocks? If so, can we form large network for two Hubs and one Redesign CJoin, three Hubs and two Redesign CJoin, and four Hubs and four Redesign CJoin (i.e 2 − by − 2 CJoin)? • Given the networks of implementable Conservative Join, CJoin with fluctuation based building block, Hub, can they be utilized in logic and arithmetic computation? If so, can we compute for a 2 − by − 2 CJoin based NAND-gate, NOR-gate and HALF-ADDER? • Can the tokens at the output of the Half-Adder be consumed? If so, is it possible to realize a static buffer circuit parameter at T = 1K that consumes the token? If so, can we form a large network composed out of Half-Adder with a static buffered circuit to consume the output token? Then, the main contributions of this thesis are stated as follows: • We proposed a new Conservation Join design with circuit parameters and circuit element placements that do meet the industrial requirements for manufacturing and it is verified by means of simulations. • We demonstrate that the new Conservation Join design can coexist with fluctuation-driven building block. The network was verified by means of simulations.

1.3. OVERVIEW

5

• We demonstrate that these SET-based building blocks can form a large networks to compute for a family of gates consisting of NAND gate and NOR gate and simulate the gates. • We similarly demonstrate that these SET-based building blocks can form a large networks to compute for logic and arithmetic computation consisting of a HALFADDER and the network is verified by means of simulations. • We obtained a static buffer circuit parameter at T = 1K that is compatible with HALF-ADDER and it is verified by means of simulations, i.e, using SIMON 2.0 simulator [7]. • We apply the static buffer to consume the token at the output of the HALFADDER and we demonstrate that they can coexist in the large network, and it is verified by means of simulations.

1.3

Overview

The remainder of this thesis is organised as follows: In Chapter 2 relevant SET background concepts are presented, explaining the tunneling behaviour appearing in SET circuits and previous work related to SET Electron box, SET transistor, and SET buffer are discussed. In the same chapter, the Brownian motion circuit concepts are described followed by Dual rail coding logic, which is a systematic technique to construct Brownian logic circuits. In Chapter 3 Implementable basic building blocks for Single Electron Tunneling (SET) based Brownian circuits are presented. In Chapter 4, Networks of SET based Brownian circuit building blocks are introduced. The implementation of 2-by-2 CJoin based NAND gate, NOR gate, HALF-ADDER, and Static buffered HALF-ADDER are presented. Finally, Chapter 5 presents the conclusions along with recommendations for future research work.

6

CHAPTER 1. INTRODUCTION

2

SET Background

In this chapter the background concepts of Single Electron Tunneling (SET) Technology, Brownian Motion circuit concepts and Dual Rail Coding logic is presented. In section 2.1, we present the SET concepts and for detail discussion on the physics of SET devices the reader is referred to [33],[35]. We present SET Electron Box, SET Transistor and SET buffer in section 2.2. Then section 2.3, introduces the concepts of Brownian motion circuits. Dual Rail Coding logic is discussed in section 2.4. Finally, in section 2.5 an overview of the chapter is presented.

2.1

SET Concepts

In the study of classic physics theory electrons are treated as particles and this theory shows that electrons are not allowed to cross a barrier like a piece of insulator. This is because an electron doesn’t have enough energy to overcome the energy band gap and then reflects back. However, in the 1920’s new insights about the characteristics of electrons were found by L. de Broglie [26] and Schrodinger and this resulted in the formulation of the Schrodinger wave equation. Again, in quantum physics an electron can be perceived as both a particle and a wave function. The latter behaviour was described by the Schrodinger wave equation, and this forms the basis for quantum mechanics. Hence, according to the Schrodinger wave equation there is a chance that an electron tunnels through a barrier and enters into a classically forbidden region. This is known as the quantum tunneling effect phenomenon. Moreover, the junction via which the electrons will or will not tunnel is known as quantum tunnel junction and this is shown is Figure 2.1. The basic Single Electron Tunneling, SET circuit comprises of tunnel junctions and capacitors.

Symbol Figure 2.1: Quantum tunnel junction circuit symbol The tunnel junction is made by inserting a thin insulator in-between two separated conductors making it behaves as a capacitor. The movement of electron via the tunnel junction can be controlled by the potential difference across it. This is because as the potential difference increases it directly affects the increase in charge accumulation at 7

8

CHAPTER 2. SET BACKGROUND

the surface of the electrode against the isolating layer, until a high enough bias has built up across the tunnel junction, and one electron will be transferred. However, the tunneling of an electron via the tunnel junction is known as tunnel event. The behaviour of the junction is analogous to a diode but the difference is noted at the scale in which switching occurs. Transporting of charge via a tunnel junction occurs at a number of a single electron per time. This transport of a single electron effects the voltage across a tunnel junction meaning that a few electrons through a tunnel junction will hinder further charge transport, hence achieving the possibility of controlling the transport of charge in discrete and accurate quantities. The tunnel junction is distinguised by a junction capacitance and resistance, represented with Cj and Rj , respectively, in which each of them depends on the thickness of the insulator (non-conductor) and the physical size of the tunnel juction. However, the principle of operation of SET circuits is a function of the controlled transport of charge through tunnel junctions. Charge transportation through a tunnel junction is referred to as tunneling. By assumption, a tunnel event is only possible if this is energetically favorable for the complete circuit in which the tunnel junction is embedded. Electrons are considered to tunnel via the tunnel junction strictly one after another during tunneling [6],[16]. A single electron is the minimum quantity of charge that can be transported through a tunnel junction. Moreover, the presence of charge on a tunnel junction can have any value, including arbitrary fractions of the electron charge. In an instance, when there is no tunneling, the SET tunnel junction behaviour electrically correspond to a classic capacitor. The charge of a capacitor, q q2 contributes 2C to the energy present in the circuit. This means that tunnel events j change the energy of the circuit in steps of: q2 ≡ Ec 2Cj

(2.1)

where C is the capacitance of the island and qe is the charge of an electron (1.60217 ∗ 10−19 C), is required. A tunnel event cannot happen if the Coulomb energy is not available. This is known as Coulomb blockade. Moreover, electron tunneling is a quantum mechanical process described in [34], [16]. This is governed by the principle that an electron’s wave function extends through the tunnel barriers, hence the electron charge is spread over the capacitive islands in a SET circuit. Then if the spreading of electron charge over the capacitive islands in a SET circuit succeeds, there would be considered no localized charges, therefore computation utilizing electrons would not be possible. In order to ensure charge quantization, the electron’s wave function should be located either on one side of the barrier or on the other side. This requires the tunnel junctions having a sufficiently high tunneling resistance, thereby enabling the charging energy, also known as the Coulomb energy to dominate over the quantum charge fluctuations. This is expressed thus: qe2 h Rj Cj  h ⇔ Rj  2 ≡ 25.8kΩ 2Cj qe

(2.2)

where h is the Planck’s constant while notation of Cj and Rj has been mentioned above. The commonly used value for the resistance Rj of all the tunneling junctions in this

2.1. SET CONCEPTS

9

research is 100kΩ which has been used in previous research work [10], [18], [17], [24], [21]. The amount of free energy before (Finitial ) and after (Ff inal ) determines whether the tunnel event will occur or not due to decrement or increment of the tunnel event. More so, if the decrement of free energy as a result of tunneling event, then tunneling would occur after some time, hence bringing the circuit to a lower energy state. One must calculate the tunneling behaviour of electrons by determining the free energy before and after a potential tunneling event. With the increase in the amount of circuit element, the approach of determining whether tunneling occurs or not using free energy calculations is increasingly becoming complicated. And again it becomes prohibitive when performing calculations for circuits with an amount of elements required to create useful logic circuits. Moreover, with the introduction of critical voltage (that is Coulomb gap) the calculation determining whether a tunneling event occuring is reduced to the comparison between the applied voltage over the tunnel junction and its critical voltage. The expression of change in free energy ∆E is shown in equation 2.3 below. ∆E ≡ −qe (|Vj | − Vc )

(2.3)

where Vj is the applied voltage due to tunnel junction and Vc is the junction’s critical voltage. This approach predicts that an electron only tunnels if the voltage across the tunnel junction (Vj ) is greater than sum critical voltage (Vc ). |Vj | > Vc

(2.4)

The critical voltage of a junction can be determined by determining the capacitance of the circuit as seen from the tunneling junction. This is achieved by using the Thevenin equivalent circuit. All charges on nodes and voltage sources are disregarded or taken as zero, the voltage sources are replaced by grounded wires and this enables capacitive equivalent calculation. The circuit depicted in Figure 2.2 is assumed for Thevenin equivalent circuit calculation. Using the example case above we can determine equivalent circuit capacitance. This is realized using Kirchoff’s laws. The expression of equivalent capacitance for Cj is shown in the equation 2.5 below: Cx Cy + Cz ≡ Cv (2.5) Cx + Cy Then calculating for the serial combination of Cv and Cw helps to obtain the capacitive equivalence, Ce stated thus: Cw Cg



Cx Cv Cx +Cv

Cw + Cg +





Cx Cv Cx +Cv

 ≡ Ce

(2.6)

However, combining Equations (2.5) and (2.6) will lead to a complex relation for the capacitive equivalence, Ce . Hence, for simplicity sake showing that the difference in accuracy is not so high, we will leave it as it is stated above. The relation of the critical voltage of the considered tunnel junction is stated thus: qe Vc ≡ (2.7) 2(Cj + Ce )

10

CHAPTER 2. SET BACKGROUND

Cy Vs Cx

Cz Vi Ce

Cw

Cj

Cj

Cg

Figure 2.2: Equivalent circuit for determining the critical voltage In which qe = 1.602 ∗ 10−19 C, and Cj is the capacitance of the tunnel junction while Ce is the equivalent capacitive value of the remainder of the circuit as highlighted in the above relations. A tunnel junction is said to be stable if the tunnel junction voltage is less than the critical voltage else it is unstable. More so, a circuit is stable if all tunnel junctions in that circuit is stable. Then, if the tunnel junction is unstable, an electron tunnels after some time. Due to the probablistic nature of quantum tunneling, we can only give the tunneling probability of an electron. The probability that error occurs imply no tunneling of electron take place and when the probability increases means an increased waiting time for the tunnel event to take place. The probability error is a function of tunnel rate. And the tunnel rate can be expressed thus: Γ=

|Vj | − Vc qe Rj

(2.8)

A probabilistic model is required in calculating tunneling delay. This is a consequence of tunneling being stochastic in nature. The error probability is expressed as follows: Perror = e−Γtd

(2.9)

where td is the process start time in seconds. Hence, equation 2.9 can be rewritten to calculate the needed delay time for some probability error. −ln (Perror ) (2.10) Γ Moreover, substituting for probability error and tunnel rate in equation 2.10 will yield the following relation stated thus: td =

td =

−ln (Perror ) qe Rj |Vj | − Vc

(2.11)

2.2. RELATED WORK

11

In this thesis as a result of previous studies, the probability error and tunnel resistance is taken to be Perror = 10−8 and Rt = 105 Ω respectively. Secondly, we will consider the effect of thermal energy, that is if thermal energy has dominance over the charging energy, Ec , implying that the effects of quantization are not observable. For any temperature greater than 0K there is a non-zero probability that an electron will tunnel via a tunnel junction even if the tunnel junction’s voltage is less than the critical voltage as stated earlier. Then the error probability as a result of tunneling caused by thermal effects can be described by a simple relation stated thus: −∆E

Ptherm = e KB T

(2.12)

Hence, to ensure that thermal tunneling does not dorminate charge quantization, the condition stated below should hold: Ec =

qe2  KB T 2C

(2.13)

in which KB is the Boltzmann’s constant and T is the absolute temperature.

2.2

Related Work

In this section, we shall look at some of the related work done in the previous research which stems from the most simple SET circuitry, that is, electron box. Next, we will further discuss SET transistor and finally SET buffer.

2.2.1

SET Electron Box

One of the most simple SET circuit is the electron box depicted in Figure 2.3. It is composed of a quantum dot or island connected with two electrodes. On one part, it is connected through a tunnel junction to a voltage source, and this is formed with a thin piece of insulator. While on the other part, it is connected through a capacitor to the ground, and the capacitor is formed with a thick piece of insulator. The tunnel junction, quantum island and capacitor are in series connection with each other. An island contains no net charge, which implies that it contains the same quantity of protons as it contains electrons. Moreover, an electron can be added into or removed from the quantum island through the tunneling junction via tunnel event. For an electron to tunnel into or from the quantum island via the tunnel junction, the Coulomb energy is required. The Coulomb energy is expressed in this relation: Ec =

qe2 2C

(2.14)

in which C is the capacitance of the island and qe is the charge of an electron (1.60217 ∗ 10−19 C). However, the tunnel event cannot take place if the Coulomb energy is not available. Coulomb blockade phenomenon results only when an electron has tunnelled through the

12

CHAPTER 2. SET BACKGROUND

q

Vb

Figure 2.3: The Electron Box circuit tunnel junction. The energy required for an electron to tunnel can be provided by the Voltage source. Then an electron tunnels from and into an island if the bias voltage exceeds a certain value. Hence, the bias voltage helps in controlling the amount of electron present on the island. Increasing the bias voltage will populate the electron particle with a certain amount of electrons, therefore leading to a staircase-like feature. Since there are other sources of energy apart from voltage source, as thermal energy source which can provide the required energy for the tunnel event. And while thermal energy is not desired, then the thermal energy kB T should be much less than the Coulomb energy required for a tunnel event. This is shown in the Equation (2.15): Ec =

qe2  kB T 2C

(2.15)

in which T is the absolute temperature in Kelvin and kB is the Boltzmann’s constant (1.38066 ∗ 10−23 JK −1 ). This implies that the quantum island capacitance should be in the magnitude order of 1a F or less for room temperature operation. This condition is true for most circuits, though in this thesis, simulations were done assuming a 1K temperature. Hence, assuming a 1K temperature we assured that the simulation results showed functional behaviour only, since the focus of this thesis is on the computational aspects of SET circuits. The other condition for observing tunneling phenomenon, is that an electron is assumed to be well localized in classical theory, in which electrons are described by wave functions in the quantum mechanics theory, showing the chance of the presence of an electron. Again, the electron wave function extends through the barrier and the electron is not obviously localized on the quantum island due to insufficient opacity of the tunnel barrier. The tunnel barrier opaqueness is described by the tunnel resistance Rt . The conditions [20] for observing SET charging effects is depicted in the expressed relation 2.16: q Rt  2 = 25.6kΩ (2.16) qe in which h is Planck’s constant (6.62607 ∗ 10−34 Js). For the derivation and explanation of this equation, the reader can go through this reference [36],[15], [20], [33]. The commonly used tunnel resistance value, Rt of 100kΩ is utilized throughout this thesis work.

2.2. RELATED WORK

2.2.2

13

SET Transistor

The simplest device that can be constructed with SET junctions is the SET transistor [13], [20], [32], [3], [14], [12]. It is comprised of two tunnel junctions connected in series, and a gate electrode which is either resistively or capacitively connected to the quantum island formed by the node connecting the two junctions [3]. These are known as threeterminal switching devices. This can transfer electrons from source to ground one by one. However, the resistively coupled SET transistor is very difficult to realize, this is because the gate resistor must have a large value. However, in this research work our interest is on the capacitively coupled gate transistor and this can be depicted in the Figure 2.4 below. I

d

Cj1 Vg

Cg

Cj2

Figure 2.4: The SET transistor circuit Hence, the tunneling of electron through the SET transistor begins from the source tunnel junction to the quantum island and from the quantum island through the drain tunnel junction. However, whether the electron tunnels is a function of the charge present on the quantum island or due to the discrete changes with the elementary charge, that is, when electron tunnels via the tunnel junctions, which can be modified continuously by a voltage over a capacitor Cg . Then the gate electrode effect is that the background charge q can be altered at will, this is because the gate voltage in addition polarizes the quantum island, in that the quantum island charge becomes q = −ne + q0 + Cg (Vg − V2 )

(2.17)

Then substituting q0 = q0 + Cg (Vg − V2 ) in V1 and V2 of the double junction relation stated in [33] yields the new voltages across the junctions stated in the relations below: V1 =

(C2 + Cg )Vb − Cg Vg + ne − q0 CΣ

(2.18)

C1 Vb − Cg Vg + ne − q0 CΣ

(2.19)

V2 =

where CΣ = C1 + C2 + Cg . However, the electrostatic energy includes the energy stored in the gate capacitor, then the work done by the gate voltage should be accounted for in the free energy. Moreover, the free energy change after a tunnel event in tunnel junctions

14

CHAPTER 2. SET BACKGROUND

one and two is stated in the relations below: ∆F1

±

e = CΣ

∆F2

±



e ± ((C2 + Cg )Vb − Cg Vg + ne − q0 ) 2

(2.20)

e ± (Vb C1 + Cg Vg − ne + q0 ) 2

(2.21)

e = CΣ







Only transitions with negative free energy change, ∆F1 < 0 or ∆F2 < 0 at zero temperature are permitted. Hence, these conditions may be used to generate a stability plot. The discussion on Coulomb oscillation is beyond the scope of this work. Operation of SET transistor The concept of operation of a SET transistor is that tunneling of a an electron through one of the tunnel junctions can cause that tunnel junction to be in coulomb blockade and hence, at the same time suppress the blockade of the other tunnel junction. In this manner, electrons can only transport through the SET transistor one at a time. More so, an excess electron, on the quantum island decreases the island voltage by a voltage CeΣ = 2mV as mentioned in [13]. This means that before and after tunneling through the tunnel junction, the quantum island voltage were between 1mV and 2mV and between −1mV and 0mV respectively. Therefore this causes the source tunnel junction in Coulomb blockade, in which no more electrons can tunnel through. One electron can then pass from source to drain, and the original voltage state is restored. The single-electron transistor’s operation can be described by using Thevenin’s theorem. Though, the detail derivation of the condition to maintain the electron number at n in the quantum island is beyond the scope of this research studies. Next we will discuss Single Electron Tunneling, SET Buffers.

2.2.3

SET Buffer

The concept of SET Buffers was introduced due to the feedback effects which occur in network of passive SET gates. The earlier investigations into this problem has resulted in reducing the crosstalk effects by utilizing an active buffer as a back-end for the passive SET gates. The passive elements are tunnel junction and capacitors. Following this earlier investigations in [18], four SET buffer were observed according to the SEEL paradigm. These include two dynamic buffers and two static buffers. In this research, our interest is centered on the static buffers which includes non-inverting static buffer and inverting static buffer. However, utilizing the dynamic non-inverting buffer proposed in [16], the static buffers design were extended with a second SET transistor as depicted in the Figure 2.5 below. However, the upper SET transistor features junctions J1 and J2 with a capacitor Cg1 operates as previously stated in SET transistor, though only transports a single electron from node n2 to Vs when the input voltage, Vi is ’high’. Then the lower SET transistor transport an electron when the input voltage, Vi is ’low’ that is from Vd to node n2. This shows that the buffer switches output values as a result of transporting

2.2. RELATED WORK

15

Vs J1 Cg1

Cb1 n1 j2

Vin

Vout n2 J3 Cg2

Cl

Cb2 V(1) n3 J4

Vd Figure 2.5: Static Inverting buffer an electron without a further need for reset phase. This Buffer design is made by simply observing that both the lower and upper SET transistors function complimentarily to each other. This implies that when the input voltage, Vi of the upper SET transistor is ’high’ constraint the charge transport from the lower SET transistor, in which a ’low’ input enables it and vice versa. Moreover, the transport of charge in the lower transistor is directly opposite to the transport of charge in the upper transistor. Hence, the transport of charge in the lower transistor do occur firstly from node n3 via tunnel junction J3 to node n2, then secondly, tunnel event do take place via tunnel junction J4 . From the foregoing, the upper transistor, when combined with the bias capacitor Cb1 , displays a switiching manner analogous to CMOS p-type transistor. The same thing goes for the lower transistor when combined with bias capacitor, Cb2 , which displays a switching manner analogous to an n-type transistor (see Figure 2.5). In summary, the Buffer circuit operation results in when input voltage, Vi is low then the ouput node, n2 is ’high’ and when the input voltage is ’high’, then the output node is ’low’. Similarly, we assume that the J1 , J2 , J3 , and, J4 junctions have a C1 , C2 , C3 , and, C4 capacitance respectively. This implies that the lower transistor is a replica of the upper transistor by choosing Cg1 = Cg2 , C3 = C2 and C4 = C1 . Then, the voltages across the tunnel junction J3 and J4 are set in a manner that their absolute values are equivalent to those used in accomplishing switching in junctions J2 and J1 , respectively. The upper and lower transistor would display the same switching behaviour for equal values of Vi if we

16

CHAPTER 2. SET BACKGROUND

Capacitance(s) C1 , C4 C2 , C3 Cb1 , Cb2 Cl

Value(aF) 0.1 0.5 2.7 9

Table 2.1: Static Buffered Circuit parameters

set Vd = Vs . The same idea goes for setting Vd = −Vs and applying −Vi as input for the lower transistor. The two transistors would still display the same switching behaviour for equal values of Vi and again the transport of charge in the lower transistor would take place in opposite direction. The detail explanation of the conditions under which tunnel event can occur is given in [18]. Next is the Buffered SET circuit parameters achieved at an operating temperature T = 1K, which is different from the previous work at an operating temperature of T = 0K. Buffered SET Circuit Parameters The circuit parameter of Static Buffer is stated in the Table 2.1 above. We can observe from the above parameters that the difference from the previous work is in the both biasing capacitors and the operating temeperature which is now at 2.7aF and 1K respectively, though the circuit behaviours remain the same. This we can see from the simulation results using the single-electron device and circuit simulator SIMON (SIMulation Of Nanostructures) [7]. The idea of investigating the operation of Static Buffered SET circuit at temperature T = 1K is for future utilization with other circuitry that operates at same temperature. This is hereby allowing the cascading of these different circuit component to be compatible at 1K temperature. The instance of this can be seen subsequently in the later section of this research work. Simulation Results The simulator parameters include a tunnel resistance Rt = 105 Ω and an operating temperature T = 1K while Vs = 16mV . The simulation results are depicted in Figure 2.6 below. As we can observe, the active buffer performs the logic invert function correctly and produces the required voltage levels and operates on a DC supply voltages only. This is shown starting from the top, the first bar displays the supply voltages Vs , then the second bar displays the input voltage Vi , and then the last bar displays the output Vo . Note well, that the static SET buffer switches output values as the result of the transport of one electron only.

2.3. BROWNIAN MOTION CIRCUIT CONCEPTS

17

Static Buffer simulation 0.02

mV

input

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

output

0 0

0.2

0.4

0.6

0.8

1

time

Figure 2.6: Static Inverting buffer simulation results

2.3

Brownian Motion Circuit Concepts

The concept of Brownian motion was introduced since noise and random fluctuations are vital hinderances in the ongoing development of integrated electronic circuit, hence motivating new strategies to alleviate their effects. Some of these strategies are as follows: first is suppressing noise, second is the detection and correction of errors via the information encoding in a redundant way, third is limiting applications to those that have inherent robustness to noise, that is, living with it and the fourth strategy is exploiting it. Hence, noise and fluctuations as a resource to explore the computational state space of token based circuits. However, in this thesis work, we are interested in the latter strategy of exploiting fluctuation in logic and arithmetic computation. Therefore, Brownian motion can be decribed when the motion of tokens in wires and modules fluctuates, that is moving forward and backward repeatedly. One of the important advantage of this strategy is this ability to search through the topology of the circuit, allowing them to backtrack out of deadlocks. Moreover, since Brownian circuits are under delay-insensitive circuits, then any delays to tokens as a result of Brownian motion do not affect the correctness of the circuit’s operation. In Single Electron Tunneling technology, electrons have a non-zero chance of tunneling via a tunnel junction, that is at temperature above 0K even though the conditions for critical voltage is not met. Hence, thermal fluctuations cause this tunneling. As a result of this led to random movement of electrons through a SET circuit, these electrons are evenly distributed. The application of this thermal fluctuation can be seen in [5] where the Brownian motion effect has been used to create Quantum Ratchets. As a result of this random fluctuation that is interfering with the operation of nanometer scale electronic devices, then F. Peper et al have undergone recent research proposals to exploit the signal fluctuations in SET logic and arithmetic circuits [25], [19]. This concept has been applied in the simulated annealing process of a Boltzmann

18

CHAPTER 2. SET BACKGROUND

machine implemented by Single Electron Tunneling, SET devices [30].The first proposed circuit primitive is known as T-element that proves to be universal for a class of circuits called T oken − P ass circuits but this is under the condition that signals undergo fluctuations. The powerful key of fluctuations is the signal’s ability to backtrack out of deadlocks, and this is common in asynchronous circuits with discrete signals. The T-element together with Token-Pass circuits, both have a somewhat rigid structure that is basically a set of wires that can interact with each other at certain locations in very restricted ways. Hence, this has posed efficiency queries on this design. Then, this has led to less complex design than T-element. The two building blocks operating on similar principle in the context of the so-called Brownian circuits have been proposed [25], [19]. The notion of Brownian circuits is to utilize fluctuations to guide signals through a circuit. In which, the search process is driven by fluctuations via a Brownian maze formed by the topology of the circuit [25]. Then the two circuit elements that are less complex than T-element which can be used as primitives of a universal class of Brownian circuits are called the Hub and the Conservative Join (CJoin). These two proposed building blocks have been shown to form a computationally universal set in which any desired functionality can be built [19]. However, we are going to see in this thesis work, the instances of logic and arithmetic computation with these blocks. More so, Single Electron Tunneling technology provides a suitable locations corresponding to Coulomb islands where the signals of Brownian motion resides, this is because of the token-based nature of signals and another factor of discreteness in Brownian circuits. More on the Hub and the Conservative Join (CJoin) will be discussed subsequently on the course of these work. Hence, for detailed exposition and analysis of Brownian motion the reader is referred to [11] since this is outside the scope of this research work. Next, we will be discussing Dual Rail Coding logic.

2.4

Dual Rail Coding logic

Dual-rail coding is one of the techniques used in Data transfer. It is a technique used most widely, in which two tracks are used to represent one bit of data. For instance, a ’0’ value is used by one track where as a ’1’ value is used by another track. However, the receiver can, hence know exactly when a bit of data has been transmitted and as well acknowledge same by sending a signal back. Though, Data transfer scheme can be realized by utilizing handshaking protocols mentioned in [27], [4] together with data encoding schemes in which data can be transmitted in a delay-insensitive manner [4]. The Sender and Receiver module communicating with the Dual − rail code is depicted in Figure 2.6 below. Data can be sent using pair of wire that is for each bit, two wires I0 (0) and I0 (1), this is for the first bit, and the same goes for the subsequent bits. Moreover, the receiver performs action and send back an acknowledgement signal once a transition has occurred on one wire in each pair. The number of wires required to send 2n unique messages with this scheme is 2n wires. Then comparing n > 2 Dual − rail coding with One − Hot coding, which is another coding technique, shows that Dual − rail coding technique has a marked improvement over One − Hot coding. Again, One − Hot can send only n

2.4. DUAL RAIL CODING LOGIC

19

I0 (0) I0 (1) I1 (0) I1 (1) I2 (0) I2 (1)

Sender

Store

I2 I1 I0

Receiver ack

Figure 2.7: Dual-rail Data transfer State 1 2 3 4

Inputs 00 01 10 11

Encoding Idle, data not ready Valid 1 Valid 0 Illegal

Table 2.2: Four (4) Phase handshaking Dual-rail Encoding

n

unique messages on n wires while 2 2 unique messages can be sent on the same amount of wires by Dual − rail coding technique. The Dual − rail coding can be used for data transmission with any of the two handshaking protocols. The encoding with four (4) phase handshaking is depicted in the Table 2.2 stated above: However, the inputs is reset to zero ’0’ after each data, thereby putting the communication back into the idle state ready for next transfer. The encoding is more complex with two (2) phase handshaking protocol. This is becuase detecting a ’0’ or ’1’ is depending on both the input levels as well as on the previous input state at the moment the data is transferred. Hence, in Table 2.3 all the possible states are listed together with the corresponding previous input combinations for each input combination. Then the input combination ’00’ can represent a ’0’ or ’1’ depending on if it was ’10’ or ’01’ in the moment before ’00’ was detected. More over, the simultaneous signals on both inputs are prohibited for the two handshaking protocols. There are several Delay-insensitive codes that much efficiently utilize the amount of tracks available but utilization involved encoding schemes, such as Sperner, Berger, and Knuth codes. For instance, 20 unique messages can be sent with 20 lines by One − Hot code, where as 1024 unique messages is sent by Dual − rail code and 184,756 unique messages are sent by Sperner. Thus, for an in-depth understanding and analysis of Handshaking protocols and Delay-insensistive coding schemes, the reader can refer to [27], [4].

20

CHAPTER 2. SET BACKGROUND

State 1 2 3 4 5 6 7 8

Inputs 00 00 01 01 10 10 11 11

Previous Inputs 01 10 00 11 00 11 01 10

Encoding Valid 1 Valid 0 Valid 1 Valid 0 Valid 0 Valid 1 Valid 0 Valid 1

Table 2.3: Two (2) Phase handshaking Dual-rail Encoding

2.5

Conclusion

In this chapter we have presented the Single Electron Tunneling, SET technology background, Brownian motion circuit concept and Dual-rail encoding logic on which we base our implementations. In the next chapter we first redesigned one of the Brownian motion circuits that is Conservative Join (CJoin) to an implementable Building Block, thereby maintaining the same functionality and behaviour. We then utilize the SET Background presented in this chapter to understand and arrive at the required SET topology that can be implemented industrially and exhibit the needed functionality.

SET Based Brownian Circuit Building Blocks

3

In this chapter we present SET Based Brownian circuit building blocks. In section 3.1 we re-visited the previous research on one of the Brownian circuits, that is, Hub circuit, which is fluctuation based building block. In section 3.2 we re-visited again the previous research on the Original Conservative Join circuits, that is, deterministic building block, which serve as a platform for our further research. In section 3.3 we present SET implementable building block for Conservative Join, which we call redesigned CJoin. In sub-section 3.3.1 we propose the new conservative Join, ReDesCJoin circuitry. In sub-section 3.3.2 we discuss the SET Based Brownian building blocks and the proposed implementation of the new design of the Conservative Join, ReDesCJoin. Finally, in section 3.4 we conclude the chapter with an overview.

3.1

Hub Circuit

In this section we want to re-visit the work done in [27] on Hub circuitry which we reverified through simulation, since the goal of this research is to realize complex networks of Brownian circuits for arithmetic and logic computation, which we intend to implement in this thesis work. However, there are two fundamental universal set for Brownian circuits in which Hub circuit is the first Building block of the Fluctuation Based circuit. It contains three bidirectional wires. Next, we will discuss the functional behaviour of Hub. Hub’s Functional Behaviour The transport of tokens from one block to another in a Hub circuit is realized through routing techniques and this implies random scheme in which the token jumps from one wire to another wire to see if it is taken by the other building block otherwise taking it back. Moreover, the Hub needs fluctuations to perform its operation and this is based on the random scheme of signaling. It comprises of three outputs wires. In principle there is at most one signal at a time on any of the wires and this signal can move any of the wires due to its fluctuations. Due to the bidirectional nature of the Hub wires, any of the output wires can equally serve as an input wire as well. This provides its output signal to other building blocks by repeatedly offering its state at its output terminals, and taking it back when it cannot be delivered or it is not consumed by the other building block in the network. The Hub circuit symbol is depicted in the figure below. Hence, the possible transitions and the resulting location of the tokens are depicted in the three states. The token can be on any of the three wires W1, W2,and W3, and it can fluctuate between the wires in any order. 21

22

CHAPTER 3. SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Figure 3.1: Hub Module

Hub SET-based Circuit Topology The functionality of Hub can be exhibited in the SET circuit topology as shown in the Figure 3.2. It is made up of three C-Element structures which are connected to a common node, n1, through which positive charge can be transferred to other nodes. As a result the token is supplied directly into the center of the Hub. On the other hand, the supplied token could be connected to any of the nodes n1, n2, and n3. The total component make up of the circuit is six tunneling junctions and seven capacitors.The Hub circuit topology is depicted in the Figure 3.2 below.

Cs1

J1

J2

Cg

Vs

n1

Cs2

Va

J5

J3

Vs

Vs

Cs3

Cs3

J4 n2 Cg

Figure 3.2: Hub Circuit

J6 n3 Cg

3.1. HUB CIRCUIT

23

Capacitance(s) C1, C3, C5 C2, C4, C6 Cs1, Cg Cs2 Cs3

Value(aF) 10 0.1 10 0.5 0.2

Table 3.1: Hub circuit parameters Hub Circuit Behaviour The operation of Hub circuitry is stated as follows: When the input voltage, Va is high an electron tunnels away from n1 through J2 - J1. This tunneling away of electron create a vacancy on n1, and this allows one of the two SET structures, J3 and J4 or J5 and J6 to supply an electron to n1 from n2 and n3 respectively. Moreover, a low value of Cs2 is chosen such that voltages over the junctions are close enough to their critical voltages so as an increase in energy as a result of thermal energy would randomly cause the elctron to tunneling back into n2 or n3. Then the charge jumps from n1 to n2 or n3 and then back into n1 and then randomly into n2 or n3. Hence, the thermal energy is effectively used as a random control voltage. Derivation of Hub Circuit Parameters To realize the Hub functionality, the circuit has to be sensitive to thermal energy, though thermal energy should not dominate the circuit elements. More so, there shall be enough thermal energy fluctuations to enable electrons to tunnel from one island to another island. The realization of this led to the voltages over certain tunneling junction was brought close enough to their critical voltages such that an increase in the energy of an electron at the junction as a result of the extra thermal energy would at random moments cause the electron to tunnel forward. On the other hand, if there is a decrease in thermal energy, this will cause the electron to tunnel back again. Hence, the thermal energy is used effectively as a random control voltage. Circuit Parameters The circuit parameter is tabulated in the Table 3.1: Simulation Results The circuit maintains stability at a zero supply of charge. We verify the circuitry through simulation by supplying charges at time step 0.0 and 0.1 respectively, this results in a random tunneling of the electron or charge in and out of nodes n1, n2, and n3. The simulation result is depicted in Figure 3.3 stated thus:

24

CHAPTER 3. SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Hub simulation result 0.02 mV

Va 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n2 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n3 0 0

0.2

0.4

0.6

0.8

1

time

Figure 3.3: Hub simulation result

3.2

Original Conservative Join Circuit

In this section we want to re-visit the work done in [27] on Conservative Join, that is, CJOIN circuitry which We re-verified through simulation, since the goal of this research is to realize complex networks of Brownian circuits for arithmetic and logic computation, we intend to implement in this thesis work. The Conservative Join is not a fluctuation based kind of structure but simply put deterministic structure which is designed to work in cooperation with the Hub. Conservative Join’s Functional Behaviour The Conservative Join, or CJoin, can be described as a building block that has two input wires and two output wires in which both input and ouput wires are bi-directional in operation. The CJoin can be explained as a synchronizer of two signals

3.2. ORIGINAL CONSERVATIVE JOIN CIRCUIT

25

passing through it. Hence, when only one token is present at an input wire without a corresponding token at the other input wire, then the CJoin remains inactive. When the two input wires receive tokens at the same time, the CJoin fires and takes the two tokens and then places them at the output, thereby not allowing them to return back. Signals may fluctuate on the input wires of a CJoin, that is between leaving and arriving randomly, but when the signals are processed by the CJoin, they are placed on the output without a possibility of going back, while the signal may also fluctuate at the ouput. However, there may be a reversed operation of CJoin, in which the forward/backward movement of the two signals through it may be repeated an unlimited number of times. As we can observe, bidirectionality has caused no distinction between the input and ouput wires to the CJoin, though the terminology of input and output is still in use as a result of the forward direction of the process. When connecting more than one CJoin to each other, we should ensure that the input terminals face the output terminals. This is not the case with Hubs, which exhibit bi-directional wires, which may be connected to CJoin or other Hubs in any way without a particular orientation.The CJoin symbol is depicted in Figure 3.3 below.

Figure 3.4: Symbol of Conservative Join

CJoin SET-based Circuit Topology The CJoin design is developed from the non-inverting buffer design introduced in [16]. When the inputs of the CJoin circuit have the tokens at the same time, then the circuit draws positive charge from the source thereby placing it on the output of the buffer structure. However, this output controls the tokens at the input to the output, then the positive charge is grounded. Hence, the circuit is made up of fourteen(14) tunnel junctions and seventeen(17) capacitors. The circuit topology of the implemented Original Conservative Join is shown in Figure 3.4. From the latter schematic diagram we can observe some diagonal wires running through the circuitry and this has resulted in the wire routing not meeting the manufacturing constraints of the industrial manufacturing requirements. As we will observe later, the circuit parameter is not compliant with the industrial demands, therefore leading us to propose

26

CHAPTER 3. SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

a new Conservative Join that will meet these demands. We will tackle this in the next section.

Vs

Vs

Cs1

J1

Cs1

J5 Cb

Ca Vs

Vs

Vs

J2

J9

Cg1

Cn1

J6

Cn1

Cg1

n1

n3 J10 Cg3 n5 J11 Vs Cs2

J3

Cg4

J12

J7

n6

Cn2

J4 Cg2

Cn2

J8 Cg2

J13 n2

Cn3

Cn3

n4

J14

Figure 3.5: Original Conservative Join Circuit

Conservative Join Circuit Behaviour The circuit functions thus: When the inputs, Va and Vb receive tokens respectively, then electrons tunnel through the tunnel junctions J1 - J2 and J5 - J6, thereby leaving positive charges on nodes n1 and n3, respectively. Hence, when nodes n1 and n3 have simultaneously gotten a charge, then an electron tunnels from node n5 into the source through tunnel junctions J9 and J10. Afterwards, an electron tunnels from nodes n6 to n5 resulting from the SET transistor J11 - J12, which acts as a buffer and separates the influence of the input gate capacitor, Cn1 and the driving gate capacitor, Cn2. However, the charge on node n6 causes the charge on node n1 to be transferred

3.2. ORIGINAL CONSERVATIVE JOIN CIRCUIT

Capacitance(s) Ca, Cb Cs1, Cn3 Cn1 Cn2 Cg2 Cg3 C1, C3, C5, C7, C11, Cs1, Cg1, Cg4 C9, C14 C2, C4, C6, C8, C10, C12, C13

27

Value(aF) 1 0.5 0.25 0.3 11.5 10.5 10 5 0.01

Table 3.2: Original CJoin circuit parameters

into node n2 through J3 and J4, again the charge on node n3 to be transferred into node n4 through J7 and J8. The output nodes are nodes n2 and n4, therefore the input tokens represented as positive charges are thus transferred to the output node. Moreover, to bring the circuit back to a neutral or reusable state, the charge remaining on node n6 has to be removed or neutralized. This is realized by connecting node n6 to the ground through a reversed transistor structure, J14 - J13. Hence, if there is a positive charge residing on node n6 and the charges on node n1 and n3 become zero causing an electron tunneling from ground into node n6, therefore resetting the circuit or neutralizing the circuit. Again, as soon as the output charges on nodes n2 and n4 are consumed, then the circuit is ready to accept new input tokens. Derivation CJoin Circuit Parameters The CJoin circuit parameters were taken from the non-inverting buffer introduced in [16] and then adjusted to deal with the thermal effects. The CJoin exhibits a deterministic response, hence it has to be designed in such a way that the thermal energy has little or no effect on its behaviour. Circuit Parameters The circuit parameter of the Original Conservative Join design is summarized in Table 3.2. Simulation Results The simulation result is depicted in the Figure 3.6. When both inputs, Va and Vb receive an input token, that is, not when only one of them receives an input token, charges appear on the output nodes n2 and n4 only.

28

CHAPTER 3. SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Original Conservative Join simulation result 0.02 mV

Va 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

Vb 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n2 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n4 0 0

0.2

0.4

0.6

0.8

1

time

Figure 3.6: Original conservative Join simulation result

3.3

Implementable Building Block for CJOIN

In the previous section, we correctly reviewed the previous research on the Original Conservative Join functionality, which has two major limitations towards industrial implemenation, first it had long diagonal wires that appear on the design literally, thereby causing routing problem, second the circuit parameters fell short of the industrial standard. In this section we investigate the possibility of eliminating the long diagonal wires, and possibility of realizing industrially implementable circuit parameters. We then have redesigned the Conservative Join and verify same by means of simulation.

3.3.1

The Redesigned CJOIN Circuit

The previous design of Conservative Join circuitry had some challenges that limit it’s realization, though the functionality is as required. First, its unrealistic nature is induced by the long diagonal wires required for the Cn3 capacitors, which are creating a routing problem for the implementation. Second, it falls short of the industial standard of the parameters of the tunnel junction capacitances. It has tunnel junction

3.3. IMPLEMENTABLE BUILDING BLOCK FOR CJOIN

29

capacitance of 0.01aF for C2, C4, C6, C8, C10, C12, and C13 and this values are too small to be industrially realized utilizing current manufacturing techniques. As a result of these challenges, we have proposed a new topology for the Conservative Join, hence The Redesigned CJOIN, and this depicted in the later section. It can be observed that the diagonal wires present in the previous design of the Conservative Join have been eliminated. Again, we will observe later that the tunnel junction capacitance of 0.01aF which fall below the industrial realization in the previous research work has been improved, then in the new topology we have have choosen a new value of 0.1aF for these capacitances and these values can be implemented industrially utilizing current manufacturing methods. Moreover, we have verified the new proposed topology through simulation done using SIMON simulator [7]. The ReDesCJoin’s Functional Behaviour The Redesigned Conservative Join, or ReDesCJoin has the same functional behaviour as the original Conservative Join described in the section above. It sill has two input wires and two output wires. As with the original design, signals may fluctuate on the input wires of a ReDesCJoin, but once processed by the ReDesCJoin, they will be placed on the output wires from where there is no going back, even though fluctuations on the output wires are allowed. When connecting ReDesCJoins to each other, it should be ensured that input terminals face output terminals. ReDesCJoin SET-based Circuit Topology The design of the ReDesCJoin is still based on the non-inverting buffer in [16]. Such that when signals arrive at the inputs, Va and Vb at the same time, then the circuit draws a positive charge from the source placing it on the output of the buffer structure. This output drives the signals residing at the input to the output and when this occurs the positive charge is grounded. The circuit is made up of fourteen(14) tunnel junctions and seventeen(17) capacitors as the original Conservative Join circuitry. The SET circuit topology that implements the ReDesCJoin is depicted in the Figure 3.5. Redesigned Conservative Join Circuit Behaviour The circuit operates as follows: When inputs Va and Vb go high, an electron tunnels through the junctions J1 - J2 and J5 - J6 leaving positive charges on nodes n1 and n3 respectively. When n1 and n3 simultaneously have a positive charge, an electron tunnels from n5 into the source through tunnel junction J9 and J10. Subsequently, an electron tunnels from n6 to n5 due to the SET transistor J11 - J12, which acts as a buffer and separates the influences of the input Cn1 gate capacitors and Cn2 driving gate capacitors. At this point, the positive charge on n6, causes the positive charge on n1 to be transferred into n2 through J3 and J4, and the positive charge on n3 to be transferred into n4 through J7 and J8.Nodes n2 and n4 are the output nodes of the circuit. However, to restore the circuit back to a neutral state, the charge remaining on n6 has to be removed. This is realized by connecting n6 to ground through a reversed

30

CHAPTER 3. SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Vs

Vs

Cs1

J1

Cs1

J5 Cb

Ca Vs

Vs

Vs

J2 Cg1

J9 Cn1

Cn1

J6 Cg1

n1

n3 J10 Cg3 n5 J11 Vs Cs2

J3

Cg4

J12

J7

n6

Cn2

J4 Cg2

Cn2

J8 Cg2

J13 n2

Cn3

Cn3

n4

J14

Figure 3.7: ReDesigned Conservative Join Circuit transistor structure, J14 - J13. This happens only if there is a positive charge residing on n6 and the output charges on nodes n2 and n4 are also positive (set to logic ”1”), case in which an electron tunnels from the ground into n6, resetting the circuit. Hence, the circuit is ready to accept new input tokens when the output charges have been consumed. Derivation of ReDesCJoin Circuit Parameters The Redesigned CJoin circuit parameters were taken from the single electron tunneling delay insensitive and fluctuation based computation paradigms and circuits in [27]. Then, these parameters were adjusted to ensure that the proposed ciruit meets with the previous design functionality and again, to deal with the thermal effects. The Redesigned CJoin exhibits a deterministic response, hence it has to be designed in such a way that the thermal energy has little or no effect on its behaviour. Circuit Parameters The circuit parameter of the Redesigned CJoin design is summarized in Table

3.4. CONCLUSION

31

Capacitance(s) Ca, Cb Cs2 Cn1, Cn2, Cn3 Cg2, Cg3 Cg4 C1, C3, C5, C7, C11, Cs1, Cg1 C9, C14 C2, C4, C6, C8, C10, C12, C13

Value(aF) 1 0.5 0.3 10.5 11 10 5 0.1

Table 3.3: Redesigned CJoin circuit parameters 3.3. Simulation Results The simulation result is depicted in the Figure 3.8. When both inputs, Va and Vb receive an input token, that is not when only one of them receives an input token. Then charges appear on the output nodes n2 and n4 only.

3.3.2

Discussion

We have demonstrated that the original Conservative Join, CJoin for short, can be redesigned in the Single Electron Tunneling (SET) Technology. The long diagonal wires that have been a challenge towards industrial realization, thereby leading to routing problems have been eliminated. The tunnel junction circuit parameters that have fell short of the industrial standards by a factor of O(0.01aF) have been upgraded to a factor of O(0.1aF) which is the expected industrial standard. The redesigned CJoin functions at 1K temperature as the previous design. The simulation results have shown that the redesigned CJoin has maintained the same functionality as the previous CJoin design. The next challenge facing the redesigned CJoin, is it’s coexitences with the second Brownian circuits, which is Hub, the fluctuation based building block. Again another challenge facing the redesigned CJoin is whether it can be utilized in a complex circuitry, to do logic and arithmetic computations. These will form our next research questions, which we will endeavour to answer in the next chapter.

3.4

Conclusion

In this chapter we have reviewed the previous research on the Brownian circuits building blocks, that is, the Hub and the Conservative Join. We propose a new design for the Conservative Join, which we call redesigned CJoin. We verified the redesigned CJoin through simulations.

32

CHAPTER 3. SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Redesign Conservative Join simulation result 0.02 mV

Va 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

Vb 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n2 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n4 0 0

0.2

0.4

0.6

0.8

time

Figure 3.8: ReDesigned Conservative Join circuit simulation results

1

Networks of SET Based Brownian Circuit Building Blocks

4

In this chapter we present Networks of SET Based Brownian circuit building blocks. In section 4.1 we present an example network of one redesigned CJoin and two Hubs. In section 4.2 we present a network of two redesigned CJoin and three Hubs. In section 4.3 we present a network of two-by-two CJoin. In section 4.4 we present a network of two-by-two CJoin Based NAND gate. In section 4.5 we present a network of two-by-two CJoin based NOR gate. In section 4.6 we present a network of two-by-two CJoin based Half-Adder. In section 4.7 we present a network of Static Buffered Half-Adder Based computation. In section 4.8 we discuss the networks of SET Based Brownian circuit Building blocks. We then verify all these networks of SET Based Brownian circuit building blocks by means of simulations. Finally, in section 4.9 we conclude the chapter with an overview.

4.1

One Redesigned CJoin and Two Hubs

In Figure 4.1 depicts the network example of one Redesigned CJoin and two Hubs. Hence, in this section, we are going to investigate the cascading of one redesigned Conservative Join and two Hubs. As already mentioned, random fluctuation search plays an important role in the design of one redesigned CJoin and two Hubs. In Figure 4.1, first, also, the token at input A can’t be ”aware”, either the Hub or ReDesCJoin is ”aware” of whether the other required input token D to the cascaded network will be recieved, hence this results in the need to check the possibilities. More so, since the input A will be fluctuating between the both sides of Hubs, this will only be processed by only one CJoin, that is, if it has a second input token recieved or available at the ReDesCJoin. In other words, the two input tokens to the network, search for one another with respect to Brownian process, and when they happen to be at the input terminals of one and the same CJoin at a certain time, then the CJoin will operate on them. Otherwise, if the two input tokens fail to find one another at a CJoin, then no operations by the CJoin will take place. From the foregoing, the two Brownian circuit building blocks function as expected at the same temperature that is 1K. However, merely connecting them together creates an undesired effect in the circuitry (i.e crosstalk), hence affecting its functionality. In order to maintain the Brownian process in the Hub, the circuit parameters of the Hub have to be adjusted. The adjusted circuit parameters are stated in Table 4.1. This is needed to balance out the extra capacitance n1, the Hub circuitry has added on the network of the two Hub and one ReDesCJoin, as a result of this extra capacitance from being connected to the redesigned CJoin circuit. However, the circuit parameters of the 33

34 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

E

B

C

D

A

F

Figure 4.1: Network of Two Hubs and One ReDesigned CJoin Capacitance(s) C1, C3, C5 C2, C4, C6 Cs1, Cg Cs2, Cs3

Value(aF) 10 0.025 10 1

Table 4.1: Adjusted Hub circuit parameters redesigned CJoin remain unchanged. An instance to demonstrate that these building blocks can be integrated into one functional circuit block is depicted with two Hubs and one redesigned CJoin, this is shown in Figure 4.1. Hence, with one redesigned CJoin cascaded to two Hubs. Network Example Operation To demonstrate that this building blocks can function as one circuitry in a network, when there is no token at the inputs of the Hub connected to the redesigned CJoin, we observed through simulation that the latter remains stable, that is, without firing. Conversely, as soon as there are tokens at the inputs of the Hub, that is, depending on the arrival times of the inputs, then the redesigned CJoin will fire that is consuming the input tokens, therefore exhibiting its synchronisation behaviour on the input tokens. More so, if there is only one input token at input of one Hub and there is none at the other Hub, this implies that the redesigned CJoin should not fire and vice versa. Simulation Results The results of the simulation can be seen in Figures 4.2 and 4.3 below.

4.2. TWO REDESIGNED CJOIN AND THREE HUBS

35

One Redesigned CJoin and Two Hubs Network example 0.02 mV

Va 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

Vb 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

B 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

C 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.2: Network of 2 Hubs and 1 Redesigned CJoin simulation result The continuation of the simulation results of the cascading of two Hubs and one re-designed Conservative Join instances

4.2

Two Redesigned CJoin and Three Hubs

At this point, we will extend the network to three Hubs and two Redesigned Conservative Joins. The basic idea is to investigating the coexistence of these Building blocks, keeping in mind that we are working towards utilizing them in a more complex circuitry for logic and arithmetic computations. From the previous explanation, the two building blocks functions as expected, though for the network of two redesigned CJoin and three Hubs to function as a unit, thereby maintaining the random fluctuation functionality of the Hub. However, to realize this, the parameters of the Hub have to be tuned. The tuned parameters of the Hub are tabulated in Table 4.2 below.

36 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS One Redesigned CJoin and Two Hubs Network example continues 2e-19

C

n2

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

n4

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.3: Network of 2 Hubs and 1 Redesigned CJoin Capacitance(s) C1, C3, C5 C2, C4, C6 Cs1, Cg Cs2, Cs3

Value(aF) 10 0.065 10 1

Table 4.2: Adjusted Hub circuit parameters for 2 RedesCJoin and 3 Hubs

Functional Operation of the Network In Figure 4.4, we will see the network connection of two Redesigned CJoin and three Hubs. They are connected consecutively as follows, from the Figure, starting from the leftmost part, the Hub with wires labelled A and B, the B wire is connected to the input of the ReDesCJoin, which has output E and F respectively, then the second input to the ReDesCJoin comes from the central Hub which is connected to the both ReDesCJoin one on the left with output E and F, and the other on the right with output G and H. These connections from the central Hub serves as inputs to the both ReDesCJoin as earlier described. That is, the central Hub with input Va given the first input connection wire to the ReDesCJoin with output G and H. Then the second input to the ReDesCJoin with output G and H comes from the Hub at the rightmost part of the Figure with label C and D in which wire with C label on it is connected to the input of the ReDesCJoin with output G and H respectively. It is comprised of five (5) building blocks of two basic Brownian circuit blocks. This is because, the input to the Redesigned Conservative Join comes from the Hub circuitry, hence the Hub is fluctuation based circuit while Redesigned CJoin is determinstic as discussed earlier. The Network operates as follows: Having established that token to the Network sources from the Hub, then when all tokens are present on all the Hubs, it is a matter of

4.2. TWO REDESIGNED CJOIN AND THREE HUBS

37

probability as to whether it is the Redesigned CJoin with output E and F that fires or the other ReDesCJoin with output G and H that fires. Though, this firing of the CJoin takes the concept of Brownian search. However, the common token being the central token is consumed by the firing CJoin, that is, either the ReDesCJoin with output E and F or ReDesCJoin with output G and H, this means that if the ReDesCJoin with output E and F fires, it implies that the tokens will be placed at the output E and F respectively which may fluctuate at the output, hence leaving the non-firing Redesigned CJoin with output G and H only with one token placed at either of wires of the rightmost Hub, or simply put that the non-firing CJoin is not matched by a second token. Again, the same thing is applicable if the ReDesCJoin with output G and H is the firing ReDesCJoin. Network Circuit Symbol

E

G

B

C

A

D F

Va

H

Figure 4.4: Network of Three Hubs and Two ReDesigned CJoin Simulation Result The Cascaded Network of three Hubs and two ReDesigned CJoin has been verified through simulation, hence a number of simulations were done using different seed of random generators and the results of two of these simulations are depicted in the Figures 4.5 and 4.6 respectively. However, in the two simulations which results is zero (0), are left out. The charge distribution on A and B with respect to the left Hub and charge distribution on C and D with respect to the right Hub are depicted on the Figure 4.5 and 4.6 respectively. More so, the central Hub is supplied token at a zero time, then the redesigned CJoin with output G and H fires and the charges are trapped at its output and this is depicted in Figures 4.5 and 4.6 respectively. Again, the next figure depicts a similar behaviour in the second simulation, except that at this point the Redesigned CJoin with outputs E and F fires, thereby trapping the charges at its respective outputs and this is depicted in Figures 4.7 and 4.8 respectively.

38 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Two Redesigned CJoin and Three Hubs Network example 0.02 mV

Va 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

A 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

B 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

C 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.5: Network of 3 Hubs and 2 Redesigned CJoin simulation results

Two Redesigned CJoin and Three Hubs Network example continues 2e-19

C

D

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

G

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

H

0 0

0.2

0.4

0.6

0.8

time

Figure 4.6: Network of 3 Hubs and 2 Redesigned CJoin simulation results

1

4.3. TWO-BY-TWO CJOIN

39

Two Redesigned CJoin and Three Hubs Network example result 2 0.02 mV

Va 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

A 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

B 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

C 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.7: Network of 3 Hubs and 2 Redesigned CJoin simulation results

4.3

Two-By-Two CJoin

In Figure 4.9 depicts the network of Two-by-two Redesigned Conservative Join evolved from the design based on the n-by-m CJoin. This is because the consequence of the Two-by-two Redesigned Conservative Join is observed in a more efficient and straightforward designs. However, the n-by-m CJoin can be formed as an array of Conservative Join, CJoin modules that is with n rows and m columns. The Two-by-Two ReDesCJoin circuit design is comprised of four (4) ReDesCJoins, that is, ReCJ1 , ReCJ2 , ReCJ3 , and ReCJ4 plus four (4) Hubs as shown in Figure 4.9. The Two-by-Two ReDesCJoin is in array form, that is, it forms rows and columns of two ReDesCJoin and one Hub respectively. This means that in the first row, if the input A1 to the Hub is set to ”High”, that is, logic 1 or voltage 0.016mV and the second input on the column part,

40 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Two Redesigned CJoin and Three Hubs Network example result 2 continues 2e-19

C

D

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

E

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

F

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.8: Network of 3 Hubs and 2 Redesigned CJoin simulation results

that is input B1 to the Hub is set to ”High”, that is, logic 1 or voltage 0.016mV, then these inputs through the two Hubs, that is, the Hub in row part and the other Hub in the column will through Brownian search scheme look for a matching token, in this instance, the matching token will cause the ReDesCJoin represented by ReCJ1 to fire, thereby causing the tokens to be placed at the output of ReCJ1 , where it may further fluctuate. Similarly, this is also applicable in the instances of ReCJ2 , if inputs A1 and B0 to the Hubs in the row and column respectively are set to ”High” or 1. The same idea goes for ReCJ3 and ReCJ4 if it’s corresponding inputs to the Hub are set to ”High” or 1. Moreover, each row contains CJoin modules and m - 1 Hubs, hence Hubs allow a token to conduct Brownian search in the row of m CJoins. This is analogous to each column containing n - 1 Hubs for searching in the column of n CJoins. However, this results in a total of n(m - 1)+(n - 1)m = 2nm - n - m Hubs used in the n-by-m CJoin. The primary idea of these designs is to use the CJoin in an n-by-m CJoin as min-terms that is as products of a set of variables in a canonical form in a Boolean expression and to utilize the Hubs as max-terms that is for summing the min-terms into desired results. Functional Operation of Two-By-Two CJoin The 2-by-2 CJoin operates thus: when the two-by-two CJoin receives one token from the input wire in the first row of the Hub and one token from the input wire at the right column of the Hub in Figure 4.9, then the n-by-m CJoin directs the tokens through the Brownian search process to the redesigned Conservative Join in the first row and the right column, which will consume or absorb these tokens, thereby producing one token at each of its two corresponding output wires. More so, fluctuation of signals take place internally within n-by-m CJoin, where all wires are bidirectional. The operation of two-by-two CJoin has formed the basis upon which all other circuits evolved, as we will see subsequently in this thesis work that two-by-two CJoin has been versatile in logic

4.3. TWO-BY-TWO CJOIN

41

and arithmetic computation. An example of arithmetic operation based on two-by-two CJoin are NAND gate, NOR gate and HALF-ADDER, we will discuss the latter in detail in the subsequent sections. Two-by-Two CJoin Circuit Design The Two-by-Two CJoin Circuit Designed is depicted in Figure 4.9. B1

B0

A1

ReCJ_2

H

ReCJ_1

H

H

ReCJ_3

H

ReCJ_4

A0

Figure 4.9: Two-By-Two CJoin Circuit Design Two-by-Two CJoin Circuit Behaviour From the previous explanation on the functional operation of the Two-by-two CJoin, we will now explain further with the Figure 4.3. From the figure, ReCJ1 to ReCJ4 represent redesigned conservative Join one to redesigned conservative Join four while H represent the Hub. And the wires with the input A1 or A0 and B1 or B0 represent the signal. As the name implies two-by-two CJoin meaning two-by-two matrix or two-dimensional array, with reference to the diagram, each row and column has two CJoin and one Hub respectively. And the number of Hub per row or column can be deduced from this formulae, 2nm - n - m = number of Hubs per row or column. However, when the tokens at the input A1 and B1 is high or ”1” while the tokens on input A0 and B0 is low or ”0”, then through the Brownian search of the tokens, the redesigned CJoin one, ReCJ1 fires while the remaining three Redesigned CJoin did

42 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Capacitance(s) C1, C3, C5 C4, C6 C2 Cs1, Cg Cs2, Cs3

Value(aF) 10 0.05 0.036 10 1

Table 4.3: Adjusted Hub circuit parameters on the row of RedesCJoin Capacitance(s) C1, C3, C5 C4, C6 C2 Cs1, Cg Cs2, Cs3

Value(aF) 10 0.05 0.035 10 1

Table 4.4: Adjusted Hub circuit parameters on the column of RedesCJoin

not fire as a result of this, they did not get the right match so as to fire. This is also applicable when the tokens on the input A1 and B0 are high or ”1”, then ReCJ2 fires while the other three ReCJ do not. When the token at input B0 and A0 is high or ”1”, then ReCJ3 fires leaving the other three ReCJ not firing. The same idea is applied to the token at input A0 and B1, when high or ON or ”1”, the last ReCJ4 fires while the other three Redesigned CJoin did not fire. The latter has been verified through simulation. Then a number of simulations were done using different seed of random generators. Two-by-Two CJoin Circuit Parameters To achieve this circuit parameters, the parameters of the Hub has to be adjusted. Here, we have two adjusted Hub parameters, the Hub parameter on the row of CJoin is adjusted followed by the Hub parameter on the column of CJoin. The two Hub adjusted parameters are tabulated on Tables 4.3 and 4.4. Simulation Result The simulation results for the Two-by-Two Conservative Join are presented in Figures 4.10, 4.11, 4.12, and 4.13 and they indicate that Two-by-Two Conservative Join functions correctly. The Two-by-Two Conservative Join requires 168 circuit elements. Next, is the second simulation result of the 2-by-2 redesigned conservative join, ReDesCJoin is depicted in Figure 4.11.

4.4. TWO-BY-TWO CJOIN BASED NAND GATE

43

Two-by-Two ReDesCJoin simulation result 1 0.02 mV

A1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

B1 0 0

0.2

0.4

0.6

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1

time 2e-19 C

n1 0 0

0.2

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0.6

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1

time 2e-19 C

n2 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.10: Network of 2-by-2 Redesigned CJoin first simulation results Next, is the third simulation result of the 2-by-2 redesigned conservative join, ReDesCJoin is depicted in Figure 4.12. Next, is the fourth simulation result of the 2-by-2 redesigned conservative join, ReDesCJoin is depicted in Figure 4.13.

4.4

Two-By-Two CJoin Based NAND gate

In the previous section we discussed the versatility of Two-by-Two Conservative Join whereby useful circuitry as NAND gate can be constructed out of it. As discussed previously, the basic concept behind this design is to utilize Two-by-Two CJoin as min-terms in a standard form in a Boolean expression and to utilize Hub as a max-terms in summing the min-terms into desired results. However, Two-by-Two Conservative Join is dual-rail thus each signal is represented by two lines. That is A = (A1, A0), B

44 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Two-by-Two ReDesCJoin simulation result 2 0.02 mV

A1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

B0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n3 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n4 0 0

0.2

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0.6

0.8

1

time

Figure 4.11: Network of 2-by-2 Redesigned CJoin second simulation results = (B1, B0). This is exemplified as follows. When A = 0, this means that A1 = 0 and A0 = 1 and when A = 1, then A1 = 1 and A0 = 0. NAND gates are one of the two basic logic gates along with NOR gates from which any other logic gates can be built. As a consequence of this characteristic, NAND and NOR gates are sometimes called universal gates. Due to this we want to investigate NAND gate Based Two-by-Two CJoin. NAND gate Based Two-by-Two CJoin with respect to its name is designed from 2-by-2 CJoin and 2 Hubs that is a total of 4 CJoins and 6 Hubs. Next we will discuss the functional behaviour of NAND gate Based Two-by-Two CJoin. Functional Behaviour of NAND gate Based Two-by-Two CJoin In the previous explanation of the circuit behaviour of Two-by-Two CJoin, in which the inputs to the design is received through the Hub situated in either row-wise or column-wise of this design, in which the received tokens can carry out Brownian search to obtain the desired result or functionality. The only difference in this design is the addition two Hubs which is used in summing the min-terms of Two-by-Two CJoin into their desired results.

4.4. TWO-BY-TWO CJOIN BASED NAND GATE

45

Two-by-Two ReDesCJoin simulation result 3 0.02 mV

A0 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

B0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n5 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n6 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.12: Network of 2-by-2 Redesigned CJoin third simulation results a1 0 0 1 1

a0 1 1 0 0

b1 0 1 0 1

b0 1 0 1 0

c1 1 1 1 0

c0 0 0 0 1

Table 4.5: NAND gate Based 2-by-2 CJoin truth table

NAND gate Based Two-by-Two CJoin Circuit Design Figure 4.4 and table 4.5 depicts the organization of NAND gate Based Two-byTwo CJoin design and its truth table respectively.

46 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Two-by-Two ReDesCJoin simulation result 4 0.02 mV

A0 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

B1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

n7 0 0

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1

time 2e-19 C

n8 0 0

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1

time

Figure 4.13: Network of 2-by-2 Redesigned CJoin fourth simulation results Capacitance(s) C3, C5 C1, C4, C6 C2 Cs1, Cg Cs2, Cs3a Cs3b

Value(aF) 0.05 10 0.036 10 0.5 0.42

Table 4.6: First adjusted Hub circuit parameters for NAND gate Based 2-by-2 CJoin

Two-by-Two CJoin Based NAND gate Circuit Parameters More so, to realize this, the parameters of the additional two Hubs have to be adjusted. Here, we have two adjusted Hub parameters, the first added Hub circuitry to the 2-by-2 CJoin is adjusted followed by the second Hub circuitry to the 2-by-2 CJoin, then the two Hub adjusted parameters are tabulated on tables 4.6 and 4.7 respectively.

4.4. TWO-BY-TWO CJOIN BASED NAND GATE

47

B1

B0

C0 A1

ReCJ2

H

H

ReCJ1

H

H

H C1

ReCJ3

H

ReCJ4

A0

Figure 4.14: NAND gate Based Two-By-Two CJoin Capacitance(s) C3, C5 C1, C4, C6 C2 Cs1, Cg Cs2, Cs3a Cs3b

Value(aF) 0.05 10 0.036 10 0.5 0.6

Table 4.7: Second adjusted Hub circuit parameters for NAND gate Based 2-by-2 CJoin

Simulation Results The simulation results for the NAND gate Based Two-by-Two Conservative Join are presented in Figures 4.15, 4.16, 4.17, 4.18, 4.19, 4.20, 4.21, and 4.22 respectively. And these results indicate that NAND gate Based Two-by-Two Conservative Join functions correctly. The NAND gate Based Two-by-Two Conservative Join requires 194 circuit elements.

48 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS First Input of NAND gate truth table 0.01 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

a0 0 0

0.2

0.4

0.6

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1

time 0.01 mV

b1 0 0

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0.4

0.6

0.8

1

time 0.02 mV

b0 0 0

0.2

0.4

0.6

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1

time

Figure 4.15: First Input of NAND gate First Output of NAND gate truth table 2e-19

C

c1

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.16: First Output of NAND gate

Next, is the third input and output simulation result of Two-by-Two Based NAND gate in Figure 4.19, 4.20.

4.4. TWO-BY-TWO CJOIN BASED NAND GATE

49

Second Input of NAND gate truth table 0.01 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

a0 0 0

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1

time 0.02 mV

b1 0 0

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0.6

0.8

1

time 0.01 mV

b0 0 0

0.2

0.4

0.6

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1

time

Figure 4.17: Second Input of NAND gate

Second Output of NAND gate truth table 2e-19

C

c1

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.18: Second Output of NAND gate

Next, is the Fourth input and output simulation result of Two-by-Two Based NAND gate in Figure 4.21, and 4.22.

50 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Third Input of NAND gate truth table 0.02 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

a0 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.19: Third Input of NAND gate Third Output of NAND gate truth table 2e-19

C

c1

0 0

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0.6

0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.20: Third Output of NAND gate

4.5

Two-By-Two CJoin Based NOR gate

In this section, we are going to further investigate the versatility of 2-by-2 Conservative Join in designing of a NOR gate Based Two-by-Two CJoin. This design has the same number of components when compared with NAND gate Based Two-by-Two CJoin. Hence, one 2-by-2 CJoin and 2 Hubs. The difference with NAND gate Based 2-by-2 CJoin is in the configuration of the additional 2 Hubs to the 2-by-2 CJoin network and the desired behaviour we want to see at the output through the truth table. Again, it uses the basic concept of 2-by-2 CJoin functioning as a min-term in a standard form of

4.5. TWO-BY-TWO CJOIN BASED NOR GATE

51

Fourth Input of NAND gate truth table 0.02 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

a0 0 0

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1

time 0.02 mV

b1 0 0

0.2

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1

time 0.01 mV

b0 0 0

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0.4

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1

time

Figure 4.21: Fourth Input of NAND gate Fourth Output of NAND gate truth table 2e-19

C

c1

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.22: Fourth Output of NAND gate

a Boolean expression while the 2 Hubs function in summation of the min-term to the desired results. It equally utilizes dual-rail encoding in which one signal is represented with two signals, for example A = 0 meaning A1 = 0 and A0 = 1 and vice versa. Next, we will discuss the functional behaviour of Two-by-Two CJoin Based NOR gate. Functional Behaviour of Two-by-Two CJoin Based NOR gate The functional behaviour of the NOR gate is similar to that of the NAND gate,

52 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS this is seen in either of them utilizing Brownian search concept based on the fluctuation circuitry of the Hub. Moreover, the inputs to the Two-by-Two CJoin Based NOR gate is obtained through the Hubs, that is, interleaved between the two CJoins either row-wise or column-wise. Again, when there is a search match of the tokens in the circuitry, this will lead to the affected CJoin circuit to firing, thereby affecting the added Hubs to consuming the resulting output token to the desired result of the design. Two-by-Two CJoin Based NOR gate Circuit Design Figure 4.23 and Table 4.8 depicts the organization of NOR gate Based Two-byTwo CJoin design and its truth table respectively. B1

B0

A1

ReCJ2

H

H

ReCJ1

H

H

H

C0

ReCJ3

H

ReCJ4

A0

C1

Figure 4.23: Two-By-Two CJoin Based NOR gate

Two-by-Two CJoin Based NOR gate Circuit Parameters To realize the circuit parameter of the 2-by-2 CJoin Based NOR gate, the parameters of the additional two Hubs have to be adjusted. Here, we have two adjusted Hub parameters, the first added Hub circuitry to the 2-by-2 CJoin is adjusted followed by the second Hub circuitry to the 2-by-2 CJoin, then the two Hub adjusted parameters are tabulated on tables 4.9 and 4.10 respectively:

4.5. TWO-BY-TWO CJOIN BASED NOR GATE

a1 0 0 1 1

a0 1 1 0 0

b1 0 1 0 1

b0 1 0 1 0

c1 1 0 0 0

53

c0 0 1 1 1

Table 4.8: NOR gate Based 2-by-2 CJoin truth table Capacitance(s) C2, C3, C5 C1, C4, C6 Cs3a Cs1, Cg Cs2 Cs3b

Value(aF) 0.05 10 0.65 10 0.5 0.8

Table 4.9: First adjusted Hub circuit parameters for NOR gate Based 2-by-2 CJoin

Simulation Results The simulation results for the NOR gate Based Two-by-Two Conservative Join are presented in Figures 4.24, 4.25, 4.26, 4.27, 4.28, 4.29, 4.30, and 4.31 respectively. And these results indicate that NOR gate Based Two-by-Two Conservative Join functions correctly. The NOR gate Based Two-by-Two Conservative Join requires 194 circuit elements as NAND gate Based Two-by-Two CJoin. Next, we will investigate Two-by-Two CJoin Based HALF-ADDER.

Capacitance(s) C3, C5 C1, C4, C6 C2 Cs1, Cg Cs2 Cs3a Cs3b

Value(aF) 0.05 10 0.04 10 0.6 0.55 0.65

Table 4.10: Second adjusted Hub circuit parameters for NOR gate Based 2-by-2 CJoin

54 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS First Input of NOR gate truth table 0.01 mV

a1 0 0

0.2

0.4

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1

time 0.02 mV

a0 0 0

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1

time 0.01 mV

b1 0 0

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0.6

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1

time 0.02 mV

b0 0 0

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1

time

Figure 4.24: First Input of NOR gate First Output of NOR gate truth table 2e-19

C

c1

0 0

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1

time 2e-19

C

c0

0 0

0.2

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1

time

Figure 4.25: First Output of NOR gate

Next, is the input of Two-by-Two CJoin Based NOR gate simulation result is

4.5. TWO-BY-TWO CJOIN BASED NOR GATE

55

Second Input of NOR gate truth table 0.01 mV

a1 0 0

0.2

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1

time 0.02 mV

a0 0 0

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1

time 0.02 mV

b1 0 0

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1

time 0.01 mV

b0 0 0

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1

time

Figure 4.26: Second Input of NOR gate Second Output of NOR gate truth table 2e-19

C

c1

0 0

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0.6

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1

time 2e-19

C

c0

0 0

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1

time

Figure 4.27: Second Output of NOR gate depicted in the Figure 4.28.

Next, is the output of Two-by-Two CJoin Based NOR gate simulation result is depicted in the Figure 4.29.

56 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Third Input of NOR gate truth table 0.02 mV

a1 0 0

0.2

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1

time 0.01 mV

a0 0 0

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1

time 0.01 mV

b1 0 0

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1

time 0.02 mV

b0 0 0

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1

time

Figure 4.28: Third Input of NOR gate

Third Output of NOR gate truth table 2e-19

C

c1

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.29: Third Output of NOR gate

Next, depicts the fourth Input simulation results of NOR gate based 2-by-2 CJoin in Figure 4.30.

4.5. TWO-BY-TWO CJOIN BASED NOR GATE

57

Fourth Input of NOR gate truth table 0.02 mV

a1 0 0

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1

time 0.01 mV

a0 0 0

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1

time 0.02 mV

b1 0 0

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1

time 0.01 mV

b0 0 0

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1

time

Figure 4.30: Fourth Input of NOR gate

Next, depicts the fourth output simulation results of NOR gate based 2-by-2 CJoin in Figure 4.31. Fourth Output of NOR gate truth table 2e-19

C

c1

0 0

0.2

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0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6 time

Figure 4.31: Fourth Output of NOR gate

0.8

1

58 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

4.6

Two-By-Two CJoin Based HALF-ADDER

In Figure 4.32, we can observe that when adding two inputs forinstance labelled A and B, and this results in two outputs which is, sum, S and carry, C. S is the two-bit XOR of A and B, and C is the AND of A and B. Hence, a Half-adder is the addition of two one-bit numbers with two outputs S and C. In the previous sections, we have been investigating the idea behind n-by-m CJoin that is for constructing useful circuits as Half-Adder. Hence, this Half-Adder with respect to the latter caption, is made out of 2-by-2 CJoin and four Hubs or simply put four CJoins and eight Hubs. As we have explained previously, the inputs to the Half-adder is dependent on dual-rail encoding logic in which an input is represented by the 0-wire and the 1-wire at the top and a similar pair of wires at the right. These are fed to the four CJoins, and the resulting four min-terms are combined through the Hubs into an XOR of the inputs to produce the sum of the Half-Adder at the bottom and into an AND of the inputs to produce the carry at the left. Next is the functional behaviour of two-by-two CJoin Based Half-Adder. Functional Behaviour of Two-by-Two CJoin Based Half-Adder The functional behaviour of Half-Adder based 2-by-2 CJoin is dependent on the Brownian search of tokens and this is analogous to the previous explanation of the Two-by-Two CJoin. This is because the inputs to the Half-Adder circuitry is received through the fluctuation based ciruitry, Hub situated in between two CJoin that is either row-wise or column-wise as we have seen earlier. For instance, when A = 0 and B = 0, this means that A1 = 0 and A0 = 1 while B1 = 0 and B0 = 1, these inputs of A and B into the HALF-ADDER will search by means of Brownian scheme to look for the matching token search space, this results in ReDesCJoin, ReCJ3 to fire, thereby causing the output S = 0 and C = 0, implying that S1 = 0 and S0 = 1, C1 = 0 and C0 = 1 respectively. The same concept goes for the rest of the input tokens as can be seen in the truth Table 4.11. The tokens search for token matching within the circuit through the Brownian search, and once it matches, the corresponding CJoin fires. Then, the additional four Hubs function in summing the results of the min-terms into their desired outputs of either XOR or AND as the case may be. Next is the Two-by-Two CJoin Based Half-Adder circuit design. Two-by-Two CJoin Based Half-Adder Circuit Design Figure 4.6 and table 4.11 depicts the organization of Two-by-Two CJoin Based Half-Adder circuit design and its truth table respectively.

Two-by-Two CJoin Based Half-Adder Circuit Parameters

4.6. TWO-BY-TWO CJOIN BASED HALF-ADDER

59

B0

B1 INPUT A1

ReCJ2

H

ReCJ1

C1

H

H INPUT H

Carry (AND)

H

ReCJ3

C0

H

ReCJ4

H H A0 SUM (XOR)

S0

S1

Figure 4.32: Two-By-Two CJoin Based Half Adder a1 0 1 1 0

a0 1 0 0 1

b1 0 0 1 1

b0 1 1 0 0

s1 0 1 0 1

s0 1 0 1 0

c1 0 0 1 0

c0 1 1 0 1

Table 4.11: Half-Adder Based 2-by-2 CJoin truth table

To realize the 2-by-2 CJoin Based Half-Adder circuit parameters, the parameters of the additional four Hubs have to be adjusted. Here, we have four adjusted Hub parameters, the adjusted four Hub parameters are tabulated on the following tables below. For us to understand how these Hubs are cascaded in Figure 4.32 which relates to the adjusted Hub parameters. We will give the explanation with the aid of Two-by-Two CJoin Based Half Adder diagram stated above. Out of the added four Hubs to 2-by-2 CJoin, the first Hub was connected between ReCJ2 and ReCJ3 and the output of this Hub is connected between the second Hub and ReCJ4, then the third Hub is connected between ReCJ2 and ReCJ4 and producing output S0, while the fourth Hub is connected

60 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Capacitance(s) C3, C5 C1, C4, C6 Cs1, Cg Cs2, Cs3 C2

Value(aF) 0.05 10 10 0.5 0.03

Table 4.12: First adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder Capacitance(s) C3, C5 C1, C4, C6 C2 Cs1, Cg Cs2 Cs3a Cs3b

Value(aF) 0.05 10 0.03 10 0.5 0.53 0.50

Table 4.13: Second adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder between ReCJ1 and ReCJ3, then producing output S1 and C1 respectively. Then, the adjusted Hub parameters with the sequence as highlighted latter in the Tables 4.12, 4.13, 4.14 and 4.15 below. Simulation Results The simulation results for the 2-by-2 CJoin Based Half Adder are presented in Figures 4.33, 4.34, 4.35, 4.36, 4.37, 4.38, 4.39, and 4.40 respectively. And these simulation results indicate that 2-by-2 CJoin Based Half Adder functions correctly. The 2-by-2 CJoin Based Half Adder requires 220 circuit elements (that is 104 tunnel junctions and 116 capacitors). Next, we will investigate Buffered HALF-ADDER.

Capacitance(s) C3, C5 C1, C4, C6 C2, Cs3a Cs1, Cg Cs2, Cs3b

Value(aF) 0.07 10 0.55 10 0.5

Table 4.14: Third adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder

4.6. TWO-BY-TWO CJOIN BASED HALF-ADDER

Capacitance(s) C3, C5 C1, C4, C6 C2 Cs1, Cg Cs2 Cs3

61

Value(aF) 0.05 10 0.045 10 0.5 0.50

Table 4.15: Fourth adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder First Input of the truth table 0.01 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

a0 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.33: First Input of the HalfAdder

Next, is the input and output Two-by-Two CJoin Based Half Adder simulation result is depicted in the Figure 4.35, and 4.36.

Next, is the input and output Two-by-Two CJoin Based Half Adder simulation result is depicted in the Figure 4.37, and 4.38.

62 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS First Output of the truth table 2e-19 C

s1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

s0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

c1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

c0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.34: First Output of the HalfAdder Second Input of the truth table 0.02 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

a0 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b0 0 0

0.2

0.4

0.6

0.8

time

Figure 4.35: Second Input of the HalfAdder

1

4.6. TWO-BY-TWO CJOIN BASED HALF-ADDER

63

Second Output of the truth table 2e-19 C

s1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

s0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

c1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

c0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.36: Second Output of the HalfAdder Third Input of the truth table 0.02 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

a0 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

b0 0 0

0.2

0.4

0.6

0.8

time

Figure 4.37: Third Input of the HalfAdder

1

64 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS

Third Output of the truth table 2e-19 C

s1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

s0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

c1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

c0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.38: Third Output of the HalfAdder

Next, is the input and output Two-by-Two CJoin Based Half Adder simulation result is depicted in the Figure 4.39, and 4.40.

4.7

Static Buffered HALF ADDER Based Computation

In this section the static buffer version of Half Adder Based Computation previously discussed in section 4.6 is presented. Also, the buffer’s supply voltage and the output voltage change the Half Adder logic gate’s biasing as a result of a feedback effect. The static inverting buffer can also be utilized as a stand-alone inverter if desired and can be used as a building block for designing larger SEEL, Single Electron Encoded Logic circuits as discussed in [5]. Hence, when referring to a static buffered Half Adder Based 2-by-2 CJoin, we mean a Half Adder based 2-by-2 CJoin as discussed in section 4.6 augmented with the static inverting Buffer discussed in section 2.1.3 as an output buffer. Given that the buffer inverts its input, the logic function performed by the buffered

4.7. STATIC BUFFERED HALF ADDER BASED COMPUTATION

65

Fourth Input of the truth table 0.01 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

a0 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

b0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.39: Fourth Input of the HalfAdder Fourth Output of the truth table 2e-19 C

s1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

s0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

c1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

c0 0 0

0.2

0.4

0.6

0.8

time

Figure 4.40: Fourth Output of the HalfAdder

1

66 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Half Adder Based 2-by-2 CJoin is the inverse of that performed by the 2-by-2 CJoin Based Half Adder. However, when referring to a Half Adder implementing a logic function, we imply the logic function performed by the entired Buffered Half Adder(Buffer + Half Adder). In the next part we discuss the Static Buffered Half Adder circuit design. Static Buffered Half Adder Circuit Design Figure 4.7 depicts the organization of Static Buffered Half Adder circuit design. B0

B1

INPUT A1

ReCJ2

H

ReCJ1

C1

INPUT

H

H H

H

CARRY (INV−AND) ReCJ3

C0

B

H

ReCJ4

B

H H

A0 B

SUM (INV−XOR) S0

S1

Figure 4.41: Static Buffered Half Adder

Functional Behaviour of Static Buffered Half-Adder From the previous section we have seen that the output of the Two-by-Two Based Half Adder has feedback effects which is introduced by additional Hubs to the circuit, in

4.7. STATIC BUFFERED HALF ADDER BASED COMPUTATION

Capacitance(s) C1, C4 C2, C3 Cg1, Cg2 Cb1, Cb2 Cl

67

Value(aF) 0.01 0.05 0.05 2.6 8.5

Table 4.16: First adjusted Static Buffered Half Adder circuit parameters which introducing the Buffers help to eliminate these feedbacks. In Figure 4.41, we can observe that we have three added Buffers but in simulating this design we had six Buffers. This is because, each Hub is bidirectional, as we discussed earlier, meaning that the output of one Hub is more than one that is up to three. This is why we have more than three Buffers as can be seen in Figure 4.41. As previously stated on 2-by-2 CJoin functional circuit behaviour, this is based on a Brownian search. We assumed a supply voltage Vs = 16mV and that logic ’1’ is represented as 16mV. More so, we assumed that the inputs are driven by ideal voltage sources. The Static Buffered Half Adder was built and simulated and the design and simulation will be discussed in the next part. Static Buffered Half-Adder Circuit Parameters To achieve the circuit parameter of static buffered Half-Adder, then the parameters of the second, third and fourth added Hubs in the previous section plus six (6) additional static Buffers have to be adjusted. Hence, three out of the six Buffers maintain same parameters, and another two Buffers maintain the same parameters, and then the last added Buffer has a different parameter from the latter two Buffers.The difference observed in these Buffer parameters is only in its load capacitance. The parameters of the adjusted three, two and one same Buffer parameters, plus the second, third and fourth added Hub parameter in the previous section are tabulated on the following Tables 4.16, 4.17, 4.18, 4.19, 4.20, and 4.21 respectively. For us to understand how these Buffers are cascaded which relates to the adjusted Hub parameters. We will give the explanation with the aid of Static Buffered Half Adder diagram shown in Figure 4.41. For a clear understanding of the cascading made for the six added Buffers, since pictorially we can observe three added buffers with a label B in a rectangle box, now this is how it is cascaded. The Buffer at the output of the Hub linked to ReCJ2 and ReCJ4 maintains two Buffers instead of one and the same goes for the Hub linked to ReCJ1 and ReCJ3 and the Hub linked to ReCJ4 via two Hubs linked to ReCJ3 and ReCJ2. The adjusted Buffer and Hub parameters as highlighted latter in the Tables 4.16, 4.17, 4.18, 4.19, 4.20, and 4.21. Simulation Results The simulation results for the Static Buffered Half Adder are presented in Figures 4.42, 4.43, 4.44, 4.45, 4.46, 4.47, 4.48, 4.49, 4.50, 4.51, 4.52, and 4.53 respectively.

68 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Capacitance(s) C1, C4 C2, C3 Cg1, Cg2 Cb1, Cb2 Cl

Value(aF) 0.01 0.05 0.05 2.6 8.0

Table 4.17: Second adjusted Static Buffered Half Adder circuit parameters Capacitance(s) C1, C4 C2, C3 Cg1, Cg2 Cb1, Cb2 Cl

Value(aF) 0.01 0.05 0.05 2.6 9.0

Table 4.18: Third adjusted Static Buffered Half Adder circuit parameters These simulation results indicate that 2-by-2 CJoin Based Static buffered Half Adder functions correctly. The Static Buffered Half Adder requires 274 circuit elements (that is 128 tunnel junctions and 146 capacitors).

Next, is the first output of static buffered Half Adder simulation results.

Next, is the second output of static buffered Half Adder simulation results.

Capacitance(s) C3, C5 C1, C4, C6 C2 Cs1, Cg Cs2 Cs3a, Cs3b

Value(aF) 0.05 10 0.04 10 0.5 0.60

Table 4.19: Second adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder

4.7. STATIC BUFFERED HALF ADDER BASED COMPUTATION

Capacitance(s) C3, C5 C1, C4, C6 C3a Cs1, Cg Cs3b Cs2

69

Value(aF) 0.07 10 0.55 10 0.50 0.04

Table 4.20: Third adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder Capacitance(s) C3, C5 C1, C4, C6 Cs1, Cg Cs2 Cs3a Cs3b

Value(aF) 0.05 10 10 0.45 0.50 0.52

Table 4.21: Fourth adjusted Hub circuit parameters for 2-by-2 CJoin Based Half Adder First input of Static Buffered Half Adder truth table 0.01 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

a0 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b0 0 0

0.2

0.4

0.6

0.8

time

Figure 4.42: First Input of Static Buffered HalfAdder

1

70 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS First output of Static Buffered Half Adder truth table 2e-19 C

s1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

bs1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

s0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

bs0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.43: First Output of Static Buffered HalfAdder First output of Static Buffered Half Adder truth table continues 2e-19

C

c1

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

bc0

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.44: First Output of Static Buffered HalfAdder continues

Next, we will discuss the simulation results of the third input and output of the static buffered Half Adder as previously highlighted in the truth table.

4.7. STATIC BUFFERED HALF ADDER BASED COMPUTATION

71

Second input of Static Buffered Half Adder truth table 0.02 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

a0 0 0

0.2

0.4

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0.8

1

time 0.01 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.45: Second Input of Static Buffered HalfAdder Second output of Static Buffered Half Adder truth table 2e-19 C

s1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

bs1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

s0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

bs0 0 0

0.2

0.4

0.6

0.8

time

Figure 4.46: Second Output of Static Buffered HalfAdder

1

72 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Second output of Static Buffered Half Adder truth table continues 2e-19

C

c1

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

bc0

0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.47: Second Output of Static Buffered HalfAdder continues Third input of Static Buffered Half Adder truth table 0.02 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

a0 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

b0 0 0

0.2

0.4

0.6

0.8

time

Figure 4.48: Third Input of Static Buffered HalfAdder

1

4.7. STATIC BUFFERED HALF ADDER BASED COMPUTATION

73

Third output of Static Buffered Half Adder truth table 2e-19 C

s1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

bs1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

s0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

bs0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.49: Third Output of Static Buffered HalfAdder Third output of Static Buffered Half Adder truth table continues 2e-19

C

c1

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

c0

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

bc0

0 0

0.2

0.4

0.6

0.8

time

Figure 4.50: Third Output of Static Buffered HalfAdder continues

1

74 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS Fourth input of Static Buffered Half Adder truth table 0.01 mV

a1 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

a0 0 0

0.2

0.4

0.6

0.8

1

time 0.02 mV

b1 0 0

0.2

0.4

0.6

0.8

1

time 0.01 mV

b0 0 0

0.2

0.4

0.6

0.8

1

time

Figure 4.51: Fourth Input of Static Buffered HalfAdder Fourth output of Static Buffered Half Adder truth table 2e-19 C

s1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

bs1 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

s0 0 0

0.2

0.4

0.6

0.8

1

time 2e-19 C

bs0 0 0

0.2

0.4

0.6

0.8

time

Figure 4.52: Fourth Output of Static Buffered HalfAdder

1

4.8. DISCUSSION

75

Fourth output of Static Buffered Half Adder truth table continues 2e-19

C

c1

0 0

0.2

0.4

0.6

0.8

1

time 2e-19

C

c0

0 0

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1

time 2e-19

C

bc0

0 0

0.2

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0.8

1

time

Figure 4.53: Fourth Output of Static Buffered HalfAdder continues

4.8

Discussion

We have demonstrated a network of implementable redesigned Conservative Join with fluctuation based building block in Single Electron Tunneling Technology at the same temperature, i.e, 1K while maintaining the desired behaviours. We demonstrate that the network of two Hubs and one redesigned CJoin can coexist. In the simulation result, we can observe that there are fluctuations on the Hub wire B and C. The output of the network n2 and n4 at the redesigned CJoin has a time delay of approximately 0.42 seconds, that is, before the tokens synchronizes by coming out High or set to 1. We demonstrate the network of two redesign CJoin and three Hubs can coexist equally. In the simulation result, we observe that there are fluctuations at the Hubs wires, A, B, C, and D. Though, the output of the redesigned CJoin, G and H come High, that is, logic 1 after a time delay of approximately 0.50 seconds. The same thing is applicable for the output of the redesigned CJoin, E and F, however, showing the delay-insensistive nature of the operations and the robustness to errors reduce the demands on the technology, underlining the promises of the proposed avenue. We demonstrate the network of four Hubs and four redesigned CJoin, that is, 2-by-2 CJoin in SET technology that they can coexist. This 2-by-2 CJoin network operates with the concept of dual-rail logic. In the simulation results show that each output of the redesigned CJoin has a varying delay-time from the subsequent redesigned CJoin. We demonstrate again the network of 2-by-2 CJoin based NAND-gate. In the simulation results show that the output of each of the logic inputs from the truth table is correct, though we observe a time delay at some instances. We demonstrate again the network of 2-by-2 CJoin based NOR-gate. In the simulation results, we observe that the output of each of the logic inputs from the truth table is correct. Though, we observe a time delay at the output of the network. We demonstrate the network of 2-by-2 CJoin based Half-Adder, that they can coexist.

76 CHAPTER 4. NETWORKS OF SET BASED BROWNIAN CIRCUIT BUILDING BLOCKS We have seen the robustness of the network as the circuit complexity keep growing in area. The area of 2-by-2 CJoin based Half Adder is 220 circuit elements. This network operates with the concepts of dual-rail logic. In the simulation result, we observe that the output of each of the logic input of the truth table is correct, though there are some time delay at the output, hence, underscoring the key of Brownian search. The area of the network complexity keep on growing as we want the consumption of the output of the 2-by-2 CJoin based Half Adder with a buffer. The area of 2-by-2 CJoin Buffered Half Adder is 274 circuit elements implying that it is too complex. We demonstrate a static buffer with circuit parameters at 1K. We demonstrate a network of 2-by-2 CJoin static Buffered Half Adder. In the simulation results, we have shown the output of logic input of the truth table followed by inverted output coming from the static buffer. The simulation results have that it is correct. All these networks are verified by using SIMON (SIMulator Of Nanostructures)[7].

4.9

Conclusion

In this chapter we have investigated the networks of SET Based Brownian Circuit building Blocks. In order to demonstrate that these Brownian circuit building blocks can function correctly in a network structure, we implemented one redesigned CJoin and two Hubs network, two redesigned CJoin and three Hubs network, newtork of 2-by-2 CJoin, NAND-gate based 2-by-2 CJoin, NOR-gate based 2-by-2 CJoin, Network of 2-by-2 CJoin based Half-Adder and Network of static buffered Half Adder based computation. We also verified these networks via simulations.

Conclusion and Discussion 5.1

5

Summary

In this thesis the design and simulation of Single Electron Tunneling circuits for Brownian Motion Based Logic and Arithmetic Computation are addressed. The summary of the investigations and the results are stated as follows. In Chapter 2, we presented Single Electron Tunneling Technology background concepts, related work on SET, Brownian Motion circuit concepts and Dual rail coding logic. We obtained static buffer circuit parameters at 1K to enable combination with other circuits that operate at the same temperature. In Chapter 3, we reviewed SET based brownian circuit building blocks, i.e, Hub circuit and Conservative Join circuit. We then proposed the implementation of a new design for the Conservative Join, that is, Redesign CJoin. This redesign CJoin takes care of the industrial limitations of long diagonal wires and tunnel junction’s circuit parameters. In Chapter 4 we proposed the implementation of networks of SET Based Brownian circuits building blocks. We first implemented network of One redesigned CJoin and Two Hubs, followed by networks of two redesigned CJoin and three Hubs, then networks of four Hubs and four redesigned CJoin, i.e, 2-by-2 CJoin. We implemented networks of two-by-two CJoin based NAND gate and NOR gate respectively. Next we implemented networks of 2-by-2 CJoin based Half Adder for logic and arithmetic computation. We utilize the buffering scheme to consume the output of 2-by-2 CJoin based Half Adder, hence static buffered Half Adder based computation. The proposed circuits and networks were all verified by means of simulations and proved that the proposed SET circuits and networks can deliver the required functionality. Furthermore, circuits ability to exploit fluctuations offer potentials to work closer to the thermal limit than noise-suppressing techniques and as a result they can relax the limitations on the operating temperatures of nanometer scale devices toward room temperatures, however, Brownian circuits appears to be promising and implementation in SET technology proves to be more robust against effects which cause electrons to behave in a random manner.

5.2

Future Research work

• In this thesis we utilize two fluctuation based building blocks in constructing large network as 2-by-2 CJoin Based Half Adder. We suggest that these two building blocks be utilized for further logic and arithmetic computations like Full Adder, 77

78

CHAPTER 5. CONCLUSION AND DISCUSSION

counters and so on. • In this thesis we have proved the robustness of Brownian circuit in Single Electron Tunneling (SET) Technology, which lead to more complex circuit elements. We suggest an optimized design of Brownian circuit in terms of area occupied by the circuit elements for future complex design and easy controllability. • In this thesis we have observed the the power of Brownian motion to avoid deadlocks but it cost sometime to settle a circuit into its final state. We suggest speeding up Brownian circuits that may somehow limit the time-cost to which tokens undego Brownian motion searching[25]. • In [25] proposal of using ratchet has been made to speed up Brownian motion search. We suggest an efficient design of ratchet that will meet this need. • In literature, suggestion of utilizing ratchet to speed up computation may reduce Brownian search operation. We suggest that critical study of where and how to apply ratchet be carried to avoid reducing the power of Brownian motion search.

Bibliography [1] International technology roadmap for semiconductors, 2007 edition, emerging research devices, 2007, downloadable from website http://www.itrs.net/links/2007itrs/home2007.htm. [2] International technology roadmap for semiconductors, 2007 edition, executive summary, 2007, downloadable from website http://www.itrs.net/links/2007itrs/home2007.htm. [3] Single-electron transistors: Electrostatic analogs of the dc squids., vol. MAG-23, IEEE Transactions on Magnetics, March 1987. [4] Delay-insensitive systems - an overview., no. 1, Distributed Computing, 3, (1998). [5] Quantum ratchets and quantum heat pumps., no. 2, Applied Physics A: Materials Science and Processings, 75 (2002). [6] D. V. Averin. and K. K. Likharev. (eds.), A correlated transfer of single electrons and cooper pairs in systems of small tunnel junctions., vol. 30, Elsevier Science Publishers BV, 1991. [7] H. Kosina C. Wasshuber and S. Selberherr, Simon - a simulator for single-electron tunnel devices and circuits, 16 (1997), no. 9, 937–944. [8] S. D. Cotofana, C. R. Lageweg, and S. Vassiliadis, On computing addition related arithmetic operations via controlled transport of charge, proceedings of 16th IEEE Symposium on Computer Arithmetic, June 2003, pp. 245–252. [9]

, On effective computation with nanodevices: A single electron tunneling case study, Proceedings of the 2004 International Semiconductor Conference (CAS 2004), October 2004, pp. 41–50.

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[19] J. Lee and et. al., Brownian circuits - part 11: Efficient designs, (In preparation, 2008). [20] C.H. Meenderinck, Arithmetic operations in single electron tunneling technology, Master’s thesis, July 2005. [21] C.H. Meenderinck and S. D. Cotofana, Computing division using single-electron tunneling technology, IEEE Transactions on Nanotechnology (2007), 451–459. [22] G. E. Moore, Cramming more components onto integrated circuits, Electronics 38, April 1965, pp. 114–117. [23] Gordon. E. Moore, Progress in digital integrated electronics, Digest of the 1975 International Electron Devices Meeting,IEEE, 1975, p. 1113. [24] M. Akazawa N. Asahi and Y. Amemiya, Single-electron logic systems based on the binary decision diagram, IEICE Transactions on Electronics, vol. E81-C, January 1998, pp. 49–56. [25] F. Peper and et. al., Brownian circuits - part 1: Concepts and basic designs, (In preparation, 2008), 11. [26] G. Lochak. S. Diner, D. Fargue and F. Selleri., The wave-particle dualism- a tribute to louis de broglie on his 90th birthday, D. Reidel Publishing Company, 1984. [27] S. Safiruddin, Single electron tunneling based building blocks for delay insensitive circuits, Master’s thesis, June 2008, p. 93. [28] S. Safiruddin, S. D. Cotofana, and F. Peper, Single electron tunneling delay insensitive and fluctuation based computation paradigms and circuits, Proceedings of the 2008 IEEE/ACM International Symposium on Nanoscale Architectures, June 2008, pp. 69–76. [29] S. Safiruddin, S. D. Cotofana, F. Peper, and J. Lee, Building blocks for fluctuation based calculation in single electron tunneling technology, Procedeengs of the 8th IEEE Conference on Nanothechnology, August 2008. [30] T. Asai T. Yamada, M. Akazawa and Y. Amemiya, Boltzmann machine neutral network devices using single-electron tunneling, Nanotechnology,, vol. 12, 2001, pp. 60– 67.

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List of Publications 1. I. Agbo, S. Safiruddin and S. Cot¸ofan˘a, “Implementable Building Blocks for Fluctuation Based Calculation in Single Electron Tunneling Technology”, in Proceedings of the 9th IEEE Conference on Nanotechnology, Genoa, Italy July 2009, pp. 450-453.

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Curriculum Vitae

Innocent Okwudili Agbo was born in AmechiAwkunanaw in Enugu-South local government area of Enugu state, Nigeria on 11th April, 1971. From 1985 he took secondary education at the Comprehensive secondary school AkpashaAwkunanaw Enugu where he graduated in 1990. From 1993 he took bachelor education at the Enugu State university of science and technology where he graduated in 1999 with second class honours upper division in Computer Science and Engineering. From 2007 he joined the Computer Engineering laboratory at Delft University of Technology, The Netherlands for his Master education, to start his MSc graduation project he was under the supervision of associate professor Sorin Cot¸ofan˘a. During his MSc graduation project he submitted one paper for publication, which was accepted and published. His research interests include Computer arithmetic, nano electronics, logic design and computer architecture.