306
CES TRANSACTIONS ON ELECTRICAL MACHINES AND SYSTEMS, VOL. 1, NO. 3, SEPTEMBER 2017
Multilevel Current Source Converters for High Power Medium Voltage Applications Li Ding, Yujuan Lian, student member, IEEE, and Yun Wei Li, Senior member, IEEE (Invited) Abstract—In medium voltage high power applications, multi-level current source converters (CSCs) are good candidate to increase system power region, reliability, and the quality of output waveforms. Compared with widely researched voltage source multi-level converters (MLCs), the current source MLCs have the advantages of inherent short-circuit protection, high power capability and high quality of output current waveforms. The main features of MLCs include reduced harmonics, lower switching frequency and reduced current stress on each device which is a particularly important for high power application with low voltage and high current requirements. This paper conducts a general review of the current research about MLCs in higher power medium voltage application. The different types of parallel structure based MLCs and the modulation methodologies will be introduced and compared. Specifically, the circuit analysis of the common-mode (CM) loop for parallel structures will be conducted, the common-mode voltage (CMV) and circulating current suppression methods developed on the base of multilevel modulations will be addressed. Index Terms—Circulating current, common-mode voltage, current source converters, multi-level converter, high power medium voltage, parallel structure.
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I. INTRODUCTION
URRENT source converter (CSC) can provide the advantages of inherent four-quadrant operation, reliable short circuit protection, motor-friendly waveforms and voltage boosting capability. Compared with voltage source converters (VSC), the slow dynamic response of CSC restricts its applications when high dynamic response is required. But there is a large application field for high power adjustable drives such as pumps, fans, rolling mills, wind parks and energy storage systems in which fast dynamic response is not needed. Moreover, the desirable short circuit protection performance makes the wide application of CSC in flexible AC transmission system (FACTS), high-voltage direct current (HVDC) system, solar photovoltaics (PV) and data center supplies [1]-[5]. Multilevel topologies for CSCs can improve the system power region and harmonic performance, which have attracted many attentions in recent years [6]-[10]. The main advantage of multilevel topologies is to handle high operating current with low or medium current semiconductors. The emerged multilevel converters (MLCs) can be classified into three Li Ding is currently working toward the Ph. D degree in electrical power engineering in the Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada. (e-mail:
[email protected])
categories, i.e. embedded, two stage, and parallel MLCs [11]-[13]. Between them, parallel operation is a more practical structure and is easier to implement. There are mainly two types of parallel CSC topologies based on the arrangement of DC source. If each paralleled CSC module had its own DC source, it can be classified into the first type. This topology can bring independent DC links for each current source inverter (CSI) and two DC inductors (one implemented in the upper leg and one in the lower leg) are used to support the constant DC link current in each module. A DC-link current ripple reduction modulation for this direct parallel topology by proper selection of redundant switching states was introduced in [14]. On the other hand, if the paralleled CSC modules are shared with the same DC source, that results in the second type of topology, in while only the total DC current can be guaranteed. The DC current balance for each module would be a serious issue to make the system work properly. One of the major concerns in both voltage source converter (VSC) and CSC based medium voltage drives is the common-mode voltage (CMV) which is generated by the switching actions of the semiconductor devices. Such CMV can cause motor shaft voltage, bearing current and common-mode current (CMC), which are harmful for the proper operation and lifetime of the system. The relevant solutions include isolation transformer, integrated common-mode (CM) choke, which have been thoroughly discussed in [15]. Compare to the high cost of the isolation transformer and other additional components, the integrated CM choke is a practical solution. However, the size and cost of the CM choke strongly depend on the magnitude of CMV and therefore on the amplitude of CMC [16]. Therefore, it is always desirable to apply active CMV suppression method with PWM and control improvement, such that the size and cost of CM choke can be reduced. Several advanced modulation methods aimed to suppress the magnitude of CMV of CSC-fed motor drives have been proposed [17]-[22]. Two types of space-vector-modulation (SVM) based nonzero-state (NZS) modulation techniques were adapted in [17] to reduce the CMV magnitude considerably. In [18], a SVM based modulation strategy with reference trajectory optimization (RTO) to reduce the CMV and improve the low-order harmonic performance was proposed. In [19], a SVM based method by selecting the proper zero vectors and using proper switching sequence to reduce the CMV peak was proposed. A solution based on average-value-reduction (AVR)
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DING et al. : MULTILEVEL CURRENT SOURCE CONVERTERS FOR HIGH POWER MEDIUM VOLTAGE APPLICATIONS
Multilevel SHE was proposed in [34] for MLC applications, a gating pattern of the converters can make a given set of harmonics generated by the two or more converters add up to zero. Therefore, more orders of unwanted harmonics can be eliminated to get better total AC current.
attenuated which greatly contributes to the suppression of the common-mode resonance. A. 3-level AVR SVM 1) 3-segment AVR SVM An average value reduction based SVM was proposed in [19] to minimize the average value of CMV during one sampling period instead of switching frequency with proper zero vector selection. The average value of CMV (CMV avg ) in each sampling period can be defined as CMVave = T1 ⋅ CMVact1 + T2 ⋅ CMVact 2 + T0 ⋅ CMVzero , (1)
C. Space Vector Modulation Based on the conduction constraint introduced before, only two switches in the inverter conduct at any time instant, one in the top half of the CSI bridge and the other in the bottom half. Under this constraint, the three-phase inverter has a total of nine switching states. These switching states can be classified as three zero switching states and six active switching states. There are three zero switching states [1,4], [3,6] and [5,2]. The zero state [1,4] represents that switches S i1 and S i4 in the inverter phase leg A conduct simultaneously and the other four switches in the inverter are off. The DC current I dc is bypassed, which leads to i a =i b =i c = 0. This operating mode is often referred to as the bypass operation. IV. SVM BASED CMV AND CIRCULATING CURRENT SUPPRESSION In the transformerless CSC system, the CM choke is implemented to attenuate the CMV instead of isolation transformer to reduce the system size and cost. Moreover, the neutral points of input and output filters are connected by a damping resistance which is used to reduce the motor voltage stress shown as Fig. 7. In that case, the possible CM resonance problem should be a concern due to the LC series connection under adjustable speed operation. Several CMV suppression methods to reduce the CM choke and damping resistance size are developed in the single CSC system [17]-[22]. SCR Sr1
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CMV is generated by device switching patterns, which can cause voltage fluctuations within the neutral points between the grid and load. The CMV reduction methods can be generally classified into two groups. Some methods depend on the structure modification and others rely on the modulation modification. Obviously, modulation modifications would be more practical and easy to implement. Most of SVM based RCMV methods are dedicated to suppress the peak value of CMV by removing or reselecting the zero states in the conventional SVM. However, the reduction of CMV peak value is not effective to suppress the common-mode resonance. This is because the third-order component in CMV is produced by both the active states and the zero states. If one could utilize the zero states to compensate the CMV produced by the active states, the lower average value of CMV would be achieved, so that the third-order component in CMV can be effectively
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where CMV act1 , CMV act2 and CMV zero represent the CMV produced by adjacent active and zero states in one sampling period, respectively. T 1 , T 2 and T 0 are the corresponding dwell time. 2) 4-segment AVR SVM The 4-segment AVR SVM places two zero vectors (I 01 and I 02 ) at two terminals of a sequence with equal dwell time of T 0 /2, while two active vectors are placed in the middle of the sequence. In order to minimize the switching frequency, the adjacent zero states of two consecutive sampling periods are kept the same. The switching frequency can be reduced while the CMV attenuation performance will not be affected since the phase voltages variation between two consecutive samples is small, meaning the zero state selected for the previous sample is also likely to be selected for the current sample in order to minimize the CMV ave . As there are 3 possibilities for the first zero vector and 3 possibilities for the second zero vector, which results in 9 options of zero state combinations in each sample. Compared with 3-segment AVR SVM, the 4-segment AVR SVM is more flexible for compensating the CMV produced by the active vectors, and has superior performance when the modulation index is low or the zero vector dwell times are high. T0 / 2 ⋅ CMVzero1 + T1 ⋅ CMVact1 + T2 ⋅ CMVact 2 (2) CMVave = +T0 / 2 ⋅ CMVzero 2 3) 4-segment AVR SVM Δ As the dwell time of the two zero vectors in the 4-segment AVR SVM are fixed as T 0 /2, 4-segment AVR SVM still has limitation on the CMV ave minimization. In order to further attenuate CMV ave , the 4-segment AVR SVM Δ is developed by allowing the two zero vectors placed at the two ends of a PWM sequence to have different dwell times, while the total dwell time of zero vectors (T 0 ) is remained unchanged. T 0 *Δ is the dwell time for the first zero vector, and T 0 *(1-Δ) is the dwell time for the second zero vector. Obviously Δ=0 leads to only applying the second zero vector, which becomes 3-segment AVR PWM, and Δ=0.5 leads to the 4-segment AVR SVM. T0 ⋅ ∆ ⋅ CMVzero1 + T1 ⋅ CMVact1 + T2 ⋅ CMVact 2 (3) CMVave = +T0 ⋅ (1 − ∆ ) ⋅ CMVzero 2 4) 3-segment AVR SVM Δ Although the 4-segment AVR SVM Δ could achieve superior CMV reduction performance, it may have adverse impact on the output current quality as the positions of active vectors within a PWM sequence are shifted by the variation of Δ. In order to improve the harmonic performance while maintaining the CMV reduction performance, 3-segment AVR
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DING et al. : MULTILEVEL CURRENT SOURCE CONVERTERS FOR HIGH POWER MEDIUM VOLTAGE APPLICATIONS
adopted to reduce the average value of CMV instead of the peak value. These methods were verified by both simulation and experiment with good performance. The average value of CMV produced in each sampling period in multilevel modulation can be shown as
CMVave = T1 ⋅ CMV1 + T2 ⋅ CMV2 + T3 ⋅ CMV3 ,
(6)
where CMV 1 , CMV 2 and CMV 3 are the CMV produced by the three adjacent vectors I x , I y and I z respectively. The multilevel AVR SVM is proposed to choose proper switching states to minimize the average value of CMV during each sampling period. Based on the above analysis, this modulation method is more flexible compared to a single CSC system. The offline third CMV with conventional 5-level SVM, which is aimed to minimize the switching times, and 5-level AVR SVM is shown as Fig. 11, which shows that the 5-level AVR SVM can reduce the CMV at the whole modulation index region.
311
the CMC, C eq means the equivalent capacitance of input and output filters, L 1 =L 2 …=L n represent the CM inductance of each module. As can be seen that, the difference of CMV produced by adjacent CSI is proportional to the circulating current and the CMC is related to the sum of CMV produced by each CSI. Suppressing circulating current and CMC is to make a compromise between the CMV difference reduction or total CMV reduction, an effective way is to suppress the CMV of each CSC to a small value. V. SIMULATION RESULTS To better verify the effectiveness of introduced multilevel AVR SVM for parallel CSC-fed drive system, simulation is conducted on a parallel medium voltage high power drive system. The system parameters are shown as Table II. The two paralleled CSC parameters are totally the same with shared input and output filters. Synchronous SHE is adopted to each rectifier side to eliminate low order harmonics. And 3-level AVR SVM, conventional 5-level SVM and 5-level AVR SVM are applied on the inverter side to compare their CMV suppression effectiveness. TABLE II SIMULATION AND EXPERIMENT PARAMETERS Parameters
Fig. 11. Offline calculation of third order CMV with AVR SVM strategies for parallel CSC.
To understand the relationship between circulating current and CMV, the equivalent common-mode loop circuit analysis introduced in [20] can be extended to the N-CSC parallel system, which is shown as Fig. 12. Thus, the circulating current and CMC expressions can be derived as (7) _
i1
+
_
L2
in
_
+
+
Ln
_
v2
DC link
vn
Grid frequency
60Hz 5.35mH
Input filter capacitance
92uF
Differential-mode inductor
47.3mH
Common-mode inductor
400mH
CM resistance
35Ω
CM resonance frequency
24Hz
CSI output capacitance CSI
Rated motor power/voltage Stator leakage inductanc
_
R
Fig. 12. Equivalent common-mode loop circuit with N CSCs in parallel.
V2 − V1 icr1 = i1 − i2 = jω L Vn − Vn −1 , (7) icrn = in −1 − in = jω L 1/ n ⋅ (V1 + V2 + Vn ) icm = iR = i1 + i2 + in = R − jX C + 1/ n ⋅ jX L where i crn means the circulating current between the nth CSC module, V 1 to V n represent the third order CMV produced by each CSI, i cm following through the damping resistance means
Motor
4160V 1MVA
Line inductance
Stator resistance
+
Ceq
iR
CSR
v1
+
i2
Nominal power
_
+
L1
Grid voltage (line-to-line)
Simulation Values
76.6uF 1MW/4160V 0.21Ω 5.2mH
Magnetizing inductance
155mH
Rotor resistance
0.146Ω
Rotor leakage inductance
5.2mH
Fig. 13 shows the CMV and CMC waveform with AVR SVM strategies when the motor running at 13Hz. Fig. 13(a) and (b) show the 3-level AVR SVM for single and parallel system respectively. It shows that the voltage stress between the input and output filter neutral points increases from 174.6V to 335.7V and the CMC rises from 3.63A to 7.02A, due to the reduction of system resistance after parallel connection. The simulation results of 5-level AVR SVM for parallel CSC are shown as Fig. 13(c). The CMV can be reduced to only 42.33V and the CMC is suppressed to only 0.864A, which can effectively reduce the size of CM choke. The circulating current and CMC waveforms with conventional 5-level modulation and 5-level AVR SVM for parallel CSC system are shown as Fig. 14. The motor is running
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