multilevel voltage source converters for high

WS 2012 OTTO VON GUERICKE UNIVERSITY FACULTY OF ELECTRICAL ENGINEERING AND INFORMATION TECHNOLOGY INSTITUTE OF ELECTRIC POWER SYSTEMS

MULTILEVEL VOLTAGE SOURCE CONVERTERS FOR HIGH/MEDIUM AND LOW POWER APPLICATIONS

RESEARCH PROJECT

HADI AMIRI ADVISOR: DR. FISCHER

DECEMBER 2012 MAGDEBURG GERMANY

MULTILEVEL VOLTAGE SOURCE CONVERTERS

OTTO-VON-GUERICKE UNIVERSITY

CONTENTS 1.

OVERVIEW-------------------------------------------------------------------------------------------------------------3

2.

HIGH POWER MULTILEVEL CONVERTERS ---------------------------------------------------------4 2.1 2.2 2.3 2.4

2.5

2.6

3.

LOW POWER MULTILEVEL CONVERTERS-------------------------------------------------------- 35 3.1 3.2 3.3 3.4

3.5 3.6 3.7

4.

Introduction ----------------------------------------------------------------------------------------------------- 4 Classification ----------------------------------------------------------------------------------------------------5 Advantages and Disadvantages -------------------------------------------------------------------------------6 Three Major Commercialized Converters -------------------------------------------------------------------6 2.4.1 Cascaded H-Bridges---------------------------------------------------------------------------------6 2.4.2 Diode Clamped---------------------------------------------------------------------------------------9 2.4.3 Capacitor Clamped---------------------------------------------------------------------------------12 Other Topologies----------------------------------------------------------------------------------------------15 2.5.1 Generalized Converter (P2)------------------------------------------------------------------------15 2.5.2 H-NPC------------------------------------------------------------------------------------------------15 2.5.3 3L-ANPC --------------------------------------------------------------------------------------------17 2.5.4 Modular Multilevel Converter (MMC) ---------------------------------------------------------17 2.5.5 NPC-CHB--------------------------------------------------------------------------------------------18 2.5.6 New Topologies in Power Systems --------------------------------------------------------------19 2.5.6.1 Multilevel Converters in FACTS ---------------------------------------------------19 2.5.6.2 UNIFLEX- PM in Smart Grid -------------------------------------------------------19 Modulation Methods ------------------------------------------------------------------------------------------22 2.6.1 Classification----------------------------------------------------------------------------------------22 2.6.1.1 Based on switching frequency-------------------------------------------------------22 2.6.1.1 Open Loop/Close Loop---------------------------------------------------------------23 2.6.2 Multilevel Carrier-Based PWM-------------------------------------------------------------------26 2.6.3 Space Vector PWM (SVM) -----------------------------------------------------------------------30 2.6.4 Harmonic Elimination PWM----------------------------------------------------------------------32

Introduction ----------------------------------------------------------------------------------------------------35 Basic Topology: Three-level NPC --------------------------------------------------------------------------36 Modulation Methods -----------------------------------------------------------------------------------------37 New Topologies -----------------------------------------------------------------------------------------------40 3.4.1 Active NPC------------------------------------------------------------------------------------------40 3.4.2 T-Type NPC Topology---------------------------------------------------------------------------- 41 3.4.3 Hybrid Topology (HNPC)-------------------------------------------------------------------------45 Chip Area Comparison----------------------------------------------------------------------------------------46 Efficiency Comparison ---------------------------------------------------------------------------------------48 Summary--------------------------------------------------------------------------------------------------------50

SIMULATION BY PSIM-----------------------------------------------------------------------------------------51 4.1 4.2 4.3 4.4 4.5

Introduction-----------------------------------------------------------------------------------------------------51 One-phase Five-level Cascaded–HB------------------------------------------------------------------------51 Three-Phase Three-level Natural Point Inverter-----------------------------------------------------------55 Three-Phase Three-level Capacitor Clamped (Flying Capacitor) Inverter-----------------------------60 Comparison Between Three-Level FC and NPC Inverters ----------------------------------------------63

References-------------------------------------------------------------------------------------------------------------------64 RESEARCH PROJECT, H.AMIRI, DEC. 2012

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1. OVERVIEW Multilevel Voltage Source Converters are in power electronic complete famous. Predominantly they are extended in medium and high power industrial application. At low voltage, low-power there is a single topology that dominates the market: the voltage-source two-level inverter. The aim of this research is firstly to consider and investigate the voltage source multilevel converters in medium and high power applications and then evaluates three-level topologies as alternatives to two-level converters for low-voltage applications, in order to show the current state of the technology. Table 1 shows a general view of the high and low power converters.

Converters Low Power

High Power (medium/high voltage)

(low voltage) Indirect Conv.

Direct Conv. (ac-ac)

(ac-dc-ac) Current Source

Voltage Source Conv. (VSC)

Matrix Conv.

Cycloconverter

2-level Conv.

Voltage Source Conv. (VSC)

Multilevel Conv.

2-level

3-level

NPC (Diode Clamped) CHB (Cascaded H-Bridge) FC (Flying Capacitor) Table 1: A general view of energy converters [1]

RESEARCH PROJECT, H.AMIRI, DEC. 2012

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2. HIGH POWER MULTILEVEL CONVERTERS 2.1 Introduction [2,14] Only one switch cannot withstand a high or medium voltage and the direct connection of it to high power (or medium) system is difficult. In former times more than one switch connected in series was a solution, what we know at present as conventional 2-level topology, in which instead of one switch a combination of switches hold the whole dc-link voltage. As an alternative the multilevel converters have been developed. The basic concept of a multilevel converter is that instead of using many switches for whole dc voltage(conventional), the multi dc-link voltage sources (e.g. capacitors, batteries, and renewable energy voltage sources) should be used and somehow connected to switches that each switch blocks a reduced level of whole dc-link voltage. Fig. 1 shows the process from 2-level to multilevel converter. Conventional high power 2-level Converter voltage It is hard to connect a single semiconductor switch directly to medium or high voltage system

a new family of multilevel inverters has emerged as the alternative for working with higher voltage levels.

Figure 1: The process from 2-level to multilevel converter. [2,14]

However, a high number of levels increases the control processes and gives voltage imbalance problems and asymmetric distributed losses in chip, which will be discussed in the next parts.


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2.2 Classification [1] Reference [1] has classified the high-power converters as is presented in Fig. 2. “This classification also includes direct ac–ac converters and current source converters, which are currently the main competitors of multilevel technology”, but we will consider in this research only voltage source converter structures.

Figure 2: Classification of high-power converters; reference[1]


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2.3 Advantages and Disadvantages [2, 24] A multilevel based voltage source converter has some advantages over a conventional 2-level converter. The attractive features can be briefly summarized as follows: 

Output voltages with low harmonic distortion



Input currents will be more sinusoidal and with low distortion



Cleaner output waveform with low distortion allows the smaller volume of filter size.



Reduced dv/dt stresses at converter terminals, i.e. at cables and end windings of transformer, motor, or generator, and consequently a reduction in dv/dt filter size and losses.



Reduced common mode voltage which reduces common mode currents



Lower needed switching frequency which means lower switching losses

Unfortunately, multilevel converters have some disadvantages that can be categorized as: 

The greater number of power semiconductor switches (Although lower voltage rated switches can be utilized)



A separate gate drive circuit for each switch



Complexity of control system



Generally higher cost

2.4 Three Major Commercialized Converters [1,2,3,4,14] For better understanding of the new advances in multilevel technology, it is necessary to understand classic multilevel converter topologies. Three different major multilevel converter structures have been reported in the literature: cascaded H-bridges converter with separate dc sources, diode clamped (neutral-clamped), and flying capacitors (capacitor clamped).

2.4.1 Cascaded H-Bridges [1,4,14] Cascaded H-Bridge is the oldest and therefore the most important topology for understanding the basic concept of multilevel converters. For this it is reasonable to go first into it. Historically W. McMurray in 1971 was the first person who introduced multilevel concept with presentation of a series-connected H-bridge, which is today known as CHB. With works of M.Marchesoni in 1988 RESEARCH PROJECT, H.AMIRI, DEC. 2012

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and P.W.Hammond in 1995, the CHB achieved more industrial appearance [1,14]. An one-phase m-level CHB is depicted in figure 3(a). As can be seen, each H-bridge has its own separate dc source that can generate by a suitable combination of four switches(S1…S4) three voltage levels on output terminal: +Vdc, 0, and –Vdc. Understanding the switching combinations is very simple. If we close S1 and S4 simultaneously while S2 and S3 are turn off then we have +Vdc. Contrary, the reverse voltage –Vdc can be obtained by turning on S2 and S3 at the same time, whereas S1 and S4 are open. For output voltage 0 there is two possibilities: the closed switches S1 and S2 or the closed switches S3 and S4, so that the other two switches are turned off. In principle each H-Bride has two points for connection to ac-terminals, viewable in fig. 3(b).

(a)

(b)

Figure 3: (a) Output phase voltage waveform of an 11-level cascade inverter [4] (b) Single-phase structure of a m-level cascaded H-bridges inverter [4]

The first point of the first H-bridge is connected to one ac-terminal, and the second point of the last H-bridge is attached to other ac-terminal. The all other rest points of H-bridges are connected


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in series so as second point of up-H-bridge is connected to first point of down-H-bridge. As a result the ac output voltage van is the sum of the H-bridges output voltages and the number of steps (or levels) m (from peak to peak of van) can be given simply by m = 2S+1, where S is the number of separate dc sources. A staircase 11-level waveform obtained of five separate dcsources (S=5) is depicted in fig. 3(b). There, it is easily perceived the different to van connected time periods of each dc sources; as va1 (dc voltage of the last down dc source) has the shortest (P1) and va5 (dc voltage of the first up dc source) the longest time period (P5). As a hint, there is several switching options generating same output ac voltage in CHB circuit and hence the cycle duration of va1, va5 (P1, P5) in a other switching way could be complete other than above described. [4,14] In Photovoltaic systems, the CHB is very attractive since the adequate dc sources exist and on the other hand due to the possibility of direct connection to grid by connecting the series Hbridges which elevate naturally the voltage level and thus eliminate the need for a boost converter or transformer. One simple structure consist of multi PV strings is depicted in fig. 3(c). [1].

Figure 3 (c): CHB-based photovoltaic grid-connected Converter[1]

Reference 4 shows also an interesting cascaded converter as a rectifier/charger for the batteries of an electric vehicle. As can be seen in fig. 3 (d) the vehicle connects to an ac supply (charger) to charge the batteries.


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Figure 3 (d): Three-phase CHB for electric vehicle motor drive and battery charging. [4]

The main features of multilevel CHB can be presented as follows. [1,4,14] Advantages: 

The modular structure that enables simple manufacturing and simple and quick installation



The output voltage levels are more than two times the number of dc sources (m=2s+1).

Disadvantage: 

Each H-bridge needs one separate dc source

2.4.2 Diode Clamped [1,2,3,4,7,14] The diode clamped or neutral point clamped converter NPCC presented by Nabe in 1981 is the most widely in the industry utilized topology and is very appealing for medium voltage applications up to 6 kV [3]. The clamped diodes of this structure are the key components, which identify and characterize it’s structure. They clamp the switching voltage of semiconductors to RESEARCH PROJECT, H.AMIRI, DEC. 2012

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half the whole dc-link voltage. In section 3.2 we have discussed the function of a simple 3 levelNPC topology in detail and hence here want to investigate some complicated industrial applications. Several NPC structures are reported in the literatures for four-, five, six, and more levels which serve as SVC, variable speed motor drives, and high-voltage grid interconnections. Reference [4] and [10] have listed various industrial applications. A three-phase six-level diode-clamped inverter is shown in Figure 4(a) and line-line voltage waveform in 4(b). “Each of the three phases of the inverter shares a common dc bus, which has been subdivided by five capacitors into six levels. The voltage across each capacitor is Vdc, and the voltage stress across each switching device is limited to Vdc through the clamping diodes. For a six-level inverter, a set of five switches per leg is on at any given time.”[4] Fig. 4 (c) and (d) show industrial applications as photovoltaic grid-connected converter and as motor drive, respectively. The capacitors are in discharging mode when the output terminals are connected to positive side of them and they are in charging mode by connecting of terminal to negative side.

Figure 4(a): Three-phase six-level structure of a diode-clamped inverter[4]


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Figure 4 (b): Line voltage waveform for a six-level diode-clamped inverter[4]

Figure 4 (c): NPC-based photovoltaic grid-connected Converter[1]

Figure 4 (d): Three-level diode-clamped inverter with 12-pulse input rectifier.[2]

The main advantages and disadvantages of multilevel diode-clamped NPC converters can be listed as follows: [1,3,4,7]


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Advantages: 

Contrary to CHB, the NPC doesn’t need separate dc sources per leg (CHB requires one per H-bridge)



Less number of capacitors and switches compared to other major topologies



Efficiency is high for fundamental frequency switching [4], prominent for high and medium voltage applications; this advantage has been shown in 4.3 by simulation of a three-level NPC.

Disadvantages: 

The problem of reverse recovery feature of clamping diodes; i.e. more conduction losses for IGBTs.



Unequal loss distribution among semiconductors and so unsymmetrical chip temperature (This problem can be solved by Active NPC described in part 2.5.3)



The balancing problem of capacitors particularly in higher level topologies – although by advanced modulation method and using redundant switching possibilities this problem can be solved.

2.4.3 Capacitor Clamped [1,2,4] The basic concept of capacitor clamped converter (Flying Capacitor) was first presented by J. A. Dickerson in 1971 but have found by introduced topology of T. A. Meynard in 1992 more industrial applications particularly for medium voltage systems. FC (Flying Capacitor) topology is the same thing as NPC except that uses clamped capacitors instead of clamped diodes. A simple 3-level topology is simulated in chapter 4 by PSIM. For medium and high level voltage application FC needs higher switching frequency (greater than 1200 Hz) due to the capacitors should be balanced almost quickly. The proper switching frequencies for high power applications are in range of 500-700 Hz [1]. Because of this, conventional FC is less favorable for industry than NPC and CHB, despite the fact that it has modular structure. Reference 1 has listed some industrial applications. A six-level FC structure with Thyristors is depicted in Figure 5(a). In this topology the total voltage of each capacitor-leg differs from that of the next (the number of capacitors per leg is not the same). As can be seen, V5 consist of 5 capacitors, V4 from 4, and so on . As a result there will be six voltage levels as output waveform: {0,V5-V4, V5-V3, V5-V2, V5-V1, V5}. Except 0 and V5, which have no redundancy switching possibility, the other output voltage levels could be


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achieved by 4, 5 or 6 other combinations of switches; it helps to keep capacitors balanced without increasing switching frequency. [4]

Fig. 5(a) Three-phase six-level structure of a flying capacitor inverter [4]

Another industrial structure is shown in fig. 5(b). Contrary to fig. 5(a) here there is only one capacitor in each capacitor-leg. These capacitors are used only to produce new ways of commutation (phase redundancies) which keep the capacitors balanced. Hence, this structure with six IGBTs per leg produces only three-level output waveform. Furthermore by this type of 18-pulse rectifier we have a THD < 1.55 % according to [2]. As it will be shown in 4.4 there is a simple other three-level FC topology with only four IGBTs per leg useful for low power application. In low power applications the high switching frequency is possible, what allows balancing the voltage of capacitors without needing more switching redundancies.


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Figure 5: (b) Three-level capacitor-clamped inverter with 18-pulse input rectifier [2]

The main advantage and the main disadvantages of Flying Capacitor can be categorized as follow. Advantage: 

Requires only one dc-source



Possibility of other commutating ways (phase redundancy) which can used to balance the capacitors

Disadvantages: 

The need for large number of capacitors; they are expensive than clamping diodes



The balancing problem of capacitors – although by advanced modulation method or by new variants this problem can be solved.


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2.5 Other Topologies Many other topologies beside the three major previously introduced topologies have been proposed in the literatures and industrialized in several applications. Reference [1] shows a large number of new topologies for medium and high voltage systems. Most of them are a combination of the basic topologies or a slight variation of them. Some of these are briefly presented for a deeper understanding of multilevel converter concept.

2.5.1 Generalized Converter (P2) [9] Peng in 2001 at [9] introduced a new variant of capacitor clamped multilevel converter that can generate each required output levels serves too at the same time as a diode clamped. This is what is called Generalized converter or P2 (due to the basic cell is a 2-level Phase leg) and is illustrated in fig. 6. Any inverter with any number of output voltage levels can be achieved by this structure. As mentioned in [9] “the two-level inverter phase leg can be obtained by cutting off at the “2-level line,” three level inverter leg by cutting off at the “3-level line,” and so on”. As a result the M-level generalized converter is a combination of basic cells P2 in the form of a horizontal pyramid. One main advantage of P2 is that the balancing of capacitors can be obtained by itself without any control assistance circuit and even regardless of load characteristics. [9] Reference [2] presents a 4-level bidirectional dc-dc generalized converter for the dual-voltage system in future automobiles.

2.5.2 H-NPC [1] As the name of this topology suggests, it is obviously a combination of a conventional NPC and a classic H-bridge. As fig. 7 shows, here two 3-level NPC legs (connected similar an H-bridge) behave like one 3-level classic NPC leg. The combination of three voltage levels of each one of these two connected legs results in a 5-level output waveform. In addition each H-bridge requires one separate dc source to avoid short circuit of dc link. The 5-level H-NPC Converter was introduced by C. M.Wu in 1999. This hybrid structure has been industrialized by ABB and TMEIG-GE and “can be found in practice with a 36-pulse rectifier system featuring IGCTs and for a 2–7-MW (air cooled) or 5–22-MW (water cooled) power range.” [1]


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Figure 6: Generalized P2-cells, M-level, one phase leg, [9]

Figure 7: Three-phase, five level H-NPC. [1]


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2.5.3 3L-ANPC [1,12] The outer semiconductor devices in NPC have clearly more switching losses than those at inner. That is one of the before discussed disadvantages of this topology, which results in unsymmetrical junction temperature, what should be prevented if it would be critical in some applications. As a solution we can put two clamping active switches instead of two clamped diodes to make a new commutation way, as shown in fig. 8. By that the inner switches can be utilized for the positive or negative dc-link connection exactly like the outer switches. As a result we have equally distributed losses and consequently symmetrical junction temperature, which optimize the cooling system design and so increase the maximum power, current and switching frequency [1]. But according to [12] “the losses for the A-NPCC are similar to the conventional NPCC, and the main advantages in the use of this more complex structure are the loss balance control capability.”

Figure 8: Active 3L-NPCs (with only phase a shown) featuring IGCTs [1]

2.5.4 Modular Multilevel Converter (MMC) [1] Modular Multilevel Converter is developed by [R. Marquardt;2001] particularly for HVDC systems and is basically built of the connected in series single-phase two-level VSC modules (known as half-bridges), as can be seen in fig. 9. It is evident that the total dc voltage is the sum of all power cell voltages in one leg. The two switches per cell can connect or bypass the related RESEARCH PROJECT, H.AMIRI, DEC. 2012

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capacitor voltage to the total leg voltage, which can produce multilevel waveform. According to [1], “some inductors are usually included within each leg to protect during transitory short circuits.” and “This topology can be found in practical applications reported with 200 powercell/phase reaching up to 400 MW and is commercialized up to 1 GW.”

Figure 9: Modular Multilevel Converter (series-connected 2L-VSIs). [1]

2.5.5 NPC-CHB [1] This very interesting hybrid topology presented by [P. Steimer; 2003;U.S. patent] has found newly industrial applications. As the name reveals, that is a hybrid topology composed of threelevel NPC and single phase CHB. One side of the single phase CHB is connected to one NPC leg and another side to load to generate more output voltage levels. As reference [1] describes, “The number of H-bridge cells connected in series usually varies between one and two. The CHB stage acts as a series-connected active filter (AF). Although it contributes to enhance the power quality and reduce the common-mode voltages, it also introduces additional conduction and switching losses. The H-bridge dc-link capacitor voltage control, which is necessary to keep the desired voltage ratio between the NPC and the CHB, also adds to the complexity of the control system and requires additional voltage sensors.”


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Figure 10: Multilevel NPC-CHB hybrid converter with one or more H-bridges in series connection per phase (can also have unequal dc voltage ratios) [1]

2.5.6 New Topologies in Power Systems [1] 2.5.6.1 Multilevel Converters in FACTS Flexible AC Transmission Systems are known as a power control and management instrument in electrical networks generally due to the problems of active and reactive power transfer and controllability. Some devices that are considered as FACTS are STATCOM, UPFC, Active Filter(AF), and so on. They provide instant reactive power compensation in respond to transitions to enhance the grid voltage stability. Figure 11 illustrates three multilevel converters that serve as FACTS devices. [1] 2.5.6.2 UNIFLEX-PM in Smart Grid This is an advanced future power converter system for Universal and Flexible Power Management in electricity networks in order to control the power flow of several grids. It will be necessary for connection of the increased renewable energy sources. A 3 port UNIFLEX-PM system is presented in figure 12. According to [1] this topology “is capable of interconnecting three different points of common coupling, which are symbolized as three-phase grids. The power converter is based on threephase CHB multilevel converters in back-to-back configuration with an intermediate dc–dc converter stage with a medium-frequency isolation transformer to decouple the grids and provide galvanic isolation between them.” [1]


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Figure 11: (a) Thirteen-level CHB-based 6.6-kV 1-MVA transformerless STATCOM [H. Akagi;2007]. (b) 3LNPC-based AF [H. Akagi;2009]. (c) Seven-level FC H-bridge AF with tapped reactor connection for Marine power system [P. Xiao;2009]. [1]


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Fig. 12 Three-port UNIFLEX-PM system based on CHB for power management of integrated power systems in distributed generation [J. Clare; 2009]. [1]


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2.6 Modulation and Control Methods


[4,6,7,8,15,19,20,21]

Modulation strategy is one of the most important issues respecting the efficiency of energy converters. Basically it can affect the switching losses, conduction losses, and harmonics. Up to now a large number of modulation methods have been introduced but we will discuss only the most popular ones particularly those which have used in multilevel converters. It is important to mention that the choice of modulation and control method depends particularly on the convertor load.

2.6.1 Classification The basic modulation strategies can be classified based on switching frequency or open/closed loop concept. 2.6.1.1 Based on Switching Frequency The multilevel modulation strategies can be categorized in fundamental and high switching frequency methods, as illustrated in fig. 13(a). The fundamental frequency switching methods result in only a few switching actions of each one of semiconductors during one cycle of output waveform [15]. These methodologies will be discussed in 2.6.2, 2.6.3 and 2.6.4. Multilevel Converter Modulation Strategies

Fundamental Switching Frequency

Space Vector Control

Selective Harmonic Elimination

High Switching Frequency

SpaceVector PWM

Sinusoidal PWM

Selective Harmonic Elimination PWM

Figure 13(a): Classification of multilevel inverter control schemes. [4,15]


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2.6.1.2 Open Loop/Close Loop From other point of view the control strategies are divided in open loop and closed loop methods, as depicted in fig. 13(b). The Selective Harmonic Elimination (SHE) and Optimized Harmonics Stepped (OHS) need pre-defined calculations and hence are not included in the open/close loop control classification. [15]

Figure 13(b): Another Classification of multilevel inverter control schemes. [15]



Open Loop PWM Control Technique:

From three open loop techniques the SPWM and SVM are considered in details at 2.6.2 and 2.6.3, respectively. Reference [21] describes ∆Σ (Sigma Delta) control process; the respective modulator diagram is shown in fig. 13(c). “The ∆-stage subtracts the output from the reference. The Σ-stage is an integrator summing up the difference signal and feeding a comparator. This comparator is changing its output in dependency of the integrator signal being higher or lower as a constant reference. A latch, i.e. a D-type flip flop, is transferring the comparator output pulses triggered by a rectangular clock signal derived from an oscillator. The oscillator RESEARCH PROJECT, H.AMIRI, DEC. 2012

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frequency with a 50 % duty cycle is adjusting the main switching frequency. The main switching frequency is expected to be half of the clock frequency, when using a positive edge triggered flipflop.”[21]. This open loop control method is mostly applicable to power convertors that use analog-digital (ADC) or digital-analog converters(DAC).

Figure 13(c): Block diagram of a Sigma Delta modulator [21]



Closed Loop PWM Control technique:

In some applications such as motor drives (particularly for nonlinear loads) or FACTS devices the current and/or voltage should be measured and then compared to the set point for a proper performance. Also, the PV and Wind power plant converters connected to grid are committed to give a sinusoidal current with low harmonic distortion to power system. For this, a feedback (closed loop) based control structure is required. Hysteresis Current Control: A most industrialized method between the in fig. 13(b) listed feedback control techniques is Hysteresis Current Control. In this method, as can be seen in fig. 13(d), “the load current tracks the reference current within a hysteresis band.”[15] Linear Current Control: This method uses most the PI controller to regulate output current. A schematic of Linear Current Control structure is illustrated in fig. 13(e). As can be seen a Space Vector Modulation (described in 2.6.3) is applied to control the switches. Instead of SVM, we can use two comparators to compare the PI output with a high frequency triangle waveform.


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Figure 13(d): Hysteresis current control; the down figure shows the switch pulse. [15]

Figure 13(e): Linear Current Control RESEARCH PROJECT, H.AMIRI, DEC. 2012

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************* In the following the three important modulation methods developed to control the behavior of multilevel converter will be discussed.

2.6.2 Multilevel Carrier-based PWM

[4,7,13,15,19,20]

This is the simplest modulation method for both conventional 2-level or multi-level converters. The major difference is that multilevel converters need multi carriers instead of one carrier as is typical for 2-level converters. Three carrier-based PWM can be used to apply in multilevel converters: Sinusoidal PWM, Third Harmonic injection PWM (THPWM), and Space Vector PWM (SVM). Sinusoidal PWM is a very simple and therefore popular method in the industry. SPWM for multilevel converters is the same of for conventional 2-level converters. A sinusoidal reference waveform(known too as control signal) is compared to a high frequency triangular carrier signal to give the on/off pulses of the semiconductor switches. Usually the carrier frequency is 7…10 times greater than reference signal. Multilevel converters need more than one carrier. The carriers will be given in vertical or horizontal arrangement. The vertical carrier arrangements are known as Phase Dissipation (PD), Phase Opposition Dissipation (POD), and Alternative Phase Opposition Dissipation (APOD), while horizontal arrangement is defined as Phase Shifted (PS) PWM; as are shown in fig. 14 (a-d), respectively.”In fact PS-PWM is only useful for cascaded H-bridges and flying capacitors, while PD-PWM and derivations are more useful for NPC. [15]”. A SPWM for a three-level converter is discussed in 3.3. Moreover, in chapter 4 (simulation with psim) all the simulated inverters are controlled with this modulation scheme. There, additional descriptions are presented. Note that a carrier as triangular waveform can be applied to some other control methods such as linear current control, but here the “carrier-based” means that these triangular carriers and the reference/control waveform (and not the measured values of current/and voltage) are the main factors producing output waveform.


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Third Harmonic Injection PWM : Reference [4] gives an excellent description of TH-PWM. “Adding a third harmonic modulation to the previous reference sine wave decreases the overall amplitude of the resulting PWM modulation. This is due to the fact that the minimum of the 3rd harmonic corresponds to the maximum of the fundamental and vice versa. So in order to achieve better dc link utilization at high modulation indices, the sinusoidal reference signal can be injected by a third harmonic[4]”, shown in 14(e). And according to [20] “It can be shown that by applying an appropriate coefficient to the third harmonic component, fundamental amplitude can be increased by 15%. Finally, when considering the phase to phase voltage on the motor, third harmonic components are mutually cancelled out (a 120-degree phase-shift on the fundamental corresponds to a 360-degree shift for the third harmonic) and we have on the motor windings : – Sinusoidal voltage (and therefore currents) on the motor – Phase to phase voltage 15% higher than with pure sine wave PWM modulation Consequently, this allows you : – to decrease diameter of copper windings in the motor for a given power rating. – to increase the current in the motor for a given frequency, therefore providing more output power. – to increase maximum reachable speed for a given torque, as long as mechanics (ball-bearings mainly) are suited for very high speed operations.[20]” Space Vector PWM : SVM is basically a non-carrier based control method; see 2.6.3. SVM is relative difficult to obtain in multilevel topologies and therefore some researchers have tried to implement SVM with carrier-based PWM. They found the relationship between SVM and Carrier-based PWM. As a result SVM can be achieved by comparing the carriers to a reference waveform composed of a sine waveform with the addition of a zero-sequence duty cycle [7]; as is illustrated in fig. 14(f) for a 3-level NPC. Reference [13] shows the relationship between SVM and Carrier-based PWM for multilevel converters. Moreover, J. Pou in 2012 at [17] introduces a Carrier Based SV-PWM strategy that ”autonomously carries out the voltage balancing task, with no requirement for additional control effort”. It will be worthful to mention that “the existing Carrier Based-PWM strategies do not provide natural voltage balancing; therefore, additional control effort is required to achieve the voltage balancing . The additional control effort imposes relatively high-switching frequencies in the switching devices and also distorts the ac-side voltage spectra.” [17]


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“Obviously, the dc utilization of THPWM and CB-SVM are better than SPWM in the linear modulation region. The dc utilization means the ratio of the output fundamental voltage to the dc link voltage.” [4]

(a)

(b)

(e)

(c)

(d)

(f)

Figure 14: (a-d) Multi-carrier SPWM control strategies: (a) PD, (b) POD, (c) APOD, (d) PS. [15] (e) Third Harmonic injection PWM. [7,20] (f) Carrier-based Space Vector PWM for a 3-level NPC. [7]

Other interesting Carrier-based multilevel PWM are Sub Harmonic PWM (SH-PWM) developed by Carrara 1992 and Switching Frequency Optimal PWM (SFO-PWM) developed by Steinke 1988, depicted in fig. 14(g) and14(h) , respectively.

(g)

(h)

Figure 14: (g) Sub Harmonic PWM (SH-PWM), modulation index =0.8 (h) Switching frequency optimal PWM (SFO-PWM), modulation index =0.8 [4]; this scheme can also be considered as one of SVM schemes [13] RESEARCH PROJECT, H.AMIRI, DEC. 2012

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The difference of SH-PWM with the above described methods is that it’s zero line centered in the middle of the carrier set. SFO is similar to SH-PWM except that a zero sequence (triple harmonic) voltage is added to each of the carrier waveforms. The SFO-PWM technique enables the modulation index to be increased by 15 percent before the over modulation region is reached. [4] “For the SH-PWM and SFO-PWM techniques, the top and bottom switches are switched much more often than the intermediate devices. A novel method [L. M. Tolbert;1999] to balance device switching for all of the levels in a diode clamped inverter has been demonstrated for SH-PWM and SFO-PWM by varying the frequency for the different triangle wave carrier bands” [4]; shown in 14(i).

Figure 14: (i) SFO-PWM where carriers have different frequencies; modulation index =0.85 [4]

Figure 14: (j) Reference rotation among carriers at modulation index < 0.5 to achieve carrier frequency doubling [4]


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For very low modulation index (e.g. m < 0.5), some outer levels can be lost and a multilevel inverter can operate even like a conventional 2-level. This problem but allows the inverter to have more redundant states (outer levels), which can be utilized to balance the dc-link capacitors voltage. In order to use the unused outer levels we can rotate the reference waveform among the carriers, as can be seen in fig. 14(j). Consequently the output signal will be obtained during two duty cycle of reference voltage; i.e. doubling the carrier frequency. [4,19]

2.6.3 Space Vector PWM (SVM) [17, 23] Space Vector Modulation is at present a standard control strategy applying to power converters. The initial use of SVM was at voltage source two-level and then three-level inverters but has been expanded to multilevel converters. Originally the basic concept of vector representation of 3-phase system was introduced by Park in 1933. Edith Clarke presented the well-known Clarke Transformation, with which the behavior of any three-phase system can be represented by a rotating vector in a complex plane. It results in monitoring a 3-phase system as a whole and with only two components in complex coordinate system, instead of looking each phase separately. This statement can be understood by the following illustration. [23]

Figure 15(a): Equivalent between a 3-phase system and vectorial presentation [23]

An excellent description of SVM in details can be found in Reference [23] for basic understanding and in [17] for multilevel applications. According to [17] any n-level SVM diagram is composed of six sectors generating n3 switching states. Each sector has (n-1)2 vector combinations (Regions). A 3-level SVM diagram is illustrated in fig. 15(b).


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Figure 15(b): Voltage space vectors for a 3-level NPC inverter [17]

“In the αβ frame, a two-layer hexagon, centered at the origin of the plane, identifies the spacevoltage vectors, as shown in Fig. 15. The switching states are illustrated by −1, 0, and 1, which denote the corresponding voltage levels of −Vdc/2, 0, and Vdc/2 with respect to the Natural Point. At any sampling instant, the tip of the voltage vector Vref is located in a triangle (Regions). The three adjacent switching vectors constitute the best choice for synthesizing the reference-voltage vector. The determination of the adjacent switching vectors and calculation of their corresponding duty cycles are explained in [18]. Subsequent to that, the next step is to identify the appropriate switching states and generate the switching sequence to control voltages of the capacitors. By proper selection of short vectors, i.e., 0–1–1/100, 00–1/ 110, −10–1/010, −100/011, −1–10/001, and 0–10/101, the voltage-balancing task of the dc-link capacitors is carried out. The short vectors provide redundant switching states and generate the same line-toline ac-side voltage. However, they provide currents with opposite directions flowing into the RESEARCH PROJECT, H.AMIRI, DEC. 2012

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NP. For instance, vector 0–1–1 imposes current ia to the NP (i0 = ia ), while vector 100 imposes the same current in the NP but in the opposite direction (i0 = −ia ). Adding one level to all three integer numbers that define the “low” short vectors, i.e., 0–1–1, 00–1, −10–1, −100, −1–10, and 0–10, results in the “high” short vectors, i.e., 100, 110, 010, 011, 001, and 101, respectively. Note that applying the “low” vectors results in having one or two phases connected to the lower dc-link rail, while the “high” vectors connect one or two phases to the higher dc link rail. In any case, the line-to-line voltages do not depend on the specific vector and can be considered as redundant vectors”. [17] SVM results in low harmonic distortion of load voltage with 15% greater peak value compared to classic carrier-based PWM. The complexity of sector identification and required look-up table can be easily implemented using Digital Signal Processors (DSPs) or Microcontroller Units(MCUs); [17]. However by increasing the dc-link levels SVM will be very complicated1, therefore some researchers have tried to implement SVM with carrier-based PWM, as described in 2.6.2.

2.6.4 Harmonic Elimination PWM

[4,6,8,24]

Harmonic Elimination Methods (proposed by Patel in 1974) are basically a fundamental switching frequency modulation strategies and can be categorized in Selective Harmonic Elimination (SHE) and Optimized Harmonic Stepped (OHS) PWM. They are based on finding switching angles offline2 by solving many polynomial equations to remove the predefined lower odd harmonic orders (3th, 5th, 7th, …). The even harmonics don’t exist due to the symmetric characteristic of the waveform. The switching angles for both methods are calculated during a quarter of fundamental period. Clearly, because of symmetry of sine waveform, other switching angles can be simply obtained at three other quarters. OHS gives only one angle pro level; e.g. for a 5 level-converter it’s needed calculating only two switching angles; the first angle at the beginning of first level and the second angle at the beginning of second/higher level. For an 11-level converter the five per quarter needed angles are depicted in fig. 16(a). By OHS, each semiconductor switch would be switched once during fundamental frequency. Contrary, SHE gives any number of desired switching angles but for one voltage level; i.e. more switching frequency. Figure 16(b) presents 1 2

Reference [16] shows a simple SVM which decompose multilevel SVM to 2-level SVMs. J. Sun presented an online calculation method in: “Optimal PWM based on real time solution of harmonic elimination

equations,” IEEE Trans. Power Electron., vol. 11, no. 4, pp. 612–621, Jul. 1996.


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SHE for a three-level converter. Note that the switching angles are not limited to a specific number but in high switching frequency the polynomial equations finding angles are very difficult to achieve.

Figure 16(a): OHS switching angles for an 11-level converter [8]

Figure 16(b): SHE switching angles for a 3-level converter. [24]

As reference [8], “in the multilevel inverters, for every voltage level, there could be multiple switching angles. The number of eliminated harmonics is decided by the number of voltage steps and number of switching angles in each voltage step. However, because of the complexity of the problem, most studies proposed so far are for one switching angle per one voltage level.” For this reason, we consider in

detail OHS modulation method. The Fourier expansion of the staircase waveform is presented as follow: [8]

Where N is the number of switching angles and m is the harmonic order. As an example and for an 11-level case (synthesized by 5 dc-sources or 5 H-bridge cells), the 5th, 7th, 11th, and 13th harmonics would be eliminated. The triple harmonics in a 3-phase system will be removed automatically from line-to-line output waveform because of 120 degree


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phase shift. Therefore, supposed that S is the number of dc-sources1, for a line-line waveform the lowest (S-1) non-triple odd harmonics can be removed. If the objective is a single phase waveform then then the lowest (S-1) odd harmonics can be eliminated. Also, it is clear that all even harmonics don’t exist in single phase as well as 3-phase system due to the both waveforms has symmetric characteristics. With respect to these, the corresponding equations are as follow: cos(5 θ1) + cos(5 θ2) + cos(5 θ3) + cos(5 θ4) + cos(5 θ5)= 0 cos(7 θ1) + cos(7 θ2) + cos(7 θ3) + cos(7 θ4) + cos(7 θ5) = 0 cos(11 θ1) + cos(11 θ2) + cos(11 θ3) + cos(11 θ4) + cos(11 θ5) = 0 cos(13 θ1) + cos(13 θ2) + cos(13 θ3) + cos(13 θ4) + cos(13 θ5) = 0 cos(θ1) + cos(θ2) + cos(θ3) + cos(θ4) + cos(θ5) = (V1. π)/(4Vdc) Reference [4] has calculated these switching angles using Newton-Raphson iterative method and at a modulation index equals 0.8 as following : θ 1 = 6.57° , θ 2 = 18.94° , θ 3 = 27.18° , θ 4 = 45.14° , θ 5 = 62.24° . By switching at these angles during each one of four quarters, the harmonic orders of 5th, 7th, 11th and 13th will be eliminated.

1

The number of output voltage levels in a single phase waveform is 2s+1 and in phase-phase waveform is 4s+1.


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3. LOW POWER MULTILEVEL CONVERTERS [1,3,5,6,8,10,11,12,18,22,24]

3.1 Introduction Although the multilevel converters was first developed to medium and high voltage applications due to limited blocking voltage of semiconductor switches, they have many other advantages over conventional two-level converters described in the former chapter. These advantages are also appealing for low power low voltage1 converters, in which the blocking voltage of devices is not problematic but the lower switching losses obtained by higher available levels increase the efficiency and can result in an optimized required chip area which means reducing the dimensions of device and decreasing the costs. In addition, the more available levels allow a reduction of the output filter size without increasing the switching frequency, what decreases again the costs2. However there will be a circuit complexity obtained of additional implemented switches, as well as an increased cost because of increased elements. Another interesting aspect of multilevel converter is the lower required blocking voltage of semiconductor switches. For instance, the implemented IGBTs for low voltage two-level rectifier applications have typically the blocking voltages of 600-, 1200-, 1700-V when the input phasephase voltages are 200…300, 380…460, 575…690 V-rms, respectively. But the required IGBTs in a three-level rectifier need to have only 300-, 600-, and 850-V blocking voltages for the same application. However the circuit complexity as the main drawback will not be wiped out. It seems, the use of multilevel convertors in low-voltage low-power utility application will be more attractive by increasing the costs of energy and decreasing the cost of semiconductor switches. In this chapter the low-voltage low-power IGBT based three-level NPC topologies will be considered as a solution for two-level low-power conventional IGBT based converters3. 1

Nominal line-line voltage up to 690 Vrms (IEC) and 575 Vrms (ANSI) [24] Roughly 1/3rd of the entire converter volume is taken by passive filter components; According to [24] 3 The very high switching frequency and very low power and voltage applications based on MOSFETs or other transistor types (f>50kHz) are not included in this research. However in the low-power high frequency range 3-level MOSFET-based inverters are a good alternative to 2-level. The important problem is power loss introduced by the reverse recovery of MOSFET body diode. A technique of avoiding reverse recovery loss of MOSFET body diode in a 3-level NPC is suggested by [Banerjee, D. , Multilevel inverters for low-power application, 2011]. 2


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3.2 Basic Topology: Three-level NPC


[3,5,10,24]

The multilevel topology which is discussed in literatures for low voltage low power application is the diode-clamped 3-level converter known as Neutral Point Clamped (NPC), as shown in fig. 17. Compared to the two-level VSC, three-level NPC needs 2 extra IGBTs, 4 additional diodes, and two additional gate drivers. NPC converters for low voltage applications are now in production by many companies such as YASCAWA, INFINEON, POWEREX, and SEMIKRON.

Vout Vout

(d)

(b)

(c)

(a)

Figure 17: Three Level NPC (a) One leg (b) Leg output voltage (c) Three-phase topology (d) Phase to phase output voltage [5]

The switching states of one leg of NPC shown in 17(a) are listed in table 2. It allows to conclude that Q2 and Q3 stay turned on most of the cycle, and so resulting in a less switching loss and contrary in an higher conduction loss, compared to Q1 and Q4. [5]

Table 2: The switching states for the four IGBTs of fig. 16(a) [5]

The advantages and disadvantages of multilevel converters over two-level topology discussed in chapter 2 part 3, are also valid for low power three-level NPC. Besides, the semiconductor switching losses in low-voltage three-level NPC application are lower than two-level at the RESEARCH PROJECT, H.AMIRI, DEC. 2012

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switching frequency higher than 5…10KHz (different references [10,11,12] shows different results). Three-level NPC has advantage and disadvantages for low-power low-voltage application compared to other multilevel converter topologies described in chapter 2, as follow. [3,10,24] Advantages: 

Less number of capacitors and switches compared to other major multilevel topologies.

Disadvantages: 

The problem of reverse recovery feature of clamping diodes; i.e. more conduction losses for IGBTs.



Unequal loss distribution among semiconductors and so unsymmetrical chip temperature (this problem can be solved by new topologies using redundant switches; see 3.4)



The balancing problem of capacitors and therefore the need for dc-link center point management (although by advanced modulation method it is possible to solve it)

Note that the disadvantages can be eliminated by applying other NPC-based topologies described in 3.4 and/or new modulation strategies.

3.3 Modulation Methods [3,7,15] Essentially the modulation methods described in 2.6 for high power voltage source converters can be applied to low power topologies. Moreover reference [3] describes three main modulation methods for medium and high voltage three-level NPC Converters. These methods are: 1) Carrier-based PWM; 2) Space Vector Modulation (SVM); and 3) Selective Harmonic Elimination (SHE), as be arranged at fig. 18. This time we will consider again the function of the first two methods but particularly at 3-level NPC topology. The SHE method would not be useful because it is basically a fundamental switching frequency method and more efficient in higher-level topologies.


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Figure 18: Modulation methods for three-level diode-clamped inverter. [3]

1- Carrier Based-PWM (CB-PWM) method for a three-level NPC leg (fig. 19(a)), is based on comparing a sinusoidal reference υ∗ with υcr1 and υcr2 (carrier signals) as can be seen in fig. 19(b).

Figure 19(a): Diode-clamped NPC Leg [3]

The logic of control process is very simple: if υ∗ > υcr1

⇒ Sa1 = 1, Sa2 = 1,

υaN = +Vdc/2

if υcr2