New Approach to VLSI Buffer Modeling, Considering Overshooting Effect

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New Approach to VLSI Buffer Modeling, Considering Overshooting Effect Milad Mehri, Mohammad Hossein Mazaheri Kouhani, Nasser Masoumi, and Reza Sarvari Abstract— In this brief, we use the alpha power law model for MOS devices to reach a more accurate modeling of CMOS buffers in very deep submicrometer technologies. We derive alpha model parameters of a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE simulations. By analytical efforts we find the output resistance of a minimum-size buffer and compare it with those extracted from HSPICE simulations. We propose a new model for the output resistance of a givensize buffer in any technology, which demonstrates 3% error on average as opposed to the conventional model. Also a new buffer resistance is proposed analytically and numerically to calculate the crosstalk for interconnect analysis applications. In addition, we propose a model for the transfer function zero generated by the gate-drain capacitances of MOS transistors, which cause the overshooting effect, and develop an accurate expression for modeling this phenomenon. As the final point, together with the input-to-output capacitance, the equivalent output resistors present a simple and accurate macromodel for the CMOS buffer. Index Terms— Alpha-power law, buffer overshooting effect, CMOS buffer modeling, VLSI buffer.

I. I NTRODUCTION VLSI circuit analysis in the circuit level for the most important measurements, such as delay and power consumption, depends on rigorous modeling of their basic components. One of the most prevailing and underlying elements in digital systems is the CMOS buffer. A buffer is a simple but principal and critical component and, as such, has many significant applications and is vastly used for signal cleaning and the reduction of delay, noise, and crosstalk. This buffer is popular because of its low power consumption, mainly in switching phases. With the scaling of CMOS technology into the very deep submicrometer (VDSM), buffer modeling has been a critical demand due to its many appearances in the design and analysis of digital systems. Accurate modeling of this core component can result in a better inspection through the system, whereas the model’s simplicity can cause a fast design time. Hence, many researchers have addressed this need by proposing various analytical models to present the behavior of CMOS buffers. Propagation time delay and power dissipation of buffer are its major factors that are modeled. However, in some works, the inputto-output capacitance, which results in overshoot and undershoot effects, has not been taken into account [1]–[5] while some others have incorporated this effect. In [6]–[11], power estimation models of a CMOS buffer, accounting for the influence of the input-to-output coupling capacitance of the buffer in submicrometer technologies, were given. In [6], [12]–[15], the nonlinearity induced by the inputto-output coupling capacitance is taken into account for the analytical modeling of the gate propagation delay time. The time duration when the output gets out of the steady-state value of the signal level for the first time is known as overshoot time. This parameter is currently one of the key parameters while coping with buffers, since it is Manuscript received September 10, 2011; revised April 4, 2012; accepted July 21, 2012. Date of publication August 31, 2012; date of current version July 22, 2013. M. Mehri, M. H. M. Kouhani, and N. Masoumi are with the Department of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran (e-mail: [email protected]; [email protected]; [email protected]). R. Sarvari is with the Sharif University of Technology, Tehran 16846-13114, Iran (e-mail: [email protected]). Digital Object Identifier 10.1109/TVLSI.2012.2211629

Fig. 1.

CMOS buffer.

comparable to conventional propagation delay of the buffer [14]. We have presented an expression for this parameter based on our novel macromodel of the overshooting effect. The nonlinear operation of a MOS transistor results in nonlinear resistance and capacitance in the model. Averaging these parameters in time interval when the input signal changes is a typical solution which is used in this brief. Technology transportability is an advantage of this model which most of the models may lack. The analytical model for delay in [16] benefits from the advantage of portability. Likewise, in this brief, we develop a closed-form expression to estimate the output resistances of a CMOS buffer. This model depends on device technology parameters and the input signal transition time. Therefore, there is no need for fitting or extracting parameters, which makes the developed model technology portable. What distinguishes this brief from the others is the fact that most of the overshoot models [6]–[15] have used the dynamic behavior equation of an inverter derived from Kirchhoff’s Current Law (KCL) at the output node. In contrast, our new proposed overshoot model is based on intuition and curve fitting, simultaneously, still completely in analytical form. This brief is organized as follows. The alpha power modeling is discussed in Section II. The output resistance of the buffer, and the relevant derivations and integration expressions are addressed in this section. Analytical expressions for the newly proposed model are presented in Section III. Additionally, simulations and verification procedures are performed in this section. In Section IV, the overshooting effect is modeled as a zero generated by the input-to-output coupling capacitance of MOS transistors in the transfer function. Finally, summary and conclusion are provided in Section V. II. A LPHA P OWER M ODELING In VDSM, the Shockley transistor model is no longer valid. This happens because of short channel effects such as mobility degradation, drain-induced barrier lowering, and velocity saturation. Therefore, in order to accomplish a better analysis, a more accurate model is required. As such, we utilize the current–voltage characteristic of an MOS transistor expressed in [1] and [2] as follows: iD = ⎧ β (v GS −v TH ) ⎪ ⎪ × [1 − exp(−βv DS )], @ sub.thr e. ⎨ksub × e η α kl (v GS − v TH ) 2 v DS , @ lin. ⎪ ⎪ ⎩k (v − v )α (1 + λv ), @ sat. s GS TH DS

(1)

A conventional CMOS buffer (simply an inverter) is made of NMOS and PMOS transistors, as depicted in Fig. 1. The Cin , Cout , and Rout model the equivalent input and output capacitances of the transistors, and the output equivalent resistance, respectively. For timing analysis, all these model elements must be averaged in time when the input signal transits between two

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TABLE I R ESULTS OF BALANCING THE B UFFER

(a) Fig. 2.

(b)

Tech.

W n /Lmin

W p /Lmin

tpHL = tpLH = t pd (ps)

90 nm

1.5

3.452

7.443

65 nm

1.5

3.997

8.264

45 nm

1.5

4.542

9.164

Buffer input Vin . (a) Rise. (b) Fall.

low and high values. The Rout can be written as  +  1 T  Vds  dt Rout = T 0  iD 

(a)

(b)

(c)

(d)

(2)

where T is the time needed for the input to settle to Vdd or gnd. For the input signal, we consider a ramp input as in Fig. 2(a) and (b) ⎧ t ≺0 ⎨ 0, 0 ≺ t ≺ tr Vin = ( ttr ) × Vdd , ⎩ Vdd , t  tr ⎧ t ≺0 ⎨ Vdd , t 0 ≺ t ≺ tf (3) Vin = (1 − t f ) × Vdd , ⎩ 0, t  tf. During the transition in the input signal, the transistors change their operating regions. The actual operating regions (linear or saturation) in the time interval depend on the type of load driven by the buffer [17]. In this brief, we have supposed a pure capacitive load, for NMOS and PMOS transistors of the buffer. At the beginning of the rising input, the PMOS transistor is in the subthreshold region. The effect of this current is considerable in VDSM CMOS technologies discussed in [15] and [11]. Accordingly, due to the complexity of integration from subthreshold current, we start the interval of integration from a new parameter ε instead of zero. This assumption enables us to keep the subthreshold region away from the interval of the integration. The ε parameter depends on the device technology, which in this brief is supposed to be 1% of the rise time. We also suppose that the output is just the inverted input with zero delay. By this assumption, performing the integration and simplifying the results, we have

 1 RNMOS,fall = RNMOS,rise = vt n + ε ) 1 − ( vdd tr  6 (Vdd−Vdssatn −Vtn)1−α ·(Vdd −(α−1)Vdssatn −Vtn) × V dd · ksn(α − 2)(α − 1) ! " ε ε −1)+2− ε )) 1−α ( Vdd) ((α−2)Vtn +Vdd(α( tr tr − tr V dd · ksn(α − 2)(α − 1) ! α α "7 2(Vdd −Vdssatn − Vtn)1− 2 −2(Vdd −Vtn)1− 2 . + V dd(α − 2)kln (4) 

1 RPMOS,fall = RPMOS,rise = t p| ε 1 − ( |V V dd + tr ) 6  (Vdd−vsdsat p−|V t p|)1−α·(Vdd−(α−1)V sdst p−|V t p|) × V dd · ksp(α − 2)(α − 1) " ! ε ε ε 1 −α ( tr Vdd) (Vdd·(1−|Vtp| Vdd − tr )−2Vdd+2|Vtp|+ tr Vdd) + V dd·K sp(α − 2)(α − 1) ! α α "7 2(Vdd − V sdsat p−|Vtp|)1− 2 −2(Vdd −|Vtp|)1− 2 . + V dd(α − 2)K ln (5)

Fig. 3. (a) Single CMOS buffer. (b) Simple RC model for (a). (c) Cascaded buffers. (d) RC model for (c).

Although it would be beneficial to have equal input rise and fall times, which is one assumption of this brief, we have also taken the output as just the inverted form of the input. This results in the equality of RNMOS,fall and RNMOS,rise and also the equivalence of RPMOS,fall and RPMOS,rise . The output resistances of the buffer Rout,fall and Rout,rise for the rising and falling input can be written as follows: RNMOS,fall + RPMOS,fall Rout,fall = (6) 2 RNMOS,rise + RPMOS,rise . (7) Rout,rise = 2 III. S IMULATION AND V ERIFICATION The alpha power law parameters of the buffer transistors for 3-nm technology nodes utilizing predictive technology model parameters discussed in [18] and [19] have been extracted using HSPICE simulations. In order to reach the minimum transistor sizes of the buffer to use minimum area for the buffer, we need another constraint rather than assuming 1.5 for the size of the NMOS transistor. The size of 1.5× Lmin for the width of NMOS is the minimum achievable size in drawing layout, based on Lambda scalable model. The constraint we use to obtain the minimum size of the PMOS is to make the propagation delay of the buffer symmetric. By using this constraint, we obtain the size of the PMOS. Table I carefully demonstrates the size of the PMOS transistor in three different process technologies. So as to obtain the values of Rout , Cout , and Cin , three steps are used. 1) Averaging the |Vds /Ids | through the rise and fall times using HSPICE to obtain the average resistance of the inverter, Rout . This averaging is done based on multiple loads and different sizes of buffer transistors. 2) Using (8) to obtain Cout having the values of Rout and tpd−self from HSPICE simulations. The structure used in this step and its equivalent circuit are shown in Fig. 3(a) and (b). Based on [20], for tpd−self we have tpd−self = Ln(2) × Rout Cout = 0.69 × Rout Cout . (8) 3) Using (9) to calculate Cin having the values of Rout , tpd , and Cout . The structure used in this step and its equivalent circuit

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TABLE II M INIMUM B UFFER O UTPUT C APACITANCE , I NPUT C APACITANCE , AND O UTPUT R ESISTANCE

TABLE V P ERCENTAGE E RROR OF A GREEMENT B ETWEEN Rout AND HSPICE

Tech.

90 nm

65 nm

45 nm

(10)

Tech.

90 nm

65 nm

45 nm

C out,fall

0.534 fF

0.423 fF

0.304 fF

Rout0

7608

11 880

20 790

C out,rise

0.891 fF

0.632 fF

0.439 fF

0.00%

30.50%

10.31%

C out_buffer = (C out,fall + C out,rise )/2

Min. %Err.

0.713 fF

0.528 fF

0.372 fF

0.24%

51.99%

17.08%

C in,fall

0.402 fF

0.289 fF

0.211 fF

Max. %Err.

C in,rise

0.546 fF

0.327 fF

0.195 fF

Avg. %Err.

0.03%

45.55%

16.41%

C out_buffer = (C in,fall + C in,rise )/2

0.474 fF

0.308 fF

0.203 fF a

0.002

0.073

0.086

RNMOS

7.50 k

12.50 k

20.94 k

Rout0

7621

12 620

21 480

RPMOS

11.51 k

16.82 k

25.79 k

Rbuffer = (RNMOS + RPMOS )/2

0.00%

0.03%

0.01%

9.50 k

14.65 k

23.36 k

Min. %Err. Max. %Err.

51.92%

42.57%

28.81%

Avg. %Err.

17.02%

13.30%

8.76%

(12)

TABLE III A NALYTICAL R ESULTS FOR NMOS, PMOS, AND B UFFER

(13)

Tech.

90 nm

65 nm

45 nm

a

0.305

0.089

0.123

RNMOS,fall

7.41 k

12.53 k

20.69 k

Rout0

7740

12 260

20 940

RNMOS,rise

7.41 k

12.53 k

20.69 k

RPMOS,fall

11.41 k

16.92 k

25.49 k

Min. %Err.

0.03%

0.04%

0.13%

RPMOS,rise

11.41 k

16.92 k

25.49 k

43.83%

30.04%

9.41 k

9.41 k

9.41 k

Max. %Err.

51.23%

Rout,fall Rout,rise

14.73 k

14.73 k

14.73 k

16.90%

14.32%

9.79%

Rbuffer = (Rout,fall +Rout,rise )/ 2

23.09 k

23.09 k

23.09 k

Avg. %Err. a

0.004

0.004

0.003

Rout0

7130

11 730

20 000

Min. %Err.

0.00%

0.00%

0.01%

Max. %Err.

32.88%

19.79%

9.75%

Avg. %Err.

9.85%

5.89%

2.67%

TABLE IV C OMPARISON B ETWEEN HSPICE AND A NALYTICAL R ESULTS Tech.

Error = (Rbuffer,HSPICE −Rbuffer,Analytic)/Rbuffer,HSPICE

90 nm

0.95%

65 nm

−0.55%

45 nm

1.16%

are shown in Fig. 3(c) and (d). Based on [20], for tpd we have tpd = Ln(2) × Rout (Cin + 2Cout ) = 0.69Rout (Cin + 2Cout ).

Rout0 , k

Cout = kCout0 ,

where k=

WN WP = WP0 WN0

Cin = kCin0

are as follows: Rout0 √ (12) k+a k Rout0 Rout =  (13) k 2 + ak Rout0 (14) Rout = × eak . k Table V presents the results obtained from curve fitting for these models compared with HSPICE simulations. For modeling crosstalk on neighboring interconnects in VLSI, one should find the value of Rout in coupling situation. When the buffer of the quiet line, known as victim line, is tied to Vdd or gnd, the NMOS or PMOS transistor, respectively, is ON and is operated in the deep triode region. Therefore, the value of Rout depends on the transition of the signal on the quiet line, and new expressions must be used. The deep triode region resistance is depicted by RON , and can be expressed as follows: v DS v DS RON_N = = α i D |v GS =v DD klN (v GS − v TH ) 2 v DS 1 = (15) α klN (v DD − v TH ) 2 Rout =

(9)

Inserting the model parameters from simulation into the analytical expressions (4)–(7) for the resistors, we obtain the results summarized in Tables II and III. Table IV shows a comparison between HSPICE simulation results and those obtained from the analytical expressions. As it can be seen from this table, the error is less than 2% for 45 nm. The conventional model for an inverter of the size k with respect to a minimum-size inverter in a given technology is given as follows: Rout =

(14)

(10)

(11)

and WN0 and WP0 are the minimum NMOS and PMOS transistor sizes, respectively. Based on the HSPICE simulation results shown in Table V, as the technology shrinks, the error of (10) decreases. The new relations that are based on curve-fitting results for Rout

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TABLE VI RONN AND RONP FOR 90-, 65-, AND 45-nm T ECHNOLOGIES Tech.

HSPICE

(15) and (16)

%Error

RON_N 90 nm

2.18 k

3.01 k

38%

65 nm 45 nm

3.42 k

5.12 k

50%

6.17 k

10.20 k

65%

RON_P 90 nm

Fig. 4.

3.50 k

4.82 k

38%

65 nm

5.61 k

8.17 k

46%

45 nm

10.79 k

16.61 k

54% Fig. 5.

Comparison between HSPICE simulation and (17).

Fig. 6.

Comparison between HSPICE simulation and (18).

Accurate model for CMOS buffer.

RON_P =

v SD v SD = α i D |v SG =v DD klP (v SG − |v TH |) 2 v SD 1 = α . klP (v DD − |v TH |) 2

(16)

In Table VI we have summarized the results obtained from HSPICE and analytical expressions for RON_N and RON_P for 90-, 65-, and 45-nm technologies.

It may also damage the load buffer if it exceeds the breakdown voltage of MOS in VDSM Vout,rise(t) = Vdd × (1 + k exp(−at) − (k + 1) exp(−bt)) (17) Vout,fall (t) = Vdd × (−k exp(−at) + (k + 1) exp(−bt))

(18)

where IV. M ODELING THE OVERSHOOTING E FFECT Due to the gate-to-drain capacitance of MOS transistors Cgd , the input can couple directly to the output. By taking such an influence into effect, we reach to an equivalent circuit for the buffer involving the average output resistors as well, as illustrated in Fig. 4. In this circuit, the transistors are modeled as switches, which are closed or open depending on the input ramp, falling or rising for the PMOS and vice versa for the NMOS. By carefully analyzing the circuit shown in Fig. 4, we find that it would result in the output waveform as an outcome. However, the classic method of finding the transfer function using the dynamic behavior equation of an inverter derived from KCL at the output node would be a laborious. Besides, the topology of the circuit in Fig. 4 varies several times as the input rises or falls. This leads to a multistatement expression for the output waveform. On the other hand, the exact times that the circuit topology varies are also extra parameters, which must be calculated depending on many characteristics of the circuit. Accordingly, by intuition we have modeled the output waveform by simple and accurate expressions [(17) and (18)], which comprised two poles and a zero. These simple expressions, modeling the overshooting effect, are verified to be in a good agreement with the HSPICE results. For modeling this fact, we have assumed that Vout can be written as (17) and (18) for step fall and rise inputs, respectively. As it can be seen from Fig. 5, the effect of zero makes the Vout fall down to 40 percent of Vdd for the CMOS buffer in 90-nm technology. This phenomenon produces error in estimating the propagation delay.

a=

1 + CCout gd

Rout Cgd

,

b=

Rout 2

1 , (C out +C L )

C out k = (C +C . out L +C gd )

(19) The parameters a, b, and k are achieved by intuition and curve fitting, simultaneously. Figs. 5 and 6 show the Vout of the buffer with C L = 1 fF, simulated by HSPICE and calculated using (17) and (18) for the falling and rising input for the 90-nm technology node

 ak 1 Ln (20) tOvershoot = tUndershoot = a−b b (k + 1)

 a ak VOvershoot = Vdd × 1 + k exp Ln b−a b (k + 1) 

b ak (21) −(k + 1) exp Ln b−a b (k + 1)

 a ak VUndershoot = Vdd × −k exp Ln b−a b (k + 1) 

b ak . (22) +(k + 1) exp Ln b−a b (k + 1) V. C ONCLUSION In this brief, we studied buffer modeling and derived an expression for minimum-size buffer resistance. In CMOS buffer modeling, we employed alpha power law expression for MOS devices. HSPICE simulations showed that using the alpha power model for the MOS

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in buffer leads to very accurate results. This error was less than 2% for 45-nm process technology. Also a new expression was proposed for a buffer of k-size relative to the minimum buffer size. The average error of the proposed model for 45-nm technology was less than 3%, while with the conventional model error was 10% compared to the HSPICE simulations. Also a new resistance was introduced for the buffer that can be used in calculation of crosstalk. Eventually, we improved our macromodel by taking into account the influence of the overshooting effect which was modeled as a zero generated by the input-to-output coupling capacitance of MOS transistors in the transfer function of the component. R EFERENCES [1] T. Sakurai and A. R. Newton, “Alpha power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25, no. 2, pp. 584–594, Apr. 1990. [2] K. A. Bowman, B. L. Austin, J. C. Eble, X. Tang, and J. D. Meindl, “A physical alpha power law MOSFET model,” IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1410–1414, Oct. 1999. [3] E. A. C. Costa, F. P. Cortes, R. Curdoso, L. Carro, and S. Bumpi, “Modeling of short circuit power consumption using timing-only logic cell macro-models,” in Proc. 13th Symp. Integr. Circuits Syst. Des., 2000, pp. 222–227. [4] S. Ulman, “Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers,” in Proc. IEEE Int. Symp. Circuits Syst., vol. 5. May 2003, pp. 269–272. [5] S. Dutta, S. S. Shetti, and S. L. Lushy, “A comprehensive delay model for CMOS inverters,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 864–871, Aug. 1995. [6] L. Bisdounis, S. Nikalaidis, and O. Koufopavlou, “Propagation delay and short-circuit power dissipation modeling of the CMOS inverter,” IEEE Trans. Circuits Syst., vol. 45, no. 3, pp. 259–270, Feb. 1998. [7] S. Turgis and D. Auvergne, “A novel macro-model for power estimation in CMOS structures,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 17, no. 11, pp. 1090–1098, Nov. 1998.

[8] L. Bisdounis and O. Koufopavlou, “Short-circuit energy dissipation modeling for sub-micrometer CMOS gates,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 9, pp. 1350–1361, Sep. 2000. [9] J. L. Rossello and J. Segura, “Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 4, pp. 433–448, Apr. 2002. [10] L. Bisdounis, “Short-circuit energy dissipation model for sub-100nm CMOS buffers,” in Proc. IEEE Int. Conf. Electron. Circuits Syst., Athens, Greece, Dec. 2010, pp. 615–618. [11] A. Bani-Ahmed, “The impact of modeling the overshooting effect in subthreshold region for nano-scale CMOS inverter,” in Proc. 7th Int. Conf. Innov. Inf. Technol., Apr. 2011, pp. 342–345. [12] K. O. Jeppson, “Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance of the CMOS inverter delay,” IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 646–654, Jun. 1994. [13] J. M. Daga and D. Auvergne, “A comprehensive delay macro modeling for sub-micrometer CMOS logics,” IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 42–55, Jan. 1999. [14] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Noue, “Modeling the overshooting effect for CMOS inverter delay analysis in nanometer technologies,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 2, pp. 250–260, Feb. 2010. [15] Y. Wang and M. Zwolinski, “Analytical transient response and propagation delay model for nano-scale CMOS inverter,” in Proc. IEEE Int. Circuits Syst. Symp., May 2009, pp. 2998–3001. [16] A. Kabbani, D. Alkhalili, and A. J. Al-Khalili, “Technology portable analytical model for DSM CMOS inverter delay estimation,” IEE Proc. Circuits Device Syst., vol. 152, no. 5, pp. 433–440, Oct. 2005. [17] G. Cappuccino, “Operating region modeling of deep-submicron CMOS buffers driving global scope inductive interconnects,” in Proc. Euromicro Symp. Digital Syst. Design, Sep. 2003, pp. 138–143. [18] W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45 nm early design exploration,” IEEE Trans. Electron Device, vol. 53, no. 11, pp. 2816–2823, Nov. 2006. [19] Predictive Technology Model (2011). [Online]. Available: http://ptm.asu.edu/ [20] J. N. Rabaey, Digital Integrated Circuits. Englewood Cliffs, NJ: Prentice Hall, Jan. 2003.