Nonvolatile Memristor Memory - Electrical Engineering, Technion

Nonvolatile Memristor Memory: Device Characteristics and Design Implications Yenpo Ho

Garng M. Huang

Peng Li

Dept. of ECE Texas A&M University College Station, TX 77843



linear, the element is referred to as memristance, which can be charge-controlled [3]:

ABSTRACT The search for new nonvolatile universal memories is propelled by the need for pushing power-efficient nanocomputing to the next higher level. As a potential contender for the next-generation memory technology of choice, the recently found “the missing fourth circuit element”, memristor, has drawn a great deal of research interests. In this paper, we characterize the fundamental electrical properties of memristor devices by encapsulating them into a set of compact closed-form expressions. Our derivations provide valuable design insights and allow a deeper understanding of key design implications of memristor-based memories. In particular, we investigate the design of read and write circuits and analyze data integrity and noise-tolerance issues.

M (q ) = dϕ dq

(1)

Fig. 1 Four fundamental circuit elements. Similarly, when the q-ĳ relation is flux-controlled and the element is called memductance [3]:

1. INTRODUCTION

W (ϕ ) = dq dϕ

Low-power high-density memory devices are critical to a very wide range of integrated applications. With IC technology scaling, there exists a great interest in searching for the next generation of universal memories, which are able to ubiquitously replace traditional SRAM, DRAM and nonvolatile memories such as flash memory [1].

(2)

The memristor devices demonstrated in [2] is in the form of general memristive systems:

Very recently, a new device with pinched hysteresis was demonstrated [2], which was recognized as the first reallife realization of the so-called missing fourth circuit element, memristor, whose existence was theoretically predicted by L. Chua in 1971 [3]. The well-understood basic circuit elements, resistance, capacitance and inductance, describe the relations between fundamental electrical quantities: voltage, current, charge and flux [3-4]. Resistance relates voltage and current (dv=R.di), capacitance relates charge and voltage (dq=C.dv), and inductance relates flux and current (dĳ=L.di), respectively. As shown in Fig. 1, Chua argued that there is a missing link between flux and charge (dĳ=M.dq), which he called memristance M [3].

v = R ( w, i ) ⋅ i

(3)

dw dt = f ( w, i )

(4)

where w is a set of state variables, and R and f can be explicit functions of time. It has been shown that prototyped memristor devices can be scaled down to 10nm or below and the memristor memories can achieve an integration density of 100Gbits/cm2, a few times higher than today’s advanced flash memory technologies. In addition, the nonvolatile nature of memristor memory makes it an attractive candidate for the next-generation memory technology. As an emerging device, memristors have a very unique set of device characteristics, which have not been fully analyzed, particularly from a design point of view. In this paper, we start from the reported very basic memristor device models and derive a set of closed-form design equations. Our equations succinctly capture the memristor behaviors in a way relevant to memory operations and provide clear design insights. By utilizing the design guidance derived from our closed-form expressions, we propose suitable memory read and write schemes. We discuss the unique circuit design, noise margin and data

While in the linear case, memristance becomes constant which acts like resistance. However, if ĳ-q relation is nonPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ICCAD’09, November 2–5, 2009, San Jose, California, USA. Copyright 2009 ACM 978-1-60558-800-1/09/11...$10.00.

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integrity issues arisen from the fundamental memristor device characteristics. We present in-depth analysis and suggest circuit design solutions to achieve reliable read and write operations. The proposed analyses and designs are verified by comprehensive simulation.

2. BASIC MEMRISTOR MODELS

Fig. 2

Memristor device structure and circuit model.

Fig. 2. shows the physical structure of a memristor device along with its equivalent circuit model [2]. The device is an electrically switchable semiconductor thin film sandwiched between two metal contacts. The semiconductor thin film has a certain length D, and consists of a doped and un-doped region. The internal state variable w represents the length of the doped region. The doped region has a low resistance while that of the un-doped region is much higher. As an external voltage bias v(t) is applied across the device, the length w will change due to charged dopant drifting [5]. Hence, the device’s total resistivity changes. If the doped region extends to the full length D, that is w/D=1.0, the total resistivity of the device would be dominated by low resistivity region, with a value measured to be Ron. Likewise, when the un-doped region extends to the full length D, i.e. w/D=0, the total resistance is denoted as Roff. Thus, the mathematical model for memristive device resistance can be described as [2]:

R( w) = (Ron ⋅ w D + Roff ⋅ (1 − w D) )

(5)

In the perspective of memristive systems, the following are established:

v (t ) = R ( w) ⋅ i (t )

dw(t ) dt = μ v ⋅ Ron D ⋅ i (t )

(6) (7)

where μv is the average ion mobility. Integrating (7) yields the instantaneous w(t):

w(t ) = w 0 + μ v ⋅ R on D ⋅ q (t )

(8)

where w0 is initial state for state variable w. Plugging (8) into (5) gives a simple expression for the charge-controlled memristance:

M (q ) = Roff −

( Roff − Ron ) § μ R · ¨ w0 + v on ⋅ q(t ) ¸ (9) D D © ¹

As a special case w0=0 and Ron being small enough that (Roff-Ron)§Roff, charge-controlled memristance can be simplified into:

486

§ μ R · M (q) = Roff ⋅ ¨1 − v 2on ⋅ q(t ) ¸ D © ¹

(10)

3. PROPOSED DESIGN EQUATIONS Starting from the established device characteristics shown in the previous section, we derive a set of compact closed-form expressions that provide important design guidance, which is employed in the following sections. In particular, we show how the memristance can be controlled by the applied flux and we achieve the same goal for the memristor state. Note that the flux is the integral of the applied voltage. These developments provide a critical basis for us to understand the role of the applied voltage in read and write operations of a memristor memory cell.

3.1 Memristor State Equation Denote ȕ the off/on ratio ( Roff=Ron ȕ). Equations (7) can be rewritten as:

dw dt = μ v ( Dβ − w ⋅ ( β − 1)) ⋅ v

(11)

After certain manipulations using differential calculus, it leads to: w(t ) =

2 ª º § 2( β − 1) Dβ « β −1 · w0 ¸¸ − ⋅ μ v ⋅ ϕ (t ) » 1 − ¨¨1 − 2 Dβ » ( β − 1) « ( Dβ ) © ¹ ¬ ¼

(12)

Since ȕ is normally large, Equation (12) can be further simplified: 2 ª w · ϕ (t ) º» β ⋅ D 2 (13) § w(t ) = D «1 − ¨1 − 0 ¸ − where Φ D = D¹ ΦD » 2 ⋅ μv « © ¬ ¼

Equation (13) shows an explicit dependency of the internal variable w(t) on the applied flux. Note that this formula clearly indicates that w(t) is a function of the flux applied; it indirectly depends on the voltage across memristor. Voltage waveforms with the same flux can lead to the same memristor state. Due to the finite length D of the thin film, the internal memristor state is constrained as: 0w(t)D, which corresponds to the following flux range: −

β 2μ v

(D

2

)

− (D − w0 ) ≤ ϕ (t ) ≤ 2

β 2μ v

(D − w0 )2

(14)

As a result, the memristor state stays at the full length D if the applied flux is over the upper limit, and stays at zero if the flux is under the lower limit. Applying flux across memristor would create charges through memristor, the q-ĳ relationship is expressed as: q(ϕ ) =

D2 μν ⋅ Ron

2 ª§ w · ϕ w «¨1 − 0 ¸ − §¨1 − 0 ·¸ − Φ D D «© ¹ © ¹ D ¬

2009 IEEE/ACM International Conference on Computer-Aided Design Digest of Technical Papers

º » » ¼

(15)

According to the definition of memristance [3], the fluxcontrolled memristance is:

4.2 Memristor Memory Write Operation

2

M (ϕ ) = R off

ϕ § w · ⋅ ¨1 − 0 ¸ − D¹ ΦD ©

(16)

Moreover, one unique property of the memristor is that the internal state w(t) will always come back to the same place as long as the next flux applied is zero if equation (14) is satisfied, regardless its initial state w0. This property plays an essential role in memristor memories.

3.2 Summary of Memristor Properties for the Design of Read and Write Circuits In summary, a memristor that behaves according to (6) and (7) has the following properties: 1.

Memristance is dependent on the initial state w0 .

2.

For voltage source input, the change to memristance would be the same regardless voltage waveform as long as the net flux is the same.

3.

For an arbitrary voltage input satisfying the constraint in (14), as long as the net flux injection is zero, w(t) will move back to the original position.

Fig. 4

To write a logic value to a memristor cell, one simple way is having a structure in Fig. 4(a). Assume initially the state is an ideal logical zero, w(0)=w0=0, and it is desirable to write an ideal logic one, w(t)=D. Consider a positive square-wave pulse Vin that has amplitude VA and duration Tw1 as shown in Fig. 4(b) for the write process. Rewriting (13), we express the flux in terms of state w(t) as

ϕ (t ) =

w w(t ) 2 º β ⋅ D2 ª (1 − 0 ) 2 − (1 − ) 2μ v «¬ D D »¼

(17)

Accordingly, for a given VA, the time needs for an internal state to reach D is given as Tw1, w 0 ≥

4. PROPOSED CIRCUIT DESIGN Based on the derived insights, in this section, we propose read and write schemes for memristor memories and discuss the associated circuit design issues associated with read, write stabilities and data integrity.

(a) Write operation structure, and (b) write signal patterns.

ΦD VA

where Φ D =

β ⋅ D2 2μ v

(18)

Therefore, a pulse width larger than time Tw1 is able to guarantee the state to reach the ideal one. Similarly, the pulse width Tw0 to write an ideal logic zero is also the same. Thus, a write signal that has duration equal or larger than (18) can insure a successful write. However, the memristor state only needs to pass OH to be logic one and under OL to be logic zero. The pulse width does not have to be as long as (18). The state transition times from “0” to OH and “1” to OL may be different. Thus, the required time for a successful write should take the maximum from them. Tw1,w 0 ≥

Fig. 3

(a) Memristor output levels, and (b) memristor 3D nano-structure.

ΦD ⋅ max (1 − (1 − O H ) 2 , (1 − O L ) 2 ) (19) VA M (ϕ )

4.1 Output Levels For simplicity, we can define a memristor is at logic zero when 0