OpenCV Accelerator

IMS Institute of Microelectronic Systems Leibniz Universität Hannover

A General Purpose FPGA-Accelerator with Standard USB 3.0 Interface Jörn Rath, Jan Dürre, Holger Blume {rath,duerre,blume}@ims.uni-hannover.de

Performance

Challenge Easy to use soft- and hardware interface Utilization of USB 3.0 performance

100 Throughput [MB/s]

Introduction FPGAs are well established as accelerator components due to their high flexibility and performance Only a few standard interfaces (e.g. PCI Express, HSMC) meet the latency and data rate requirements in PC-system scenarios Many standard systems, such as Notebooks, do not support such interfaces inherently The new USB 3.0 standard is suitable for low latency and very high data rate applications

1000

10

185 MB/s

1 0,1 0,01

Transfer size [Bytes]

100000 Relative latency [ms/MB]

FPGAs as Accelerators

10000

1000

5,41 ms/MB

100 10

1

Transfer size [Bytes]

Implementation

Figure 3: Performance Benchmark Results

Host PC User Application

FPGA

C++ Accelerator Library

USB 3.0

Cypress FX3 USB 3.0 Peripheral Controller

32 bit bus Interface

User Implementation

Figure 1: Implementation Overview

C++ Accelerator Library Easy to use software interface, only a single function call required USB transfers are handled in autonomous worker thread Cypress FX3 USB 3.0 peripheral controller Slave interface with 32 bit parallel data transfers @ 100 MHz FPGA-Interface User data access through standard FIFO interface USB transfers are handled automatically Cypress FX3 USB 3.0 Peripheral Controller

ALMs used

Registers used

BRAM [bits]

412 Table 1: Hardware Costs for Accelerator-Interface

603

32.768

Very small interface with only ~2% utilization of available ALMs in a Cyclone V E A4 FPGA.

Features High Performance USB 3.0 Data Link Low latency and high throughput link between FPGA and host PC Low hardware costs enable use in small FPGAs Easy-to-use Interfaces C++ software library to access FPGA accelerator over USB 3.0 Standard FIFO interface for user-data access on FPGA

Demo: OpenCV Accelerator Integration of a hardware image filter into an exemplary OpenCV video processing application via USB 3.0.

FPGA Interface

DMA Buffer Buffer 0

FIFO

... Buffer n

USB 3.0 Interface

DMA Buffer

Slave Interface (32 bit)

Transfer Control and Protocol Handler

User Implementation

Video Filtered Video

Buffer 0

... Buffer n

FPGA

Host PC Video Frames OpenCV Application

FIFO

USB 3.0 Filtered Video Frames

Figure 2: FPGA Interface Figure 4: Demonstration Setup 26th International Conference on Field-Programmable Logic and Applications, 29. August - 2. September 2016

Winner of the Innovate Europe Design Contest 2016

Hardware Image Filter