CNES 18,av. E. Belin- 31055 TOULOUSE (France). ***ALCATEL-SPACE-INDUSTRIES 26, av. J.F. Champollion - BP 1187 - 31037 TOULOUSE (France).
OPTIMAL DESIGN OF SOLID STATE MULTICARRIER POWER AMPLIFIERS: J. Lajoinie*, E. Ngoya*, D. Barataud*, J.M. Nebus*, J. Sombrin**, D. Roques*** *IRCOM - University of Limoges- 123, Av. A.Thomas, 87060 Limoges Cedex (France) CNES 18,av. E. Belin- 31055 TOULOUSE (France) ***ALCATEL-SPACE-INDUSTRIES 26, av. J.F. Champollion - BP 1187 - 31037 TOULOUSE (France) **
Abstract - Designing power amplifier for modern comunication systems is a challenging topic. A new design methodology for multicarrier power amplifiers (MCPA) is described which is based on an objective optimality criterion as to linearity and power consumption of amplifier building blocs. Amplifier design results are presented which shows the effectiveness of the methodology.
I. INTRODUCTION Multicarrier amplification in satellite and wireless communications requires a delicate trade-off between linearity and power efficiency, to ensure both minimal crosstalk between channels and DC power consumption. The classical way of dealing with this problem is to build a high efficiency power amplifier (deep class A/B, B and C) and add a linearization circuitry around. Several linearization techniques have been proposed, among which predistortion, feed forward, cartesian feed back and LINC [1]-[4]. All these techniques have in common to generate a complex amplifier with sensitivity issues to linearisation circuit parameters and stability problems that limit the overall bandwidth. And above all, there has been no objective measure of the trade-off between linearity and power consumption. In this paper, a new technique has been experimented where the power amplifier (PA) is designed to satisfy an optimum criterion in terms of linearity and power consumption. The optimization requires only passive matching. The measure of the trade-off between linearity and consumption used here has been introduced for the first time by J. Sombrin [5] a few years ago. As will be shown, this criterion gives an objective measure of the efficiency of a given PA or transistor technology as to multicarrier amplification. We will briefly present this criterion, which we will term C/(N+I) criterion. Based on this we will derive an efficient methodology for characterizing power transistors and amplifiers in terms of linearity and consumption, for multicarrier operation. The transistor characteristics thus obtained provide a complete set of information for designing multicarrier amplifier. The new design technique has been applied successfully for
the design of a 2GHz HFET amplifier, results of which are presented. II. CARRIER OVER NOISE PLUS INTERMODULATION PARADIGM: C/(N+I) CRITERION Ce Output power
Cr
axCe
I e Intermodulation
Ir
ale
Transmitter power amplirier
Transmission channel Attenuation: a
INr: Thermal noise
Receiver
Fig.1 - Communication link budget Considering the illustration of a communication link depicted in Fig. 1 above, the objective of the power amplifier is to provide enough power at the emitter end so that the receiver can pull out the utile signal from the noise. Also one of the major factor in a link budget is the signal over noise (SNR) at the receiver input. Three signal types contribute to this ratio, which are the utile signal Cr, the intermodulation noise coming from the PA Ir and the equivalent thermal noise generated within the transmission channel medium and receiver Nr, so that we can write SNR =
Cr
(1)
Nr +Ir SNR can also be expressed in terms of signal characteristics at the transmitter end, as below. SNR-= Cr (2) Cr l X Ce Nr +Ir Nr OC+ Ir C Ne +Ie Notice that a is the attenuation of the transmission channel, Ce and Ie the utile signal and intermodulation noise transmitted by the transmitter PA. Ne = Nr /a is a very important factor which can be viewed as the equivalent thermal noise at the PA output with a transmission channel and receiver considered as noiseless. Now we may state that a PA has the optimum efficacy for multicarrier operation, if it is satisfying the specified
SNR of the communication link, with the minimum power consumption. Hence SNR at the receiver input and PA power consumption are the two main parameters in consideration for MCPA design. The sole figures Ce fIe and power efficiency (PAE) usually considered are not always sufficient condition, they need to be balanced with the transmission channel noise. Also, as we are dealing with multicarrier systems, the best measure of carrier over intermodulation ratio is the noise power ratio (NPR) [6].
III. CHARACTERIZING POWER TRANSISTOR OR AMPLIFIER CELL FOR LINEARITY AND POWER CONSUMPTION: C/(N+I) CHART As we have seen optimum design of a PA needs to be conducted from the knowledge of the three main factors which are the signal over noise ratio at receiver input SNR = Cr I(Nr + Ir ), the equivalent thermal noise at receiver input Nr and transmission channel attenuation a.
For designing a PA, RF engineers have basically four degrees of freedom: the bias point Vbias, the input power Pin, the load and source impedances ZL & ZS and the number /dimensions of transistors k
Ce=k*C Pdce=k*Pdc
S
C: Output Power I: Intermodulation noise
Pdc:
Consumption
cell
Fig. 2 - Parallel power amplifier structure In many cases, the PA is made of a parallel combination of transistors (or amplifier cells) through power combiners and splitters (illustration Fig.2). For simplicity purpose, we assume ideal splitters and combiners to get upper bound of performances, to which combination losses can be added afterwards. Considering that the PA is composed of k identical amplifier cells where C, I and Pdc are the utile signal, intermodulation noise and DC power consumption of each cell, the total PA characteristics are Ce = kC, Ie = kI, (3) Pdce = kPdc The optimum PA design problem can then be stated as:
Minimise Pdce = kPd, under the condition (4) kCSN kC = ~SNRdesired Ce (,_= UL~ Ne +Ie Ne +kI The optimization variables being Vbias, Pin, ZL, Zs and k .
Defining N = Ne I k as the equivalent thermal noise (transmission channel generated noise) at each individual amplifier cell output, we can eliminate the parameter k in equation (4). Doing so, the optimization of the total PA reduces to that of a single amplifier cell or transistor, and we have the problem: Minimise
Pdc N
under the condition (5) C = SNRdesired N+I The optimization variables are now Vbias, Pin ZL , Zs and N. When N is computed, the number of cells is obtained as k = Ne I N. Actually, solution of the above problem cannot be carried directly as it is stated, this would require prohibitive computing resources, because as already said the intermodulation noise measure used here needs to be a multicarrier factor, e.g. NPR or ACPR. Instead of solving the above problem for a desired SNR, it is much more interesting to plot in a twodimensional space the SNR = C I(N + I) as a function of Pdc I N, for all reasonable values of Vbias, Pi,n ZL, ZS and N. Such a plot gives a cloud of points as depicted in Fig.3. 35 30 S 25
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15
20
25
30
35
40
45
50
Pdc/N (dB) DC Power consumption
Fig. 3 - C/(N+I) chart The upper bound of this cloud, called the envelope is the ultimate linearity vs consumption chart of a transistor or amplifier cell: C l(N + I) chart.
Given a signal over noise ratio SNR desired, the Cl(N+I) chart gives the minimum possible power consumption the transistor or amplifier cell can afford for satisfying this figure with the highest linearity. For MCPA design, C (N +I) chart is the counter part Sparameter description for linear amplifier design.
Starting from the desired SNR, the designer will readily compute the parameters Vbias, Pin, ZL, ZS for optimum operation of the amplifier cell. Then the number of parallel cells is obtained as stated before by k=Ne IN=aNr IN. Other important characteristics of the amplifier like C IN, NPR, Gain, P0,t and PAE may be added to the chart as they are all deduced from the Cl(N+I) curve. Fig.4 gives a complete C l(N+ I) chart of a 1200gm HFET, for deep A/B biasing class. It is worth noticing that in principle one should sweep systematically all possible values of the load and source impedance at fundamental, second harmonic and may be third harmonic, along with bias point and input power in order to get the C l(N + I) chart. This still requires large computing resources, as simulations are done with a multicarrier signal. It has been found that a minimum of 100 independent carriers is necessary for a good multicarrier signal representation. To make construction of the C l(N + I) chart tractable we have been looking for some strong correlation between this multicarrier characterization and more simple one or two-tone characterizations . +*C/(N+l) (dB) -mC/N (dB) -ANPR (dB) ---Pout (dBm) +0Gain (dB) PA E (%)
45
45
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35
35
30
30
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25
.....................
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to the optimum load impedance for maximum single tone PAE. - The projection of the C (N + I) envelope curve onto the source impedance plane tends to be the same for a two-tone signal (a few MHz separation) and a multicarrier signal characterization, and this corresponds to a narrow region of Smith chart. The center of this region may considered as ZSop .
Fig.5 gives the projection of Cl(N+I) chart onto load and source impedance for 1200 tm HFET, deep AB biasing. ZS(2fO)
ZL(fO) ZL(2f- )
Fig. 4 - Optimum source and load impedance locus These empirical observations are very interesting, as they make now construction of the C (N + I) chart much more tractable following the process below: (1) Find the optimum load impedance ZLopt (fundamental and second harmonic) for maximum PAE, under single tone excitation.
(2) With ZL = ZLopt, construct the C l(N + I) chart with a two-tone excitation ( I is third order intermodulation noise) in order to find Zsopt (second harmonic).
(3) With ZL = ZLopt
and Zs= Zsopt, construct the C l(N + I) chart with a multicarrier excitation, sweeping Pin, N and eventually Vbias .
With the above process we can build C (N + I)
25 30 35 Pdc/N (dB) Fig. 4 - Simulated complete C/(N+I) chart oftransistor
charts of the various transistor technologies or amplifier cells candidates for MCPA design. The cell providing the lowest consumption for desired SNR will be selected.
We have found the following observations, for A/B and B biasing class of FET transistors:
IV. OPTIMUM MCPA DESIGN
15
10
20
The projection of the C (N + I) envelope curve onto the load impedance plane (fundamental and second harmonic) tends to correspond very closely
-
Once transistor C (N + I) chart is constructed, then given the desired link SNR, we can compute the
2~ ~ 0
optimum values of the basic parameters Vbias, Pin ZL ,Zs and number of transistors k The next step is then to synthesize the optimum ZL and Zs by passive matching techniques and to add combiner losses, which we neglected above.
C (N +I) chart has been presented, which allows the characterization of power transistor and amplifier cells in terms of linearity and consumption. The great interest of this chart lies in that it provides an appropriate figure of merit for all candidate amplifier cells, early in the design process of a PA.
V. APPLICATION EXAMPLE
VII. REFERENCES
We have experimented the above design methodology through the design of a 2GHz single stage 1200gm HFET PA, the result of which are presented below. C/(N+I) chart of the transistor is shown in Fig.4. This chart as been constructed by simulation with a 100 carrier multitone signal, at a fixed biasing point (Vgs=1.55V, Vds=7V, Ids=Ids0/10). Simulation done with Envelope transient analysis[7] needs about 24hours CPU. The optimum load impedance has been confirmed by load pull measurements. We could not confirm the optimum source impedance by source pull measurement as transistor runs into oscillation. Fig.6 shows measured C l(N + I) chart of the fabricated amplifier, at nominal 50 Q load impedance. Measurements were carried on NPR setups with both a white noise generator and a AWG. By tuning the output impedance on a load pull setup, we have confirmed the optimality of that chart. As we run away of the nominal 50 Q impedance, the C/(N+I) curve is stepping down the presented one. Considering a typical SNR of 12dB, we can read from the graph the following figures: C I N =13.3 dB, NPR =18 dB, Gain =13 dB, Pout =20 dBm, PAE =32%. The achieved amplifier band width is 10% of central frequency, ie: 200MHz
[1] E. G. JECKELN, F. M. GHANNOUCHI, M. SAWAN,
+*C/(N+1) (dB) -mC/N (dB) -ANPR (dB) -Pout (dBm) +0Gain (dB) -PA E(%
45 40
L.
35
,X'----30 25 20 15 10 5
10
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25
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45
35
Pdc/N (dB)
Fig.6 Measured HFET amplifier C/(N+I) chart VI. CONCLUSION
We have presented a new methodology for the design of MCPA, based on an objective measure of the tradeoff between linearity and power consumption under multicarrier excitation. The construction of a
[2] [3]
[4]
[5]
[6]
[7]
"Adaptive digital predistorter for power amplifiers with real time modeling of memoryless complex gains", IEEE MTT-S Digest, 1996, pp. 835-838 M. Johansson, L. Sundstrom, "Linearisation of RF multicarrier amplifiers using cartesian feedback". Electron Lett., 1994, 30, (14), pp. 1110-1112,. Y. K. G. HAU, V. POSTOYALKO, "A microwave feedforward amplifier with improved phase compensation and wideband distortion cancellation"., IEEE Trans. Microwave Theory Tech., 1997, pp. 75-78 K. Y. Chan. And A. Bateman, "Analytical and measured performance of the combined analogue locked loop universal modulator (CALLUM)"., IEEE Proc-Commun, Vol. 142, No. 5, Oct. 1995, pp. 297-306 J. Sombrin "critere de comparaison, d'optimisation et d'utilisation optimale des amplificateurs de puissance non-lineaires", CNES report, Ref. CNES DT-96-16CT/AE/TTL/HY, May 1996. J. Lajoinie, E. Ngoya, D. Barataud, J.M. nebus, J. Sombrin and B.Rivierre, "Efficient simulation of NPR for the optimum design of satellite transponders SSPAs", IEEE MTT's Digest, 1997, pp. 741-744. E. Ngoya, R. Larcheveque, "Envelope transient analysis: a new method for the transient and steady state analysis of microwave communication circuits and systems", IEEE MTT's Digest, 1996, pp. 1365-1368
