Performance Characteristics and Average-Value Modeling of Auxiliary

Performance Characteristics and Average-Value Modeling of Auxiliary Resonant Commutated Pole Converter Based Induction Motor Drives B. T. Kuhn, Member, S. D. Sudhoff, Member School of Electrical and Computer Engineering 1285 Electrical Engineering Building Purdue University West Lafayette, IN 47907-1285 Abstract - The auxiliary resonant commutated pole (ARCP) converter is currently of intense interest for use in a variety of power electronic converters, and is one of the cornerstones of the Navy's Power Electronic Building Block (PEBB) effort. In this paper a detailed discussion of the required switching times needed to achieve completely soft switching operation with only one current sensor per phase is set forth. Based on this analysis, an average-value model of the ARCP converter is derived and used to explore the output characteristics of the ARCP converter. It is shown that large loads at high power factors can cause the ARCP output voltage to drop substantially. Computer simulations and laboratory data are used to validate this analysis.

I. INTRODUCTION Auxiliary resonant commutated pole converters offer the potential for reduced switching loss through the use of zero-voltage and zero-current switching of all of the semiconductors in the converter while still maintaining true PWM control. Reduced switching loss [1-4] allows the ARCP converter to operate at high switching frequencies while the reduced dv/dt and di/dt help to reduce electromagnetic compatibility (EMC) problems [2]. The ARCP converter is typically used in large multi-phase DC-AC power electronic converters where the additional control and design complexities are offset by the improved performance of the converter [5-8]. However, at high switching frequencies the performance of the converter may degrade due to the finite switching times of the phase voltages, resulting in a reduced output voltage capability. To gain insight into this voltage reduction and other performance issues, detailed computer simulations can be used. However, detailed computer simulations can be computationally intense since the switching of each semiconductor must be taken into account. These switchings create fast electrical transients which, when coupled with typically slower electrical and sometimes mechanical dynamics of a electro-mechanical system connected to the converter, make for computationally intensive simulations of these systems. This has led to simulation of these types of systems using average-value models wherein only the average-value of the waveforms are represented, whereupon the state variables become constant in the steady-state. Since the fast electrical transients of the switching semiconductors do not periodically excite the system dynamics, simulation algorithms for stiff systems such as Gear's method become effective, resulting in computationally efficient simulations. In addition, the average-value

C. A. Whitcomb, Member USN Office of Naval Research Code 334 800 N. Quincy Street Arlington, VA 22217 modeling approach is also conducive to steady state analysis which is useful for design synthesis. This paper sets forth an average-value model for the ARCP inverter. Inherent in the development of this model is a detailed consideration of the switching algorithm. Comparisons of model predictions with those of laboratory results and detailed computer simulations demonstrate that the model is quite accurate. II. SYSTEM DESCRIPTION A schematic of the ARCP converter considered in this paper is shown in Fig. 1. The converter is feeding a balanced three phase load which is representative of any number of devices, from rotating machinery to ac load busses. The currents into each phase of the load, i as , i bs , and i cs , are fed back to the ARCP gating signal generator block, which in turn generates the gating signals required to control all of the semiconductor switches in the ARCP converter. Besides the phase currents, the switching state commands s ∗a , s ∗b , and s ∗c are also input into the switching signal generator block. These switching state commands are generated by a supervisory controller which implements a modulation scheme to generate the commanded switching states for the a, b, and c phases of the converter. The inputs to the supervisory controller are the commanded q- and d-axis voltages, v ∗q and v ∗d , as well as the position of the synchronous reference frame, θe . A. ARCP Topology Fig. 2 illustrates the layout of the ARCP converter. It consists of three identical phase legs connected between the DC source and a pair of capacitors used to split the DC voltage. The center tap of these capacitors is used to feed the auxiliary circuit of all three phases. The output line-to-ground voltages are designated v ag , v bg , and v cg respectively, and the output currents are denoted i as , i bs , and i cs . The auxiliary current to each phase leg is denoted i a,aux , i b,aux , and i c,aux .

Fig 1. System Diagram

Fig. 2. ARCP Inverter

Fig. 3 depicts the x-phase leg of the ARCP converter, where x may be an 'a', 'b, or 'c'. The ARCP phase leg consists of four switches with anti-parallel diodes, a resonant inductor L r , and two resonant capacitors of equal value, C r . The resonant capacitors are placed in parallel with the main switches of the converter, S1 x and S2 x , to permit a zero voltage turn off of the main switches. The auxiliary circuit consists of the A1 x and A2 x semiconductors, their diodes, and the resonant inductor L r . This circuit is used to ensure that there will always be enough energy available to charge (or discharge) the resonant capacitors during a switching cycle. B. Supervisory Control The supervisory control can be any PWM technique, but a open loop voltage source based sine-triangle PWM algorithm as depicted in Fig. 4 is used as an example in the development to follow. Therein, v ∗q and v ∗d are the commanded q- and d-axis voltages and θe is the position of the desired synchronous reference frame. The q- and d-axis variables are related to their abc counterparts using the transformation [9] f qd0s = K es ⋅f abcs (1) where  cos(θe ) cos(θe − 2π ) cos(θe + 2π )  3 3   2π  sin(θe ) sin(θe − 2π K es = 2  ) sin(θ + ) (2)  e 3 3  3   1 1 1 2 2 2   and T

f abcs =   f as f bs f cs  

(3)

T

f qd0s =  (4)  f qs f ds f 0s   . In (1-4), f may be a voltage or a current. The abc values can be obtained from qd variables using the inverse transformation. With a sine-triangle modulation scheme, the maximum peak value of the fundamental component of the voltage that can be commanded without introducing low frequency harmonics is v dc /2 . Therefore the commanded voltages are limited by v ∗q + v ∗d 2

2

≤

vdc . 2

(5)

The voltage commands must be transformed to abc variables for the sine-triangle modulator using −1 v ∗abcs = K es ⋅v ∗qd0s (6)

Fig. 3. Diagram of an ARCP Phase Leg

−1

where K es is the inverse of (2). The resulting abc voltage commands are in the range of ±v dc /2 . The phase duty cycle commands can be calculated from the phase voltage commands using d ∗x =

2 ∗ v dc v xs +

1

.

(7)

The duty cycle commands have been offset to vary between 0 < d ∗x < 1 instead of between -1 and 1 as is traditional with sine-triangle modulation to make further analysis of the converter operation more convenient. The outputs of the supervisory control are the commanded states for the phases of the converter, where s ∗a = 1 indicates a commanded a-phase line-to-ground voltage of v dc and s ∗a = 0 indicates a commanded a-phase line-to-ground voltage of zero volts. III. ARCP SWITCH LEVEL CONTROL An important part of the design of an ARCP converter is devising a method to generate the gating signals for all of the semiconductor switches during a commutation sequence. One of the more prominent methods mentioned in the literature for this control [2,4,6,10] uses sensors to detect voltage and current thresholds which allow switches to be turned on or off under zero voltage or zero current conditions. This type of control requires up to two current sensors and a voltage sensor (or two zero voltage detectors) per leg. In order to reduce the sensor requirements, [10] suggests that a time delay could be used to control the auxiliary current rise time eliminating the need for one of the current sensors. Another method for controlling the ARCP is to calculate all of the switching times off-line as a function of the load current at the instant of switching, and then use a lookup table to load timers with the proper times to control the gating signals. This method uses only one current sensor on the output current of each phase of the converter and is the method used herein. In order to calculate the switching times, several assumptions must be made about the converter. First, the DC supply voltage is taken to be constant. Secondly, it will be assumed that the DC capacitors, C dc , serve as an ideal voltage divider. Next, the current out of the phase leg will be assumed to be constant while the converter is switching, making the inclusion of the load dynamics into the analysis of the converter switching unnecessary. Finally, semiconductor and passive component conduction losses will be neglected. Given these assumptions, there are six different switching sequences which may be used depending upon whether a low-to-high or high-to-low transition is desired and the sign and magnitude of the load current at the instant the converter leg state is to be changed. The specific switching sequences are considered below. A. Low-to-high transition with positive load current In this case, a command for a low-to-high transition is given (from the supervisory control) and the load current is positive. From Fig. 3 the output line-to-ground voltage v xg is initially latched to the lower rail by current flowing through the lower diode D2 x . The auxiliary switch A2 x is gated on immediately after the switching command is given, causing the auxiliary current i x,aux to ramp up linearly with a forcing potential of v dc /2 across L r . This auxiliary current displaces the current flowing in D2 x . Eventually i x,aux increases until it reaches i boost , where i boost = i x + i db and where the diode boost current, i db , is picked to guarantee there will be enough auxiliary current to force the voltage to rise to the upper rail when the lower switch is turned off. The time that it takes for the auxiliary current to rise to the boost current level can be calculated as T x,1lh =

Fig. 4. Supervisory Control

2

2L r i boost vdc .

(8)

At T x,1lh , the lower switch is conducting the extra boost current and is gated off. The resonant capacitor holds the voltage across the switch at zero while the switch turns off, ensuring zero voltage switching of this device. After the lower switch turns off v xg is released from the lower rail and it begins its swing to the upper rail using the extra current in the auxiliary circuit to charge the resonant capacitors. After a period of time, v xg will reach the top rail and be clamped by the upper diode D1 x . The time for this voltage rise to occur may be expressed C r ω 0 v dc  T x,2lh = ω20 arctan  (9)  iboost − i x  where ω0 =

1 2L r Cr

.

(10)

When the voltage reaches the upper rail, the current in the auxiliary circuit is given by i x,aux (T x,2lh )= i x + C r ω 0 v dc sin(ω 0 T x,2lh ) ... . (11) + (i boost − i x )⋅cos(ω 0 T x,2lh ) While the voltage is clamped to the upper rail, the upper switch can be turned on without switching losses; however, it does not need to be turned on immediately since the auxiliary current is still greater than the leg current forcing current to flow in D1 x . There is a window of time in which the upper switch can be turned on without switching losses. This window lasts until the current in the upper diode goes to zero. The width of this window is denoted T x,2lh,win and may be expressed T x,2lh,win =

2L r i x,aux (T x,2lh )− v dc [

i x ].

(12)

In an actual hardware implementation of this converter, turning on the upper switch in the middle of this window is recommended to help ensure soft switching. The time that it will take for i x,aux to fall to zero after the voltage has reached the upper rail can be calculated as T x,3lh =

2L r v dc i x,aux (T x,2lh ).

(13)

When the auxiliary current reaches zero, A2 x is gated off and the commutation cycle is complete. In a hardware implementation of this converter a small time delay could be added to this time to ensure the auxiliary current B. Low-to-high transition with slightly negative load current In this case i x is negative at the instant in which the low-to-high transition begins, but is greater than − i thresh , where i thresh is a current threshold used to decide if the auxiliary circuit is required to aid in the commutation process. Since the leg current is small, the auxiliary circuit is used to boost the current available to charge the resonant capacitors. In this case the boost current level i boost is set equal to i swb , where i swb is a current that guarantees there will be enough current to force the resonant capacitor voltage rise. This commutation sequence is identical to the low-to-high sequence with positive load current considered previously except for the manner in which i boost is calculated. C. Low-to-high transition with a large negative load current For this case i x is less than − i thresh and has enough energy to charge the resonant capacitors without the aid of the auxiliary circuit. At the command to switch from low-to-high, S2 x is turned off while the resonant capacitors hold the voltage across the switch at zero, ensuring a zero voltage turn-off. The leg current forces the voltage

rise in the resonant capacitors, causing v xg to clamp to the upper rail through D1 x after a time of T x,2lh =

2C r v dc . − ix

(14)

When the line-to-ground voltage reaches the upper rail, the upper switch is gated on. A small time delay could be added to this for a hardware implementation to ensure that the voltage rise has occurred before the upper switch is gated on. Before proceeding to consider the various high-to-low transitions, it is appropriate to summarize the results for the low-to-high transition. In particular, by substituting the expressions for i boost and i x,aux (T x,2lh ) into (8, 9, 13) and simplifying yields  2L r (idb + i x) ; i x ≥ 0   2Lvdci  r swb T x,1lh =  (15) ; − i thresh < i x < 0  vdc   0 ; i x ≤− i thresh  

T x,2lh

T x,3lh

   =   

    =    

2 ω0 2 ω0

2L r i x v dc

   Cr ω 0 v dc   arctan  i − i x  ; − i thresh < i x < 0  swb  2Cr vdc  ; i ≤− i x thresh − ix  arctan  

+

2L r i x V dc

0

1 ω0

+

Cr ω 0 v dc  idb 

; ix ≥ 0

  ; ix ≥ 0   2L i sin(ω 0 T x,2lh )+ vrdcswb cos(ω 0 T x,2lh )   ; − i thresh < i x < 0   ; i x ≤− i thresh 

sin(ω 0 T x,2lh )+

1 ω0

(16)

2L r (i db + ix ) cos(ω 0 T x,2lh ) v dc

(17) where T x,1lh is the auxiliary current boost time, T x,2lh is the line-to-ground voltage rise time, and T x,3lh is the auxiliary current fall time. Fig. 5 illustrates the semiconductor switching sequence for low-to-high transition sequences using the timed approach. This sequence always begins and ends in states 1 and 9 respectively, where ↑ s ∗x represents the command to start the transition sequence from low-to-high from the supervisory controller. D. High-to-low transition sequences The sequence for high-to-low commutations can be analyzed as a mirror image of the low-to-high sequences; A1 x replaces A2 x , the role of S1 x and S2 x are interchanged and all of the current values will be negated. The leg current i x was positive when current was flowing through D2 x but it must be negative to flow through D1 x . A similar case is made for the main switches. The auxiliary current must be negative for a high-to-low transition since it needs to take charge out of the resonant capacitors; therefore all boost current thresholds will also have to be negated. Applying these changes, the timing relations for high-to-low commutations become  2L r (idb − i x) ; i x ≤0   2Lvdci  r swb T x,1hl =  (18) ; 0 < i x < i thresh  vdc   0 ; i x ≥ i thresh  

will not yield a model in which, for example, the q- and d- axis quantities will be constant in the steady state. This is because the ARCP converter can induce low frequency harmonics into the load causing low frequency variations in the q- and d-axis variables, even in the steady state. In order to eliminate this variation from the model (so the model becomes an average value model in the classic sense) it is necessary to define a second average-value operator x=

Fig. 5. Low-to-High Semiconductor Switching State Diagram

T x,2hl

T x,3hl

   =   

    =    

2 ω0

arctan  

2 ω0

r arctan  i

Cr ω 0 vdc  idb  C ω 0 vdc  swb + i x 

2Cr vdc ix

− 2L r i x vdc

+

− 2L r i x v dc

0

1 ω0

+

; i x ≤0 ; 0 < i x < i thresh ; i x ≥ i thresh

(19)

  ; i x ≤0   2L i sin(ω 0 T x,2lh )+ vrdcswb cos(ω 0 T x,2lh )   ; 0 < i x < i thresh   ; i x ≥ i thresh  (20)

sin(ω 0 T x,2lh )+

1 ω0

      

2L r (i db − ix ) cos(ω 0 T x,2lh ) v dc

where T x,1hl is the auxiliary current boost time, T x.2hl is the line-to-ground voltage fall time, and T x,3hl is the time for the auxiliary current to fall to zero. IV. AVERAGE-VALUE MODELING

6 T fund

∫t− t

1 T 6 fund

x(t)dt

where T fund is the period of the fundamental component of the voltage out of the converter. In (22), the period of integration is over one-sixth of a cycle since the low frequency harmonics in the q- and d-axis variables will be periodic in 16 T fund . In the development to follow, first (21) and then (22) will be applied to the converter model in order to develop a NLAM. However, before proceeding, it should be noted that (21) could be used to develop an average-value model which retains information about the low frequency harmonics. Such an approach, although not taken here, could offer a compromise between a detailed switch level simulation and a full average-value model in the classic sense. The approach used herein, in which successive average-value operators is employed, will be referred to as double average-value modeling. The first step in deriving the double average-value model is to determine an expression for the fast-average of an ARCP leg line-to-ground voltage. Since the process of calculating the fast average is identical for each phase, this analysis will be set forth for the arbitrary x'th phase leg. Fig. 6 illustrates the switching process of the voltage over one switching cycle. Therein, ↑ s ∗x and ↓ s ∗x represent low-to-high and high-to-low switching commands and d ∗x represents the commanded duty cycle from the supervisory control in the range of 0 < d ∗x < 1 . In the figure, the upper trace represents the response of a hard switched converter with zero rise and fall times and no delays. The fast average of the hard switched voltage signal can be shown to be d ∗x ⋅v dc . The lower trace of Fig. 6 represents the ARCP phase leg's response to the same commanded output voltage change. T su is the setup time for the ARCP converter, or the time that it takes from the switch command being given until the first gating signal command is output from the ARCP gating signal generator. This time is dependent on the hardware implementation of the gating signal generator. The switching times T x,1lh ... T x,3hl are calculated using equations (15-20) and the current leaving the phase leg at the instant the switch command is given. The line-to-ground voltage is approximated as a linear rise in order to simplify the derivation. From

For the purposes of design and analysis of the ARCP converter, a non-linear average-value model (NLAM) wherein the switching of the converter is represented on an average-value basis is an invaluable tool. In the model set forth herein, the q- and d-axis commanded output voltages v ∗q and v ∗d and the q- and d-axis output currents i qs and i ds (which will be assumed to be constant and equal to their average-value over the averaging process) will be model inputs. The outputs of the model will be the average q- and d-axis voltages out of the converter v qs and v ds as well as the dc current into the converter, i dc . To develop an average-value model for the ARCP converter, two averaging processes will be used. First a fast average of the line-to-ground voltages of each phase leg over one switching period is applied. This fast average operator is defined as x(t)=

1 T sw

∫t− T t

x(τ)dτ

(21)

sw

where T sw is the switching period of the supervisory control modulation algorithm. Although the fast averaging procedure will result in a model where the switching is eliminated from the model, it

(22)

Fig. 6. Voltage Timing Diagram

Fig. 6, it can be shown that the fast average of the line-to-ground voltage can be represented as v xg = d x,eff ⋅v dc (23) where d x,eff =

T sw ⋅d ∗x − T x,1lh − 12 T x,2lh + T x,1hl + 12 T x,2hl T sw

.

(24)

However, (24) is only valid for a certain range of commanded duty cycles. If the commanded duty cycle is too low, the phase leg will not be able to generate the commanded pulse because there is a limit on the minimum pulse width that the ARCP converter can generate. For example, it is possible that the phase leg could be commanded high, and then before it completes its commutation sequence high, it would be commanded low again. The ARCP must complete one sequence before it starts the next; so an ARCP phase leg is not able to make pulses that are narrower than T x,min = 12 T x,2lh + T x,3lh + T x,1hl + 12 T x,2hl + T su (25)

1 0 0    v qd0s =  0 1 0  ⋅K se ⋅v abcg . (36)   0 0 0   The resulting fast average values of v qs and v ds are not, in general, constant in the steady state. They contain harmonics at a fundamental frequency of 6 ⋅ω e , where ω e is the electrical frequency of the commanded voltage. It is therefore necessary to average v qs and v ds over one sixth of a electrical cycle. These new double averages may be approximated as

d x,eff,min =

T x,min T sw

=

T x,3lh + T x,1hl + T sw

1 T + 2 x,2hl

T su

.

(26)

or T max T sw

=

1 1  T sw −   2 T x,2hl + T x,3hl + T x,1lh + 2 T x,2lh + T su  . T sw

The maximum pulse width expression is used when T sw (1 − d ∗x )< T x,1hl + T x,2hl + T x,3hl + T su . In summary,  d x,eff,min ; (27) satisfied  d x,eff =  d x,eff ; neither (27) or (30) satisfied   d x,eff,max ; (30) satisfied

(29) (30)

  . (31)   After the effective duty cycles are calculated for all of the phases, the fast average line-to-ground voltages can be calculated by (32) v xg = d x,eff ⋅v dc . These fast average line-to-ground voltages can be converted into average q- and d-axis voltages out of the ARCP converter, v qs and v ds , using the transformation to the synchronous reference frame. However, the line-to-ground voltages must first be converted to line-to-neutral voltages such that the zero sequence voltage will be zero (since the load is assumed to be wye-connected). The line-to-neutral voltage can be transformed to the synchronous qd reference frame using v qd0s = K es ⋅v abcs (33)

Using (33-35) it can be shown that

1 N Σ v (θ ) N k=1 ds e k

(38)

π k 3⋅N

(39)

to the average power into the ARCP converter which can be approximated as (41) P in = v dc i dc . Although the converter has energy storage elements, L r and C r , on average the energy stored in these devices will be a constant. Since the energy stored in the converter is constant, the power into the converter must be equal to the power out of the converter plus the losses in the converter. Since the losses in the converter were neglected previously they will also be neglected here; therefore P in = P out and the dc current into the converter can be expressed as i dc =

(35)

3 (v i + v d i d ) 2 q q v dc

.

(42)

The methods used for calculating the switching times and deriving the average-value model are general and not limited solely to the ARCP converter. These processes could be applied to other soft switched converters such as, for example, resonant dc link converters [11] or auxiliary quasi-resonant dc link inverters [12] to develop average-value models. V. IMPLEMENTATION An ARCP converter was constructed in order to verify the validity of the average-value model and the timed approach for generating the gating signals. The parameters used in the construction of the ARCP converter are shown in Table I. IGBT modules were used for the primary and auxiliary switches. The approximate on-state voltage drop of the IGBTs and diodes that were used are v igbt and v diode . The auxiliary circuit voltage was split using two large electrolytic Table I. ARCP Parameters

T

1 1 1  (34) v abcs = v abcg −   ⋅v ng is the neutral-to-ground voltage which may be expressed v ng = 13 (v ag + v bg + v cg ).

v ds =

and k varies from 1 to N where N is the number of points used in the averaging procedure. The dc current into the converter will be calculated on an average-value basis by equating the average power out which can be calculated P out = 32 (v qs i qs + v ds i ds ) (40)

where K es is as defined in (2) and where v ng

(37)

θe k =

This condition would occur when T sw ⋅ d ∗x < T x,1lh + T x,2lh + T x,3lh + T su . (27) Similarly, there will be a maximum pulse width that the ARCP phase leg can generate. This pulse width is 1 1  T x,max = T sw −  2 T x,2hl + T x,3hl + T x,1lh + 2 T x,2lh + T su  (28)

d x,eff,max =

1 N Σ v (θ ) N k=1 qs e k

where

or a minimum effective duty cycle of 1 T + 2 x,2lh

v qs =

ω e = 2π ⋅60

v dc = 300 V

L r =12.85 µH

C r = 22.88 nF

i swb = 10 A

i db = 10 A

v igbt = 2.1V

v diode = 1.1 V

T su = 6.0 µs C dc = 1000 µF i thresh = 10 A r lr = 0.028 Ω

capacitors C dc . Additionally, the resistance of the resonant inductor is listed as r lr . The timed approach of calculating the switching times off-line as a function of the load current was used in the hardware implementation. A sequence similar to Fig. 5 was used to calculate the switching times which were stored in an EPROM from which they can be loaded into a timer chip to control the switching sequence. This timer chip accurately (to 0.1 µs) controls the combinational logic so as to produce the correct semiconductor gating signals. Fig. 7 depicts an overview of the gating signal generator hardware for one phase of the converter. A transition of the commanded state s ∗x triggers the ARCP gating signal generator circuit, starting the counter and causing the A/D converter to sample the leg current. The counter is used to sequence the operations which need to be performed to load the timer chip and the A/D converter addresses the EPROM with an address corresponding to the leg current i xs . The EPROM stores the switching times for this value of current at this address. Using the address from the A/D and knowledge if the transition is from low-to-high or high-to-low, the EPROM loads the switching times into a three channel timer chip (82C54); it also loads a mode register which tells the combinational logic if the auxiliary circuit is to be used and the direction of the commutation. After all of the timers are loaded, they are triggered to start simultaneously. The timer chip's output is processed by combinational logic which changes the gating signals of S1 x , S2 x , A1 x , and A2 x at the correct times to complete a proper ARCP commutation from low-to-high or high-to-low. After the commutation sequence is complete, the trigger is reset and the circuit is ready for the next command to change. The feedback of the sequence complete signal to the trigger protects the circuit from starting a second commutation the current one is complete. The setup time for this implementation is 6 µs. Fig. 8 depicts the auxiliary current i aux and line-to-ground voltage v g as a switching command s ∗ is given. Notice the overshoot of the auxiliary circuit; this is due to the reverse recovery of the diodes in the auxiliary circuit. Zener diode snubbers were added to the auxiliary circuit [13] to snub out these overshoots quickly (the fast recovery of the auxiliary current back to zero). Since these snubbers do not impact the performance of the converter they are not included in the models. VI. EXPERIMENTAL VERIFICATION In order to validate the operation of the ARCP converter as well as the performance of the average-value model, the converter was loaded with a 4-pole 3.7 kW induction motor whose parameters are listed in Table II. The converter was operated at a switching frequency of 20kHz and the motor was loaded with a dynamometer to run at it's rated speed of 1750 RPM. Varying voltage commands were applied

10µs

4

s* 0 1 400

vg

200

0 100 20

iaux 0 20

Fig. 8. Waveforms from ARCP Converter

to the motor and the fundamental component of the voltage and it's phase relative to the commanded voltage was extracted as well as the magnitude of the dc current into the converter. Simulations were run using both a detailed model and the average-value model of the ARCP converter for the same data points as those which were experimentally obtained. For the average-value model, ten data points were used in the averaging process (N=10). The q- and d-axis voltages are plotted for these tests in Figs. 9 and 10 respectively and the dc current into the converter is shown in Fig. 11. As can be seen, the results match up well in both the q- axis and d-axis. The slight difference in the voltage magnitudes may be attributed to the semiconductor voltage drops which were not included in the NLAM model; however the overall trend is very accurate. The negative d-axis voltages which are produced correspond to the effective voltage of the ARCP converter leading the commanded voltage command by a few degrees. The NLAM can be extremely useful for calculating the output characteristics of the ARCP converter under various operating conditions. As an example of this, consider Fig. 12 wherein the output peak voltage magnitude is plotted as a function of the load current and the power factor angle (relative to the commanded voltage). For this study, the switching frequency (20kHz) and the commanded voltage (120v) are held constant while the magnitude and phase of the load current is varied. The ARCP converter parameters are the same as in Table I. Notice in this example that the 150

vq* vq

125

100

(NLAM)

vq

75

(det. sim.)

Fig. 7. Gating Signal Generator Hardware Implementation

vq

50

(lab. data) 25

Table II. Induction Motor Parameters r s = 0.3996 Ω

L ls = 6.601 mH

L m = 61.21 mH

r r = 0.1983

L lr = 3.305 mH

P=4

0

0

25

50

75

vq*

100

Fig. 9. Q-Axis Voltage of Induction Motor

125

150

1

computer simulations and to laboratory results using an experimental ARCP converter driving an induction motor.

0

vd*

1

vd

2

VIII. ACKNOWLEDGMENT This effort has been supported by the Office of Naval Research grant number N00014-96-0522

(NLAM) 3

vd (det. sim.)

4

vd

5

(lab. data)

IX. REFERENCES

6 7 0

25

50

75

vq*

100

125

150

125

150

Fig. 10. D-Axis Voltage of Induction Motor 6

idc (NLAM) 4

idc

(det. sim.)

idc

2

(lab. data)

0 0

25

50

75

* vq

100

Fig.11. DC Current into the ARCP Converter

Voltage Mag. (V) 110 108 106 90 80

104 70 60 102

50 40

100 0

30 5

10

15

Current Magnitude (A)

20

Power Factor Angle (degrees lagging)

20

Fig. 12. Effective Voltage out of ARCP Converter

effective voltage out of the converter drops off as the load current increases and as the load power factor approaches unity. VII. CONCLUSION An average-value model for the auxiliary resonant commutated pole converter has been set forth which is capable of calculating the average q- and d-axis voltages out of the converter under various operating conditions. In doing so, a timed approach for controlling the ARCP converter was demonstrated and used in the model verification. Two averaging processes were used to obtain the non-linear average-value model. This accuracy of this model was verified by comparison of its predictions with those of detailed

[1] A. Cheriti, K. Al-Haddad, and D. Mukhedkar, "Calculation of Power Loss in Soft Commmutated PWM Inverters," IEEE-IAS Conference Proceedings, 1991, pp. 782-788 [2] H. J. Beukes, J. H. R. Enslin, and R. Spee, "Performance of the Auxiliary Resonant Commutated Pole Converter in Converter Based Utility Devices," IEEE-PESC Conference Record, 1996, pp. 1033-1039 [3] J. Dawidziuk, S. Jalbrzykowski, and Z. Prajs, "An Analysis and Experimental Studies of Auxiliary Resonant Commutated Pole Inverters," IEEE Industrial Electronics Conference Proceedings, 1993, pp. 780-785 [4] M. Dehmlow, K. Heumann, and R. Sommer, "Comparison of Semiconductor Device Losses in Hard Switched and Zero Voltage Switched Inverter Systems," Fifth European Conference on Power Electronics and Applications, 1993, vol. 2, pp. 419-424 [5] M. Dehmlow, K. Heumann, and R. Sommer, "Comparison of Resonant Converter Topologies," IEEE Industrial Electronics Conference Proceedings, 1993, pp. 765-770 [6] P. P. Mok, H. Gutt, R. Spee, H. J. Beukes, and J. H. R. Enslin, "Control Complexities Related to High Power Resonant Inverters," IEEE-PESC Conference Record, 1996, vol. 2, pp.1040-1046 [7] D. M. Divan, G. Venkataramanan, and R. W. A. A DeDoncker, "Design Methodologies for Soft Switched Inverters," IEEE Transactions on Industry Applications, vol. 29, no. 1, January 1993 [8] S. Bhowmik and R. Spee, "A Guide to the Application-Oriented Selection of AC/AC Converter Topologies," IEEE Transactions on Power Electronics, vol. 8, no. 2, April 1993 [9] P. C. Krause, O. Wasynczuk, and S. D. Sudhoff, Analysis of Electrical Machinery, IEEE Press, 1995. [10] R. W. De Doncker and J. P. Lyons, "The Auxiliary Resonant Commutated Pole Converter," IEEE-IAS Conference Proceedings, 1990, pp. 1228-1335. [11] D. M. Divan, "The Resonant DC Link Converter - A New Concept in Static Power Conversion," IEEE Transactions on Industry Applications, vol. 25, no. 2, March 1989, pp. 317-325 [12] R. W. De Doncker and J. P. Lyons, "The Auxiliary Quasi-Resonant DC Link Inverter," IEEE-PESC Conference Record, 1991, pp. 248-253 [13] M. Ohsugi, T. Shimizu, G. Kimura, A. Toba, and S. Sano, "The Analyses of ZVS Turn-off Loss and the New Snubber Circuit for the ARCP Inverter," Proceedings of IECON, 1994, pp. 316-32 Brian T. Kuhn (M' 94) was born in St. Louis, Missouri on September 28, 1973. He received the BSEE and MSEE degrees from the University of Missouri-Rolla in 1996 and 1997 respectively. He is currently employed with Purdue University and P.C. Krause and Associates, working as a research engineer. His interest include the design and modeling of electrical machinery and resonant converters. Scott D. Sudhoff (M'88) received the BSEE, MSEE, and Ph.D. degrees at Purdue University in 1988, 1989, and 1991, respectively. From 1991-1993 he served as a half-time visiting faculty and half-time consultant for P.C. Krause and Associates. From 1993-1997 he served as an assistant professor at the University of Missouri-Rolla and became an associate professor at UMR in 1997. Later in 1997, he joined the faculty at Purdue University as an associate professor. His interests include the analysis, simulation, and design of electric machinery, drive systems, and finite-inertia power systems. He authored or co-authored over twenty-five journal papers in these areas. LCDR Cliff A. Whitcomb (M' 97) received a BS in Nuclear Engineering from the University of Washington, Seattle, WA in 1984, an SM in Electrical Engineering and Computer Science from MIT in 1992. He is currently a Ph.D. Candidate in mechanical engineering at the University of Maryland, College Park, Maryland. His current position is as a Program Officer in the Ship Structures and Systems Science and Technology Division (ONR 334) at the Office of Naval Research in Arlington, Virginia, overseeing basic research in electrical distribution systems. He also the Systems Engineering Manager for the Power Electronics Building Block (PEBB) project team. His twenty years of naval service has included tours onboard the USS SCAMP (SSN 588), shipwork coordinator for construction work on nuclear attack submarines at the Supervisor of Shipbuilding, Conversion, and Repair, Groton, Connecticut, and as ship research design engineer for design of submarine systems at the Naval Surface Warfare Center, Carderock, Maryland. His main research interest is in multi-disciplinary design optimization of complex systems.