Given a, b, k,, k, and x s R , a k,-valued literal and k,-valued complementary literal operations are defined as
kl
ifasxsb
L(hUxb) = 0
otherwise ifasxsh otherwise
[ {
0
C L ( k c . a x b ) = k,
(4)
respectively. Considering the logic level definition in (2), wc propose the structure shown in Fig. 3 to implement the above operations simultancously from thc same circuit with quantities normalised to Ib. Owing to space limitation only the block diagram is given. The internal circuits are similar to the circuit of Fig. 2. Repeated quantities can be rcproduced through proper mirror circuits.
independent of the technology used and operates faster than switched-current mode designs. Acknowledgment: This work is sponsored by the BogaziCi University Research Fund (01HA201).
$3 TEE 2002 Electronics Letters Online No: 20020127 DOI: IO.I049/el:20020I 2 7
4 November 2001
T. Temel and A. Morgiil (Electrical Engineering Department, Bogazici Univemi~,Dtanbul, Turkey) E-mail:
[email protected]
References
Fig. 3 Current-mode iniplenientotion(if literal und complementary literal
operations
The circuit is designed with Mietec’s ES2 0.7 pm HSPicc (level 6) parameters in full-extraction for 2.7 V power supply voltage. HSPice simulation results arc shown in Fig. 4. The topologies proposed are compared with [l] using a switching transistor with body bias/no bodyand CL(3,’2) are implemented bias conditions. The functions L(5, ’.2) using the same design parameters. The results are summarised in Table 1 rrom which it can be seen that the proposed circuits operate fastcr with almost the same design costs.
1 JAN, A.K., BOLTON, R.J., and ABD-EL BARR, M.H.: ‘CMOS multiple-valued logic design (Parts I and II)’, IEEE Trans. Circuits Sysr., 1993, 40, (8), pp. 503-532 2 DAO, T.l:, RUSSELL, L.K., and MCCLUSKEY, E.J.: ‘Multi-valued integrated injection logic’, IEEE Trans. Comput., 1977, C-26, (12), pp. 1233-1241 3 WAHO, T., CHEN, K.J., and YAMAhlOTO, M.: ‘Resonant tunneling diode and HEMT logic circuits with multiple thresholds and multilevel output’, IEEE J. Solid State Circiits, 1998, 33, (2), pp, 268-274 4 FRBITAS, D.A , and CURRENT, K.w.: ‘A CMOS current comparator circuit’, Electron. Lett., 1983, 19, (17), pp. 695-696 5 ONh’EWEER, S.P.,and KERKHOFF, H.G.: ‘High-radix current mode circuits based on the truncated difference operator’. 17th ISMVL Conf. Proc., May 1987, pp. 188-195 6 ALLEN, C M.,and GIVONE, D.D.: ‘A minimization technique for multiplevalued logic systems’, IEEE Trans. Comput., 1968, C-17, pp. 182-184
Phase detector for data-clock recovery circuit A. Hati, M. Ghosh and B.C. Sarkar
801
A new type of phase detector which can be used in data-clock recovely circuits is reponed. The main feature of the proposed phase detector is that it is frce from data dependent jitter, which is the main problem with the Hogge phase detector.
I
a 801
I li5
0
CL(3.393#
3j5
2jO
615
500
750
8j5
1000
time, ns b
Fig. 4 Simulalion results a ~ ( 5’2) . h CL(3, 3x5)
Table 1: Simulation results of proposed and switched-current mode designs for literal operations Gate
No, of ~~~
CL(3, ‘2)
Ref. [4] This study Ref. [4]
transmissions 23 21 19 21
Avcrage delay, ns
Average power dissipated, m W
4.3
0.50
7.1/6.2 4.1
0.42/0.46 0.43
6.816.3
0.42j0.40
circuit
clock signal
Conclusion: We have described a novel realisation of multi-valued logic literal and complementary literal operations. The new design is based on a current-mode threshold circuit. The gate design is
ELECTRONICS LETTERS
Introduction: Data clock recovery (DCR) circuits find wide application in modem communication systems [l]. The performance of the phase-locked loop (PLL)-based DCR circuit depends greatly on the structure of the phase detector (PD) used in the loop. Different types of PDs are suggestcd in the literature, among them the Hogge PD (HPD) is well known [2, 31. However, the main problem with the HPD is that the output terminals do not assume fixed states even in the condition of phase matching of the two inputs to it. Thus, when the charge pump filter converts the HPD output state to analoguc control voltage a train of special shaped pulses is present in the control voltage, when applied to the voltage-controlled oscillator (VCO) used in the HPD-based PLL, and the output of the VCO is found to be spectrally impure owing to these fluctuating control voltages, even in the locked state of operation of the PLL. To get rid of this problem, in this Letter a new type of PD with improved performance is proposed. The structure of the new PD is very simple and is based on common logic gates. The control voltage of the VCO with the new PD is completely frce from thc perturbing pulses, which is thc merit of the proposed structure.
14th February 2002
Fig. 1 Block diagram
Vol. 38 No. 4
uf
vco
charge pump filter output
PLL-bused clock recovery circuit
161
I
I
w, I
I
CLK2
[ -
Fig. 2 Hardware structure of new phase detector
m
v1
1
v2
flflflflflfiflflflflflflflflflflflflflflfiflflfl
Ql(F1)
--i
Q2(F2)
1
I
u
QZ(F2)
n
I
rl
-
i
I
I
n
n n
v3
q-
v4
T
U u
vi
1
m
v2
P -
n
u
u u
U
v5
U
D
Qi(F1) QZ(F2)
a
7 1
a2(F2)
r
1
I
n n
n
U
n
n b
v2
n
u
1
n n
n
n n u u
n
Experimenful results: An experiment was performed using available IC building blocks to examine the responses of DCRs using the NPD or thc HPD. 4 pseudorandom noisc (PN) scquencc gencrator implemcnted using a linear fcedback shift register (LFSR) algorithm was used to simulate the randomly varying zero-one sequence to be treated as the input data stream. The experimental DCRs regenerated the clock signals of the input PN sequcnce. The spectrum of the VCO output from the DCR using the HPD is shown in Fig. 4u, which contains spurious components owing to thc prescnce o f jitter in the control signal, whcreas Fig. 4b shows the spectrum of VCO output from the DCR using the NPD. The superiority of the DCR using the NPD is quite evident from Figs. 40 and b. mkr 1 249.9 kHz ref 0 dBm atten l O d B -20.57 dBm peak loa
1m i P
n
Q1 (Fl) -1 QW2) 1 QZ(F2)
nu n u u
"4
n
v5
U
J
I I
nu
v3
D
L : u
-
D VI
n n
U
v4 "5
n
1
m
n
v3
L
I
are low. Similarly it can he shown that when v, leads v2 then Uwill be a positive pulse of width proportional to thc phase error between v1 and v2 and D will always be low and vice versa when v1 lags v2. Thus, U and D outputs of the NPD can be low simultaneously or either onc alone can be high, but both can never be high simultaneously. In the DCR circuit, a charge pump circuit is employed to convert the digital signals Uand D into pump current (T,) and the loop filter (integrator) then converts this current into an analogue voltage. Whenevcr v I and v2 are aligned, no current will flow and as a result there is no net change in output of the loop integrator. However, when v i lcads (lags) v2, +J, (-I,,) current will flow for a period proportional to the phase error between v1 and v2,thus the output of the loop integrator exhibits a net increase (decrease). This control voltage will lead the VCO to become locked to the input signal (vl). Since the control voltage remains unchanged in the phase-locked condition of vi and v2, the spectral purity o f the VCO output will improvc, this being the mcrit of the proposed structure.
L
n
n
n
~
I
U
~
u
n
n
n
n
n
n
n
n
start 100 kHz res BW 3 kHz ref 0 dBm
C
peak
Fig. 3 Timing diugrum of signuls at dijferent points of proposed phase detectors a Input signals, v , and v2, are in the same phasc
I
VBW 3 kHz a
stop 375 kHz sweep 91.67 ms (401 pts) mkr 1 249.9 kHz -20.78 dBm
atten 10 dB
I
log 10 dBi
b v , leads v2 c
1'1
lags 1'2
Structure und operation of new, PD: The block diagram of the PLLbased DCR circuit is shown in Fig. I , while Fig. 2 shows the hardware structure of the proposed new PD (NPD). It comprises two D-flipflops (F1 and F2), three EX-OR gates (El, E2 and E3), two AND gates (G 1 and G2) and one NOT gate. It compares thc phascs of the two inputs v , and v2 where v1 is an unequal density zcro-one data stream and v2 is a locally regenerated VCO signal (a rectangular waveform of 50% duty cycle). The operation of thc NPD in open loop condition can he understood with the help of timing diagrams for different phase relations between v l and v2 given in Figs. 3a, h and c. At the rising instants of thc v2 (Le. when it changcs from 0 to I ) the statc of v I (0 or 1) will he transferrcd to the output Q1 (Q2) of F1 (F2) and will remain unchanged till the next rising instant of V I . The output of E2 (v4) is high only when the output of F1 (Ql(F1)) and the output of F2 (Q2(F2)) are both the same (i.e either high or low) and it will remain zero for a period cqual to the half period of v2. The output v3 of E l is a positive pulse for each transition instant of v1 . but its width depends on the phase error between vI and v 2 , The output v j of G1 is high only when w3 and v4 are both high. When vI leads (lags) vz, the width of v3 is greater (less) than half period of v2 and if vI and v2 are aligned, the width of v~ is equal to that of half period of v2. Therefore, when v1 and v2 are aligned the outputs Uand D of the NPD
162
WlS2 53 FC AA ~
start 100 kHz res BW 3 kHz
VBW 3 kHz
stop 375 kHz sweep 91 6 7 ms (401 pts)
b
Fig. 4 Power .spectrum of wgeneruted reference signal obtained at loop VCO output in CKC circuit a HPD b NPD
Conzmentc.: A new typc of phase dctector is proposed. The new structure is easy to implement and requires only a Iew logic gates in comparison to the HPD. In the NPD-based DCR circuit, the loop VCO control voltage is free from any variation in the locked state o f operation. Thus, this structure can be very useful in designing jitterfree data and clock recovery circuits having spectrally pure outputs. The results of the experiment performed at lowcr RF hands support the claim of superiority of the NPD. Since thc constituent IC building blocks (FFs, VCO, etc.) are available at higher ends of the RF spectrum, the NPD-based systems can he designed at that frequency region also.
ELECTRONICS LE77ERS
14th February 2002 Vol. 38 No. 4
Co
IEE 2002 Electronics Letters Online No: 20020109
17 September 2001
DOI: IO.1049/el:20020109 A. Hati, M. Ghosh and B.C. Sarkar (Phy.yics Department, Burduun University Burdwan- 713 104, We,vt Bengal, India) References 1 LEE, T.H., and BULZACCHBLLI. J.F.: ‘A 155-RIHz clock recovely delay and phase locked loop’, lEEE J. Solid-Smte Circuits, 1992, 27, (12),
pp. 1736-1745 2 HOGtiE, C.R.: ‘A self correcting clock recovery circuit’, J Lightwave Technol., 1985, LT-3, (6), pp. 1312-1314 3 SARKAR, B.C., and HATI, A,: ‘PLL-based frequency synthcsiscr witbout using the frequency divider’, IEE PTUC., Circuits Devices S’st., 148, ( 5 ) . pp. 255-260
Scheme for reducing size of coefficient memory in FFT processor M. Hasan and T. Arslan Long fast Fourier transforms (FFTs) are required in applications such as orthogonal frequency division multiplexing, radars and sonars. It i s highly desirable to reduce the sizc and power requirements of the FPT so as to realise singlc chip long FFT-based systems targeting portable applications. Presented hcrc i s a novel technique to reduce the coctficient memory almost by a factor of four by exploiting the relationships among the coefficicnt valucs thereby significantly reducing the arca and power requirements of the hardware. Introduction: The area and power consumption are of prime importancc in portable telecommunication applications. Fast Fourier transform (FFT) has to be computed in many of these applications. Long FFTs are common in orthogonal frequency division multiplexing (OFDM), radars and sonars, etc. Hence, it is very important to minimisc FFT hardware for its further area and power efficient realisation. The numbcr of coerficients in a radix-2 FFT is equal to N/2, where ‘N’ is the length of the FFT. The coefficient memory required to store thesc cocfficients will thus require N/2 locations where each location stores the real and the imaginary part of the coefficient in a conventional implementation: here we term it Conv [i]. Ma and Wanhammar [Z] and Chang and Parhi [3] proposed that the sizc of the coefficient memory can he cut to half (N/4) by exploiting the correlation among the coefficicnt values: here we term it Others. In this Letter we present a novcl technique to reduce the size of the coefficient memory by almost a factor of four ((N/X)+ I ) . We provide results demonstrating that by adopting Our technique the savings in area and power will be substantial for long FFTs in different types of realisations compared to the Others memory-based techniqucs.
Table 1: Description of various memory organisation schemes Address
I
Coefficient set (rcal, imaginary)
I
16-bit qoantised coefficient
.98, -.19 .92, -.38 .83, -.55
0100 0101
.71, -.71
7d89, e706 7641, cm4 6a64 bSe3 SaX2, aS7d
.55. - 3 3
471c., 9592 -~
0110 0111
.38, -.92
30th. 89be IXfY, 8276
I000
0.0. -1.0 -.19, -.19 - .38, -.92
0000.
- .55, -23 -.71, -.71
b8e3, 9592 a574 a57d 9592~,hXe? .. X9bc, cfu4 mx
.19, -.98
1110
I
Ill1
I
83. - 3 5
92, -.38 -98-19 -
Olhers
schemes
values
0001 00 10
-
Our scheme
Block
Block A Block 11
xom
e706, 8276
I I
Block B
Let the complex coefficient values in tcrms of the real and imaginary parts he reprcscnted as in (I): zbg
= R,,
+i&
(1)
where b indicates the memory block numbcr and g is an index which points to the coefficient values within individual blocks. The first coefficient value in each block has an index g equal to zero. The first block coefficient values are obtaincd from (1) by replacing h with I as shown in (2): zlg=
0 5 g 5 N/8
+JIl,
(2)
Let the coefficient memory addrcss generated and the actual block address be represented by an n-bit array A, and an (n - 1) bit array A, respectively. The coefficicnt memory block address is always 1 bit less than the conventional memory address as the block size is limited to ((N/8)+ 1) instead of N/2. The corresponding addrcsses of the coefficient values in the first block are given by the following equation: ,4,,[n - 2 : 01 = A,[n - 2 : 01
where n = logz (N/2), 0 sg 5 N / 8 and 0 5 m 5 N/8. The second block coefficient values can be obtaincd in terms of the first block coefficient values by performing the following substitution and in the right-hand side of (2): R1+ -Il, 11+--Rl g + (N/X - 1 - g). The symbol here corresponds to a Complement opcration. This can also be verified from Table 1, The resulting equation is as follows:
-
Zz, = [-4 [.v18-I),-
I +.A--R I ( w - I -,q) 1 0 5 g 5 ( ( N / 8 )-2)
Scheme description: The FFT coefficients are expressed as follows:
W, = exp(-jZIIk/N) where k varies from 0 to N/2 - I giving rise lo N/2 coefficients for an N-point FFT where ‘W indicates the number of data points or the length of the FFT. The values of the cocfficients for a 32-point FFT in 2’s complement form are given in Table 1. The partitioning of coefficients into blocks (as shown in Table 1) is applicable to all FFT lengths. Others proposed to divide the memory into two identical blocks, namely A and B. It is clcar that the coefficient values in block B can be generated from those in block A by interchanging the real and imaginary parts of the coefficients and by also complementing the rcal part before its assignment to the imaginary part corresponding to block B. Hence, only block A needs to be stored. In Our technique, the memory is partitioned into four blocks (Block I to Block IV) rather than two, as shown in Table 1. The memory size in Our scheme is reduced to ( ( N / 8 )+ 1) locations (only Block I is needed) from the N / 4 locations proposed by Others schemes (only Block A is needcd). Using Our scheme, therc is a nced to store only coefficient values in Block I and the rcst of the coefficient values in other blocks and their corresponding first block addresses can be generated by following thc gencral procedure given below. This procedure can he explained with the help of a 32-point FFT example given in Table 1.
ELECTRONICS LETTERS
14th February 2002
When the coefficient memory addrcss generator proceeds to generate the addrcss in the second block, the corresponding address in the first block (only Block 1 is stored) are obtained by taking the 2’s complement of the cocfficient memory address as follows: A,, = -A,[n
-2
: 01
+1
0 5 g 5 ( ( N / X )- 2 ) W/8)
+ 1) 5 m 5 (@“4)
-
1)
Similarly, the coefficient values in thc third block are obtained from thc first block coefficient values using (2) as follows:
4, = [I~,I+.j[--Rj,I
0 5 g 5 N/8
When the coefficient memory address generator proceeds to generate the addresscs in the third block, the corresponding first block addresses arc obtained as follows:
A,, = A,,[iz - 2 : 01
0 5 g 5 N / X , N / 4 5 m 5 3N/X
Similarly, the fourth block coefficient valucs arc obtained in terms of the first block coefficient values again using (2) as follows:
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