Electrical Engineering Physics is no longer sufficient. Technology .... 37nm gate
length. ▫ PNO gate: 10 nm EOT. ▫ NiSi. 2. /Poly gate. ▫ 8 levels Cu with low-k.
Physics of Advanced CMOS VLSI Dennis Buss Texas Instruments, Inc. Dallas, Texas USA
Conclusions
For For the the past past 35 35 years, years, transistors transistors have have been been developed developed using using “Electrical “Electrical Engineering Engineering Physics”, Physics”, which which was was codified codified in in the the early early 60’s 60’s
As As the the industry industry approaches approaches the the “End “End of of Roadmap”, Roadmap”, Electrical Electrical Engineering Engineering Physics Physics is is no no longer longer sufficient. sufficient. Technology Technology development development increasingly increasingly requires requires –– Sophisticated Sophisticated quantum quantum physics physics –– Non-equilibrium Non-equilibrium Boltzmann Boltzmann transport transport –– Material Material science science at at the the atomic atomic and and electron electron orbital orbital level level
This This has has implications implications for for –– Physics Physics education education –– Career Career opportunities opportunities for for physicists physicists in in the the semiconductor semiconductor industry industry
Agenda
Introduction to CMOS VLSI Technology
Physics challenges to continued VLSI scaling
Conclusion
Integrated Circuit – 1958
US Patent # 3,138,743 Filed Feb. 6, 1959
MOS Scaling Gate Length Oxide Thickness Gate Material Junction Depth Interconnect Mask Levels
Late 60's 10 µm 120 nm Al 2.5 µm Al 5
2000 120 nm 12 A poly-Si 25/70 nm Cu 25 - 35
10 µm 1200 A
Metal Gate 2.5 µm
SiO2 1200 A
Late 60's
2000
Moore's Law 10 um
Modern Modern CMOS CMOS Beginning Beginning of of Submicron Submicron CMOS CMOS
1 um
Deep Deep UV UV Litho Litho
34 Years of Scaling History 100 nm
10 nm
90 90 nm nm in in 2004 2004
Every generation – Feature size shrinks by 70% – Transistor density doubles – Wafer cost increases by 20% – Chip cost comes down by 40%
Presumed Presumed Limit Limit to Scaling to Scaling
Generations occur regularly – On average every 2.9 years over the past 34 years – Recently every 2 years
1 nm 1970
1980
1990
2000
2010
2020
34 Years of History Feature Feature Size Size Transistor Transistor Density Density Chip Chip Size Size Transistors/Chip Transistors/Chip Clock Clock Frequency Frequency Power Power Dissipation Dissipation Fab Fab Cost Cost WW WW IC IC Revenue Revenue WW WW Electronics Electronics Revenue Revenue
1970
Today
66 um um
90 90 nm nm
~10 ~10 mm mm22 1000 1000 100 100 kHz kHz ~100 ~100 mW mW ~$10 ~$10 M M $700 $700 M M $70 $70 B B
~400 ~400 mm mm22 200 200 M M >> 11 GHz GHz ~100 ~100 W W >$1 >$1 B B $170 $170 B B $1.1 $1.1 T T
Change 70x 70x 5000x 5000x 40x 40x 200,000x 200,000x >10,000x >10,000x ~1000x ~1000x >100x >100x 240x 240x 16x 16x
Reduction Reduction Increase Increase Increase Increase Increase Increase Increase Increase Increase Increase Increase Increase Increase Increase Increase Increase
Electrical Engineering Physics Conduction Band
Electron Mass Eg Hole Mass
f(E) =
1 e (E - EF )/kT + 1
)/kT (Ec -- F F )/kT n = Ncc e –– (E n Valence Band
-- E (F Ev )/kT )/kT p = Nvv e –– (F p
d2V(x) ρ (x) q + = = ( p n + N N dd aa ) 2 ε ε dx dn(x) Jnn(x) = qµnnn(x)ε(x) + qDnn dx dp(x) Jpp(x) = qµpp p(x)ε(x) - qDpp dx
High Performance Processor @ 90nm 256 million transistors 37nm gate length PNO gate: 10 nm EOT NiSi2/Poly gate 8 levels Cu with low-k interlevel dielectric
Heading for Change 100 80
Gate Length (nm)
60 40 20 0 2004
2006
2008
2010
2012
2014
2015
Heading for Change Challenges
100
•• Push Push CMOS CMOS as as far far as as we we can can (to (to "end "end of of roadmap") roadmap") •• Invent Invent next next generation generation electronics electronics
80
Gate Length (nm)
60 40 20 0 2004
2006
2008
2010
2012
2014
2015
Lithography 10
Above Wavelength
Near Wavelength
Below Wavelength
3
1 Resolution (µm)
2
1.5 1 0.6
g-line λ = 436nm
0.1
DUV λ = 248nm
0.5 0.4
0.35
i-line λ = 365nm
193 λ = 193nm
0.25
157 λ = 157nm i-193 λ‘ = 133nm
0.18 0.13
0.09 0.065 0.045 0.032
0.01 1980
λ = EUV 13.5 nm
1990
2000
2010
Year of Production
Lithography will not ultimately limit IC feature size!
Agenda
Introduction Introduction to to CMOS CMOS VLSI VLSI Technology Technology
Physics Physics Challenges Challenges to to Continued Continued VLSI VLSI Scaling Scaling –– Gate Gate insulator insulator –– Gate Gate electrode electrode –– Carrier Carrier scattering scattering –– Quantum Quantum behavior behavior of of carriers carriers in in the the presence presence of of stress stress –– Non-equilibrium Non-equilibrium Boltzmann Boltzmann transport transport –– Tunneling Tunneling –– Discrete Discrete positioning positioning of of dopant dopant atoms atoms –– Electrostatics Electrostatics –– Simulation Simulation
Conclusion Conclusion
Gate Insulator Supply Voltage (Vdd) Delay ~
CV Idrive
Clock Frequency (MHz) 10,000
5V
1,000
Power ≈ 1/2 CV2Fc
100 10
1V
Inversion Layer Charge
1980
1990
2000
Qinv ≈ Dox = εoxEox
Voltage Reduction Achieved by • Reduction in tox ≈ 10A in 2004 • Increase in εox using Plasma Nitrided Oxide (PNO)
1990
2000
Gate Leakage Current 1000
nMOS Gate Current (A/cm2)
≈ εox
Vdd tox
1980
SiON SiO2
100 10 1 0.1 0.01 0.001 0.0001 0.00001
5
10 15 20 25 Equivalent Oxide Thickness (A)
30
Gate Insulator Bad News Breakdown Strength (MV/cm)
Good News 103 102
Gate Leakage
101 100 10-1 10-2
HfSiO/TI SiSC'02 HfSiON/TI HfSiON/Toshiba VLSI '03 HfSiON/Toshiba IWGI '03 SiO2 trendline SiON Novel SiON/Toshiba VLSI '04
10-3 10-4 10-5
1.0
1.5
EOT (nm)
SiO2 (k=3.9) HfO2 (k=21), ZrO2 (k=29) TiO2 (k=60-95)
10
Si3N4 (k=7.5), Al2O3 (k=9)
1 Ta2O5 (k=19-26), La2O3 (k=27), Pr2O3 (k=31) SrTiO3 (k=50-200)
0.1
10-6 0.5
100
2.0
2.5
1
10 100 Dielectic Constant
1000
Hi-k also degrades channel mobility
Metal Gate 6.0 Pt
Valence Band Optimum for PMOS Mid-Gap
Ir
5.20 5.0 4.63 4.5
Optimum for NMOS 4.05
Conduction Band
Work Function (eV)
5.5
4.0
Ta
Zr
In
V Cd Ag Al Nb
Sn Cr Zn
Ti Gate
Hf 3.5
W
Ru Ti Os Mo
La
38A Oxide 3.0
Si 10 nm
Re
Rh
Electrons in Si Stark Effect [001]
∆2
E7
∆2
[010]
∆4
E01
∆E ∆E ≈≈ 75 75 meV meV ∆V ∆Vtt ≈≈ 50 50 mV mV
∆E=∆E10-∆E0
[100]
Modern Modern CMOS CMOS Vertical Vertical Field Field E E ≈≈ 1.2 1.2 MV/cm MV/cm Stark Stark Quantization Quantization results results in in
E11
E2 E1 E0
∆4
E31 E21
Effect of Strain E31 E21
E7 E2 E1 E0
E11
∆2
E01
∆4 210 meV
Bi-axial Bi-axial tensile tensile strain strain of of 1.3 1.3 GPa GPa results results in in ≈ 135 meV ∆E ∆Estrain strain ≈ 135 meV Mobility Mobility increase increase ≈≈ 80% 80% IIdrive increase ≈ 20% drive increase ≈ 20%
Holes in [110] Uniaxially Compressed Si HHS
Si LH,HH
LHS
[110]
Mobility Degrades Mobility Improves
ky
ky | px,py> kx
Unstrained Heavy Hole (HH)
| s,px,py ,pz> kx
Strained Heavy Hole (HHS)
Discrete Channel Dopants
W
=
40 n
m
EC
Discrete Channel Dopants Introduce IOFF Fluctuations and IOFF Degradation
IDS
Discrete Average Discrete Doping
L = 20nm
5X Current Density
Off-Current Filament
Continuum Channel Doping
VGS
Myth of the MOSFET Switch Log Ioff
Vt
φs
In In the the Off Off State State IIDD ~~ ee
Sub-Threshold Sub-Threshold Slope Slope 60 60 -- 100 100 mV/decade mV/decade
-q φs kT
∆ log ID q = kT ∆ VG
VG
Cox + CP log10e Cox ∂ φs ∂VG
For 300mV Ö Ö 55 -- 33 decades decades For V Vtt == 300mV IIon ≈ 1 mA/um on ≈ 1 mA/um ≈ 10 nA/um - 1 uA/um IIoff off ≈ 10 nA/um - 1 uA/um
Electrostatics Critical Scaling Parameters L W tox xjun xdep
tox and xdep are encountering scaling limits. This results in ... kT Cox + CP – Degraded sub-threshold slope Cox q – Increased drain induced barrier lowering (DIBL)
Multi-Gate FETs show promise of extending scaling for several generations beyond planar CMOS
Conclusion
Scaling Scaling CMOS CMOS to to the the “End “End of of Roadmap” Roadmap” will will require require sophisticated sophisticated condensed condensed matter matter physics. physics. –– Gate Gate stack: stack: Atomic Atomic and and electron electron orbital orbital understanding understanding of of this this complex complex material material system system –– Quantum Quantum behavior behavior of of carriers carriers •• High High perpendicular perpendicular E E field field •• Stress Stress –– Non-equilibrium Non-equilibrium Boltzmann Boltzmann transport transport –– Tunneling: Tunneling: Gate Gate insulator insulator and and Drain-to-Substrate Drain-to-Substrate –– Simulation Simulation
Sophisticated Sophisticated condensed condensed matter matter physics physics will will also also be be required required to to invent invent and and develop develop electronics electronics beyond beyond CMOS CMOS –– Single Single Electron Electron Transistor Transistor (SET) (SET) –– Carbon Carbon Nano-tube Nano-tube (CNT) (CNT) –– Molecular Molecular Electronics Electronics –– Spintronics Spintronics –– Quantum Quantum Computing Computing
