Pixel readout chips in deep submicron CMOS for ALICE and LHCb ...

Nuclear Instruments and Methods in Physics Research A 466 (2001) 366–375

Pixel readout chips in deep submicron CMOS for ALICE and LHCb tolerant to 10 Mrad and beyond W. Snoeysa,*, M. Burnsa, M. Campbella, E. Cantatorea, V. Cencellib, R. Dinapolic, E. Heijnea, P. Jarrona, P. Lamannac, D. Minervinic, M. Morela, V. O’Shead, V. Quiquempoixa, D. San Segundo Belloe, B. Van Koningsvelda, K. Wylliea a

EP Division, MIC group CERN, 1211, Geneva 23, Switzerland b INFN Rome, Italy c University and INFN Bari, Italy d University of Glasgow, Glasgow, UK e NIKHEF, Amsterdam, The Netherlands

Abstract The ALICE1LHCB chip is a mixed-mode integrated circuit designed to read out silicon pixel detectors for two different applications: particle tracking in the ALICE Silicon Pixel Detector and particle identification in the LHCb Ring Imaging Cherenkov detector. To satisfy the different needs for these two experiments, the chip can be operated in two different modes. In tracking mode all the 50 mm 425 mm pixel cells in the 256 32 array are read out individually, whilst in particle identification mode they are combined in groups of 8 to form a 32 32 array of 400 mm 425 mm cells. Radiation tolerance was enhanced through special circuit layout. Sensitivity to coupling of digital signals into the analog front end was minimized. System issues such as testability and uniformity further constrained the design. The circuit is currently being manufactured in a commercial 0.25 mm CMOS technology. # 2001 Elsevier Science B.V. All rights reserved.

1. Introduction Because of their capability to provide low noise, low power per channel, and large channel densities, pixel detectors will form an integral part of the detector systems of the Large Hadron Collider (LHC) at CERN. The ALICE experiment [1] will use pixel detectors as part of its Inner Tracking System (ITS) [2]. The LHCb experiment [3] will *Corresponding author. E-mail address: [email protected] (W. Snoeys).

use pixel detectors to detect photoelectrons. A special architecture where two different operating modes can be selected, satisfies the contrasting needs of these two different applications with only one pixel readout chip. The thin gate oxide of present-day commercial CMOS technologies provides radiation tolerance [4,5] if the NMOS part of the circuit is laid out using enclosed NMOS transistors and guard rings [6,7]. In the following the different applications and the dual mode architecture are described. The design implications and effectiveness of the special layout techniques

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W. Snoeys et al. / Nuclear Instruments and Methods in Physics Research A 466 (2001) 366–375

for radiation tolerance will then be discussed, together with the system issues which further constrained the design.

2. One chip, two different applications 2.1. Particle tracking in ALICE The silicon pixel detector in ALICE will form the two layers of the ITS closest to the interaction point. To reduce multiple scattering the mass of the system has to minimized. Tracking precision is required in the r–f direction with a resolution of 12 mm. The nature of the heavy ion collisions will generate high multiplicity events, and the system must be able to cope with a hit occupancy of 1%, even in such a highly segmented pixel detector. Any hits detected by the readout chip must be delayed until the arrival of the Level-1 trigger, which has a maximum latency of 10 ms and a rate of a few kHz depending on the types of particles being collided in ALICE. The duration of the trigger signal is one clock period of the 10 MHz system clock, so the delay of hits must be accurate to 100 ns across this 10 ms. The readout of the pixel chips is initiated by a Level-2 trigger, which has a maximum latency of 100 ms and a rate of a few kHz. To keep the dead time under the specified 10%, the readout of an entire event from the pixel detector system must be completed within 400 ms. The final requirement is that the system be tolerant to an ionising radiation dose of 500 krad, integrated across 10 yr of LHC operation. To reduce the mass of the detector, the silicon sensors will only be 150 mm thick. This implies that the most probable signal produced by a minimum ionising particle will be about 12,000 electrons. Hits detected by the front end will be time-

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stamped according to the system clock and then precisely delayed by means of digital circuitry. All events accepted by the Level-1 trigger will be buffered inside the chip, which allows a number of chips to be readout sequentially using the 10 MHz clock within the required 400 ms. The detector system will be constructed from a number of components. The basic ‘building block’ is a ladder, which consists of 5 readout chips bump-bonded to a single silicon sensor. 4 ladders are aligned in Z to form a stave, and the entire system consists of 60 staves arranged in two barrels around the interaction point. A readout unit is formed by a half-stave of 10 chips, read out sequentially in 400 ms. A half-stave is shown schematically in Fig. 1. The 120 halfstaves of the system are read out in parallel.

2.2. Particle identification in LHCb Encapsulation of a pixel sensor and readout chip within a vacuum tube to form a hybrid photon detector (HPD) has been demonstrated with a number of prototypes [8,9]. This has led to the development of larger area pixel HPDs for the RICH detector in LHCb [3]. Fig. 2 illustrates the concept of the pixel HPD. Photons incident on an optical input window release a photo-electron from a photo-sensitive cathode layer deposited on the inner surface. These photo-electrons are accelerated within the vacuum by a 20 kV potential difference and electrostatically focussed onto an anode which in this case is the pixel sensor and chip. About 100 vacuum-tight feed-throughs are used to provide power and biasing to the chip and to read out the data from the chip, which has about 1000 independent channels when it is operated in LHCb mode (see the next section).

Fig. 1. Schematic of an ALICE half-stave, showing the 10 front-end chips and 2 silicon sensors, readout electronics and connector. The length of a half-stave will be about 20 cm and the width 17 mm.

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average rate of 1 MHz after a latency of 4 ms. To allow readout at average rate and not at peak rate, on-chip buffering is required. To reduce dead time to below 1%, readout of a triggered event has to be completed within 900 ns which is 36 clock cycles for a 40 MHz clock. The encapsulation of the electronics within the vacuum envelope requires compatibility of the chip and its packaging with all manufacturing steps of the HPD. A complete detector system for the RICH of LHCb would consist of 500 HPDs.

3. The pixel cell Fig. 2. Schematic of a pixel HPD.

The pixel detector in the HPD must be sensitive to single photoelectrons. They must also provide a very clean signal, since a high proportion of noise hits will deteriorate the pattern recognition. The accelerating voltage applied to the HPDs will be 20 kV, which generates a signal of around 5000 electrons in the pixel sensor. With a worst case noise floor of about 250 electrons RMS and an average threshold of 1500 electrons, values obtained on a 130 channel prototype [10,11], the threshold is still six times higher than the RMS value of the noise. This should reduce the noise hits to virtually zero. This 1500 electrons pixel threshold is still considerably lower than 2500 electrons which would be the charge per pixel if the photoelectron is incident exactly on the boundary between two pixels and the induced charge is shared equally between the two. Normally pixelto-pixel threshold variations should be folded into these considerations, but with a three bit pixel-bypixel threshold adjust the overall threshold spread obtained was about 25 electrons, which is negligible with respect to the noise floor. A spatial resolution of 2.5 mm by 2.5 mm is sufficient for the incoming photons, but leads to an 8% occupancy in some regions of the RICH detector. The electrostatic focussing de-magnifies an image on the input window by a factor of 5, mapping to a 500 mm 500 mm granularity on the pixel sensor. The LHCb Level-0 trigger will be applied to the front-end chips, and arrives at an

The commercial 0.25 mm CMOS process in which the chip is currently being fabricated offers a high component density and an intrinsic radiation tolerance if special circuit layout is used (see section 6). Both the analog and digital circuitry has been designed to operate with a 1.6 V power supply, and the total static power consumption will be about 400 mW. The sensitive area measures 13.6 mm 12.8 mm, and is divided into 8192 pixel cells of 425 mm 50 mm, arranged in 32 columns and 256 rows. The pixel cell itself is divided into an analog and a digital part, as shown in the schematic of Fig. 3. The analog front-end consists of a pre-amplifier followed by a shaper stage with a peaking time of 25 ns. The design issues for such a front end are discussed in detail in Ref. [11]. Detailed analysis of signal to noise characteristics for charge sensitive front ends can be found in Refs. [12–14]. In the full chip implementation both these blocks are differential, with one input carrying the detector signal and the other tied to a clean reference. This has

Fig. 3. A schematic of the circuitry within one pixel cell.


been done to improve the common-mode rejection of the circuitry and to reduce the sensitivity to digital switching noise injected into the front-end through the substrate. A test input can be given to the pre-amplifier using a voltage step applied across a capacitor. The step size is determined by the voltage difference between two external reference signals which are fed to the chip. An external logic signal triggers the pulse. This scheme avoids having to send an analog test pulse to the chip, which would have to have a fast rise time and be accurate in amplitude. Testing is essential before flip-chip assembly to select known-good die, and afterwards to qualify detector-readout chip assemblies even during system operation. Providing a test input per pixel to allow any pixel in the chip or system to be individually addressed is therefore a key feature of the design. A discriminator compares the output of the shaper with a threshold fixed globally across the chip. In addition, each pixel contains three logic bits which can be used to finely adjust the thresholds on a pixel-to-pixel basis. Together with the global adjusts for every chip (see Section 5) this provides the required pixel-to-pixel uniformity over the full system. The outputs of the discriminators in the pixel matrix provide both a fast-OR and fast-multiplicity signal which are output off-chip. The former gives a digital pulse if one or more pixels are hit on the chip. The latter gives an analog current proportional to the number of pixels hit. Both signals can be used for diagnostic purposes and for triggering as they come immediately after a hit has been detected. The static consumption of the front-end of each cell is 50 mW. The discriminator output is fed into the digital part of the cell. The first stage consists of two digital delay units, whose purpose is to store a hit for the duration of the trigger latency. Each delay unit consists of an 8-bit latch which, on receipt of a hit from the discriminator, latches the bit-pattern present on an 8-bit bus. This pattern is the Grayencoded contents of an up–down counter whose state changes synchronously with the clock and has an adjustable modulo n. Gray-coding was chosen to reduce the digital switching in each clock cycle, and thus reduce the risk of noise coupling

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Fig. 4. The time structure of the pattern used to timestamp hits in the delay units.

into the analog circuitry. The time structure of the pattern is shown in Fig. 4. The contents of each latch are compared with the pattern on the bus and, on each positive comparison, a 2-bit counter is incremented. The third positive comparison occurs at 2n+2 clock ticks after the hit, and a logical one is then presented to the coincidence logic. This state also resets the delay unit. In this case, 2n+2 clock ticks represent the trigger latency and this can be adjusted to meet the requirements of the experiment. The result of the trigger coincidence is loaded into the next-available cell of a 4-event FIFO, which acts as the multi-event buffer and derandomiser. This FIFO is read/write addressable by means of two 4-bit busses which again carry Gray-encoded patterns. The contents of the FIFO cells waiting to be read out are loaded into a flipflop by the Level-2 trigger in ALICE and a corresponding signal in LHCb. The flip-flops of each column form a shift register, and the data is shifted out using the system clock. Finally, there are five latches inside the cell whose contents switch on or off the test input to the front-end, mask or activate a pixel, and provide the three bits of threshold adjustment. These latches have been designed to be resistant to single-event upset (see Section 6). Much attention has been paid to reducing the risk of noise injection via the substrate. In addition to the Gray-encoding of the busses and the differential front-end, the logic cells used in the pixels are current-starved, to minimise any bounce induced in the power supplies during switching.

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4. Operational modes With the addition of some extra logic, this architecture [15] can be used for the two applications described in Section 2. The mode of operation is selected by an external control signal. 4.1. ALICE mode In this mode, each pixel cell acts as an individual channel and the full matrix of 256 32 cells is read out. Using the two delay units, each cell has the capability of simultaneously storing two hits for the trigger latency. The 32 columns are read out in parallel. Using the 10 MHz clock, a complete event is read out from the chip in 25.6 ms. Fig. 5 shows the configuration of the pixel cells in ALICE mode. 4.2. LHCb mode In LHCb mode, eight pixels in the vertical direction are configured as a ‘super-pixel’ of 425 mm 400 mm, which is close to the LHCb requirements of 500 mm 500 mm. The discrimina-

Fig. 5. The configuration in ALICE mode.

Fig. 6. The configuration in LHCb mode.

tor outputs of the super-pixel are OR-ed together and the sixteen delay units of these eight cells are configured as an array. Four of the 4-event FIFOs are connected together to form a 16-event FIFO, which can be written to by any of the sixteen delay units. This meets the required de-randomiser depth for LHCb. The FIFO output is loaded into the flip-flop of the top pixel in the group, which bypasses the other seven during readout. This scheme reduces the matrix to 32 32 cells and allows a complete event to be read out within 800 ns using a 40 MHz clock. Fig. 6 shows the configuration of the pixel cells in LHCb mode. The sixteen delay units are necessary for storing the large number of hits which will occur in the high occupancy regions of the RICH. Additionally, the use of the eight separate analog blocks reduces the effective occupancy seen by the frontend. If the occupancy remained high, then there would be a risk of pulse pile-up and a subsequent loss of hits. Thus, the segmentation of the frontend relaxes the requirements on the return-to-zero time of the pre-amplifier and shaper.


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4.3. Asynchronous operation In addition to the two experiments ALICE and LHCb some other experiments have expressed interest in using this chip. In the case of NA6I [16] the events will not be synchronous to a bunchcrossing clock. The chip will synchronize the trigger pulse to an externally applied clock. For these applications one has to make the chip sensitive for a sufficiently long time after the event to ensure full efficiency by having the trigger pulse last over a few clock cycles if necessary. The important parameter here is the timewalk of the front end. The requirement in LHCb to associate the pixel hits to the correct bunchcrossing or 25 ns interval also puts limitations on this timewalk. Taking the discriminator switching time for a very large charge as a reference, simulations indicate that the discriminator will fire less than 20 ns later for a charge which is 200 electrons above the pixel charge threshold. For such a big chip as the one discussed here, the top-to-bottom line delay within the column is a few ns. Keeping the pixel charge threshold sufficiently below one half times the expected value of the charge generated in the detector, guarantees that at least one pixel will respond within a few ns after the discriminator switching time for a very large input charge. However, a few ns may not be sufficient for a neighboring pixel to react if due to charge sharing it only received a charge slightly over threshold. This indicates that to ensure full efficiency with conservation of position information (i.e. charge sharing information) for particle hits where charge is shared between several pixels the chip should be made sensitive for about 25 ns or more.

5. Periphery, configuration and I/O interface There are forty two 8-bit digital-to-analog convertors (DAC) to provide voltage and current references for the analog front-ends and the current-starved logic. Fig. 7 shows the principle of the current DAC [17]: an operational amplifier circuit is used to guarantee the correct ratio between the currents in two branches. The main reason for this circuit topology is that the low

Fig. 7. Principle of the DAC. The opamp circuit is necessary because accurate NMOS current mirrors for low current could not be made with NMOS transistors in edgeless layout.

Fig. 8. Layout of one DAC : the current source bank is clearly visible at the top. Attention was paid to maintain common center of gravity for the current sources associated with every individual bit.

current levels and the special layout of the NMOS precludes accurate NMOS current mirrors (see Section 6). The bit value determines whether the current associated with this bit is switched into the output or not. The more the current is sent to the operational amplifier input, the lower the output current of the DAC. The layout of one DAC is shown in Fig. 8, the area at the top clearly showing the current source matrix. To avoid nonlinearity errors in the DAC due to transistor parameter gradients on the chip, attention was paid to having the same center of gravity for the

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current sources of all bits. The voltage DACs are constructed from these current DACs by adding a current-to-voltage conversion stage, which was made robust against power supply and transistor parameter variations. A resistor could not be used for reasons of design portability and the lack of characterization of its radiation tolerance. The peripheral logic of the chip contains the counters to address the delay units and the FIFOs. Any memory on the periphery}including the registers controlling the DACs}is constructed from upset-hardened memory cells (see Section 6). The configuration of both the peripheral logic and the matrix of pixel cells is done by means of a serial interface following the IEEE JTAG standard [18]. This has a number of advantages. It allows both the write and read of the configuration settings in the chip, including the test, mask and threshold-adjust states of each pixel. It also allows the reading back of the analog levels generated by the digital-to-analog convertors via an additional output line. Connectivity tests of chips mounted on a stave can be done using the boundary-scan feature of JTAG. Additionally, the JTAG test feature has been adapted to detect bad chips in the serial chain and indicate their location. The width of the ALICE stave restricts the number of lines available for signalling, and for this reason a single-ended standard has been adopted. Gunning Transceiver Logic (GTL) [19] will be used for all the digital signals to and from the chip. This has the advantage of a low signal swing (800 mV) which again reduces the risk of noise injection. Additionally, the output buffers on the chip have an adjustable slew-rate control which can be controlled to match the system requirements. These buffers are powered with a supply separate from that of the rest of the chip. Finally, multiple bonding pads have been provided for the supply lines to reduce the inductance of the connection and limit the supply bounce during switching. The bottom of the chip had to be kept below 2.5 mm to meet the mechanical mounting specifications in ALICE. This severely constrained the design, because sensitive biases had to be distributed individually to each column to avoid systematic column-to-column variations due to

resistive voltage drops in the power supplies [11]. At the top of the chip about 500 mm was available to implement some testing circuitry: for some pixels in the top row analog buffering is provided for preamp and shaper outputs, and also some signals from the digital part of the pixel are buffered and connected to an output pad. These structures, which will be covered by the perimeter (guard) of the detector after bumpbonding, provide a means for detailed diagnostics and characterization.

6. Radiation tolerance 6.1. Total radiation dose tolerance Measurements on MOS capacitors in the early 1980s showed that radiation induced MOS parameter shifts become small for a gate oxide thickness of about 5 nm or below, because in addition to thermal annealing tunneling becomes more and more effective to neutralize radiation induced charge [4,5]. Fig. 9 illustrates that these early measurements are confirmed by

Fig. 9. Radiation induced flat-band shift versus gate oxide thickness. The early measurements on MOS capacitors [4] are confirmed by our measurements on transistors implemented in present-day commercial CMOS process (solid points).


measurements at room temperature on present day submicron transistors for which the gate oxide thickness is in the 5 nm range. Even although the intrinsic transistors become more and more radiation tolerant, commercial CMOS circuits usually fail under ionizing irradiation well below 1 Mrad(SiO2) due to NMOS leakage. This leakage is caused by the formation of an inversion layer underneath the field oxide or at the edge of the active area. This leads to source-to-drain leakage and inter-transistor leakage between neighboring N+ implants. Special process steps prevent this leakage for radiation tolerant technologies. In commercial CMOS this leakage can be eliminated by laying out the NMOS transistors in enclosed geometry (source or drain fully surrounded by poly gate) and introducing P+ guard rings [6,7]. To demonstrate the principle for full mixed-mode circuits two test chips were designed, each containing 130 pixel readout channels [10,11,19]. They were designed in a commercial 0.5 mm and 0.25 mm CMOS technology, respectively. For both chips the supply currents did not vary significantly under irradiation, illustrating on the scale of a full chip that this special layout prevents radiation induced leakage. The chip in 0.5 mm failed at around 1 Mrad(SiO2) due to radiation induced threshold shifts. The gate oxide thickness of about 10 nm for this process (see Fig. 9) still leads to significant transistor threshold shifts and caused the input transistor of the shaper to be pushed out of saturation resulting in a drastic decrease of the gain of the shaper. For the same threshold setting, this required a much higher input signal to exceed the threshold of the discriminator, and hence resulted in a much higher effective pixel charge threshold. In the second prototype, designed following the same principles, the thinner gate oxide of about 5 nm made the radiation induced threshold shift very small, and allowed the prototype to remain fully functional at least up to 30 Mrad(SiO2). All this is illustrated in Fig. 10. For a 10 keV X-ray irradiation at 4 krad(SiO2)/ min it can be seen that the 0.5 mm chip remained functional up to 800 krad. The oscillation in the beginning is due to annealing which took place during the measurement in spite of efforts to measure the chip as fast as possible in between the

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Fig. 10. (a) Radiation induced average pixel charge threshold and threshold spread for the test chip in 0.5 mm CMOS technology, (b) and (c) for the 0.25 mm CMOS test chip. This data confirms on the scale of a full chip the significant improvement provided by a thinner gate oxide, and hence the importance of opting for a deep submicron technology.

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irradiation cycles. At about 1 Mrad the threshold is already very high. On the contrary, Figs. 10b and c show the little variation for a 30 Mrad irradiation for the 0.25 mm testchip. These measurements confirm at the full-chip scale the improvement obtained for a thinner gate oxide, and indicate the importance of opting for a deep submicron technology with a thinner gate oxide. 6.2. Tolerance to single event effects Apart from long term degradation, radiation can also affect electronics operation through single event effects. Single event upset (SEU) where logic data is altered, and single event latch-up (SEL) where a parasitic thyristor is turned on and draws a large current, are particularly relevant. The technique to use enclosed NMOS transistors and guardrings severely reduces the risk of electricallyor radiation-induced latch-up [20–22]. In fact, P+ guards are in effect very good P-substrate contacts (or P-well contacts as the case may be), and good substrate (and/or well) contacts are a standard means to reduce the probability to turn on parasitic thyristors and to create a latch-up. All digital storage elements in the chip have been designed to be immune to SEU. They use a special latch which has been designed to recover its original state following an upset: two nodes in the design would have to be upset simultaneously for their content to be altered [23–25]. Redundancy for increased SEU immunity can also be added in other ways such as majority-voting schemes. 6.3. Design implications The technique to implement all NMOS transistors in this enclosed layout has severe design implications. Firstly, the transistor models have to be updated and the transistor has become asymmetric (the I–V characteristics depend on whether the current flows inside out or outside in). The enclosed layout for the NMOS precludes small W/L ratios (e.g. 0.1 would be impossible) in a reasonable area. This implies weak inversion operation for low currents in the NMOS, and hence the difficulty to make accurate NMOS current sources which have to operate at low

current. As pointed out earlier, this leads to the use of the opamp circuit in the DAC of Fig. 7. In addition, the non-uniform current flow causes non-uniform weighting of different areas under the gate and leads to device mismatch worse than the traditional predictions especially for large gate lengths. Moreover, as these circuits are intended for use in radiation environments, all parameters need to be characterized both before and after irradiation. More details on all this can be found in [26]. In addition to the transistor models, many of the design verification routines need to be updated to effectively use enclosed transistors. For instance, these transistors need to be extracted correctly from the layout for layout-to-schematic verification and for circuit re-simulation after extraction. Dedicated digital libraries need to be developed [27], where loss in density and speed-power performance is unavoidable in comparison to their standard counterparts. However, the alternative to this approach is to use standard radiation hardened technologies, and those lag a few generations behind the most advanced commercial CMOS technologies in terms of minimum linewidth [28]. Comparing to a standard layout in a 0.6 mm technology which would be state of the art for a radiation hardened technology, one still gains in area with two metal layers for a layout with enclosed NMOS transistors and P+-guards in this standard 0.25 mm process. Using more metal layers in commercial deep submicron technologies increases the density gain. Also the comparison in power-speed performance is favorable: an inverter biased at 2 V with fan-out of 1 is 2.4 times faster than its standard counterpart in 0.6 mm biased at 3.3 V, and consumes 10 times less power. For analog circuitry, no significant density penalty is incurred (comparing to the same technology with standard layout) if circuit topologies relying on accurate NMOS current mirrors are avoided.

7. Conclusions The ALICE1 chip has been designed with an architecture which provides the functionality required by both the ALICE tracker and the


LHCb RICH. The choice of a deep sub-micron CMOS technology (0.25 mm) has allowed the inclusion of a large amount of functionality within each pixel to meet the demands of both experiments. In addition, this technology provides radiation tolerance beyond 10 Mrad if special circuit layout is used, but this has severe design implications. The importance for radiation tolerance of opting for a deep submicron technology with a thinner gate oxide has been demonstrated both at the transistor and the full-chip level. Upset-hardened memory cells were used wherever necessary. Limiting switching noise, testability and uniformity were issues which further constrained the design to make it suitable for operation in systems containing a large number of chips. The chip is currently being manufactured. Acknowledgements We would like to thank the organizers of this conference for having given us the opportunity to present this paper. We also thank our colleagues from the ALICE ITS, LHCb RICH collaborations and the MIC and EDO groups at CERN.

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