Practice Problems 4

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Draw a diagram for a circuit that implements the VHDL module shown below. Your diagram may include gates, ... constant td: testData := (. -- key val insert delete ...
CSE/ESE 260M – Introduction to Digital Logic and Computer Design

Practice Problems 4

1. Draw a diagram for a circuit that implements the VHDL module shown below. Your diagram may include gates, muxes and one or more 8 bit subtractors (that is, a circuit with two 8-bit inputs x and y and an 8 bit output equal to the difference xy). Assume that the type of word is an 8 bit std_logic_vector. entity foo is port(A, B: in word; U, V: out word); end foo; architecture bar of foo is function negate(en: std_logic; x: word) return word is begin if en = '0' then return x; else return (x'range => '0') - x; end if; end function negate; function absVal(x: word) return word is begin return negate(x(x'high),x); end function absVal; function absDiff(x, y: word) return word is begin return absVal(x-y); end function absDiff; begin U