Previous years lecture slides - Computer Science and Engineering

CSL316: Digital Hardware Design Computer Science & Engineering Department I.I.T. Delhi

Copies of old Lecture Transparencies Instructor: M. Balakrishnan

S.No.

Topic

No. of Slides

No. of Lectures

1.

Introduction

20

2

2.

Review of Combinational Circuit Design

56

5

3.

Sequential Circuits

83

7

4.

Asynchronous Circuits

25

3

5.

Microprogrammed Control

60

5

6.

Introduction to VHDL

34

3

7.

Testing of Digital Circuits

58

5

8.

Advanced Topics

37

4

Introduction • What are digital systems ?

Digital Hardware Design • Applications M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 1: Introduction

• Design steps

1

Chapter 1: Introduction

Representation

Advantages Over Analog

• Discrete time for signals – Clock for synchronous systems

• Programmability • Predictable accuracy • Maintainability

• Quantized for all types of data – Binary number representation Chapter 1: Introduction

Though Analog systems are still used at very high frequency 3


Applications Nature of Application • Real time computing

4

Digital System Examples

Time Constraints Hard

• Interactive computing

Soft

• Off-line computing

-


2

5

• • • • •

Consumer electronics Radar & sonar processing Control systems General computing Mobile computing


6

1

System Design Steps

Specification Language • English(/any natural language) – Ambiguous and not suitable for processing by machine • Hardware description language – Machine simulatable/executable but difficult to write

Specification Verification Synthesis Verification Circuit Chapter 1: Introduction

7


8

Synthesis Methodologies Digital Systems Development Technology & Issues

Synthesis refers to the transformation of specification (behavior) to realization (structure) • Manual

M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

– Ad-hoc – Procedural

• Automated Chapter 1: Introduction

9

Development of Digital Systems • • • • •

SSI: Small Scale Integration MSI: Medium Scale Integration LSI: Large Scale Integration VLSI: Very Large Scale Integration SOC: System on Chip



10

Driving Factor: Semiconductor Technology • Key parameter (feature size) – Distance between two conducting lines – Size of the transistor 50.0 micron to 0.12 micron

• Driving Device: Memory 11


12

2

Impact on Cost

Impact on Performance

• Area is the measure of cost • Minimizing logic is less important • Interconnection area is very significant in relation to logic area • Pin count and testing becoming a significant part of the manufacturing cost

• Speed (mainly clock speed in synchronous systems) is the measure of performance • Interestingly speed increases automatically with feature size reduction • Interconnect delays very significant • At high speed, interconnects start behaving like transmission lines



13

Impact on Power

14

Design Levels • Transistor level

• CMOS is the dominant technology • Power as a major design metric along with area and delay • Low voltage operations • Special packaging and cooling technologies

• Gate level • RTL level (register transfer level) • Algorithm/behavioral level


15

Classification: Design Methodologies


Classification: Combinational or Sequential

• Processors:

Instruction set (intermediate)

• Combinational

• ASICS:

Top-down

• Synchronous (sequential)

• Memories: Bottom-up (other library cells as well) Chapter 1: Introduction

16

• Asynchronous (sequential)

17


18

3

Course Outline

Course Outline (contd.)

• Combinational circuit design – review, MSI blocks, iterative

• Sequential circuit design – FSM, RTL blocks

• Asynchronous sequential circuit design Chapter 1: Introduction

19

• • • • •

Behavioural design with VHDL Datapath and control division Microprogrammed control Testing Low power design


20

4

Combinational Circuit: Definition Review of Combinational Circuit Design M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 2: Combinational Circuits

Inputs

Outputs

f O = f (I)

Present output(s) is a function of present inputs only. 1

Boolean Functions

Chapter 2: Combinational Circuits

2

Canonical Representation

• AND, OR, NOT, NAND, NOR, EXOR etc. • Sum of minterms • Unique truth table • Total of 24 2-input functions

• Product of maxterms

• Universal gate set {NAND}, {NOR} etc. Chapter 2: Combinational Circuits

3


4

Karnaugh Map

Karnaugh Map (contd.)

y = f(a,b,c,d) = Σ (0,3,4,7,8,11,15)

y = f(a,b,c,d) = Π (1,5,9,13,15)

cd 00 ab 00 01 11 10

01

11

1 1 1


cd 00

10

ab 00 01 11 10

1 1 1 1 5

01 0 0 0 0

11

10

0


6

1

Duality

Minimization Objectives

• Replace the following and any equality will hold – AND by OR and vice-versa – 0 by 1 and vice-versa

• Number of literals for cost/area • Number of levels for time

• Demorgon’s laws – (a + b)’ = a’.b’ – (a.b)’ = a’ + b’ Chapter 2: Combinational Circuits

7


8

Symmetric Functions • Exchange variables and the function does not change – e.g. parity function

Combinational Circuit Design using MSI Blocks M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi


9

Incompletely Specified Functions


10

Why Incompletely Specified Functions ?

y = f(a,b,c,d) = Σ m(2,3,4,5,6,8,9) + Σ d(10,11,12,13,14,15)

cd 00 ab 00 01 11 10

01

11 1

1 1 X

1 1 X

X X


• Outputs actually do not matter for certain subset of inputs

10 1 1 X X

• A subset of inputs do not (or cannot) occur

11


12

2

Combinational MSI Blocks (contd.)

Combinational MSI Blocks Blocks for implementing logic • Decoders • Encoders • Multiplexers • ROMs • PLAs Chapter 2: Combinational Circuits

Arithmetic MSI Blocks • Adders • Subtractors • ALUs • Comparators 13

y = f(a,b,c) = Σ m(0,3,4,6,7)

• n to 2n decoder

15


16

Logic Implementation Using Multiplexers

Multiplexer

y = f(a,b,c) = Σ m(0,1,3,5,6)

2n:1 Multiplexer (n select lines)


14

Logic Implementation Using Decoders

Decoder



17


18

3

Logic Implementation Using Multiplexers (contd.)

ROM (Read Only Memory)

y = f(a,b,c) = Σ m(0,1,3,5,6)

2n × m ROM (n address and m outputs)

0 1 2 3 a’ 1 1 0 1 a 0 1 1 0


19

Implementing Logic Using ROMs

20

PLA (Programmable Logic Arrays) PLASpecification: n × k × m (N inputs, K product terms and M outputs)

• Direct implementation of the function • Extremely flexible as reprogramming can implement a completely different function



21

Implementing Logic Using PLAs

AND Plane

OR Plane


22

Implementing Logic Using PLAs (Example) y1= ab + b’c’d’

y2 = ab + bc’ + c’d’

• Direct implementation of SoPs • Implement product terms in the AND plane • Implement sum in the OR plane

a


23

b

c

d


y1

y2

24

4

Summary To implement a n-variable function (with k minterms) • n to 2n decoder + k input OR gate • 2n:1 multiplexer • 2(n-1):1 multiplexer + 1 inverter • 2n×1 ROM • n× p× 1 PLA with p ≤ k Chapter 2: Combinational Circuits

25

3 to 8 Decoder


M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 2: Combinational Circuits

26

4 to 16 Decoder

27

Coincident Decoding


Combinational Circuits using Multiple Modules


28

4:1 Multiplexer

29


30

5

Tri-State Buffer

4:1 Mux Using Tri-state Outputs

Input = { 0 , 1} Output = { 0, 1, Z } Chapter 2: Combinational Circuits

31


32

ROM Pin Connections

64×1 ROM

2n×m ROM


33


34

Adder ai

bi

Iterative Circuits ci-1 M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 2: Combinational Circuits

1 - bit Full Adder si

35

ci si = ai + bi + ci-1 ci = ai.bi + ci-1(ai + bi)


36

6

Comparator

ai

bi

ai gi-1 ei-1 li-1

Even-Odd Detection

gi ei li

1-bit comparator

ci-1

ei = e i-1.(ai’bi’ + ai.bi) gi = ai.bi’ + g i-1.(ai’bi’ + ai.bi) li = ai.bi’ + l i-1.(ai’bi’ + ai.bi) Chapter 2: Combinational Circuits

37

Iterative Pattern Recognition P = ‘1101’ X = Input Y = Output yi =


Pattern Recognition: Example ci-1

xi

ci

yi

00 00 01 01 10 10 11 11

0 1 0 1 0 1 0 1

00 01 10 01 00 11 10 01

0 0 0 0 0 0 0 1


38

Pattern Recognition: Example 00 if no match till now 01 if 1-bit match till now 10 if 2-bit match till now 11 if 3-bit match till now

1 if = ‘1101’ 0 otherwise 39

ci

Detecting Number of 1’s in a pattern is even/odd ci = 1 if number of 1’s among a0 to ai is odd 0 otherwise

ci =


1 - bit Cell


40

Pattern Recognition: Example xi

c1i-1

c1i = Σm (1,3,5,7)

c2i-1

yi = Σm (7)

c2i = Σm (2,5,6)

c1i c2i

yi 41


42

7

Simplification of Boundary Cells In each case boundary cells can be simplified • Adder circuit: LSB can be half adder • Comparator: Only equal input for LSB • Pattern recognizer: LSB 3-bits can be simplified Chapter 2: Combinational Circuits

43

Multi-bit Iterative Circuits xi

c1i-1

Iterative structures are regular but slow as delay adds up. Techniques used to speed up are • Multi-bit inputs per cell • Carry lookahead generators


44

Carry Lookahead Generation

xi+1

2 - bit iterative cell

Speeding Up Iterative Structures

Generate gi = ai.bi Propagate pi = ai+bi C1i+1 C2i+1

c2i-1

yi

yi+1


45


46

QM vs. K-Map Logic Minimization: Tabular Methods M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 2: Combinational Circuits

47

• K-Map is a graphical method and thus not suitable for large no. of variables • K-Map method is also not suitable for programming • QM (Quine-Mcluskey) method does not suffer from these disadvantages


48

8

QM Method: Example

Combining Minterms: Conditions

y = f(a,b,c,d,e) = Σm(0,6,7,8,20,22,24,26,30,31) Classify by number of 1’s in the binary rep. No. of 1’s

Minterms

0 1 2 3 4 5

0 8 6, 20, 24 7, 22, 26 30 31


49

Generation of Implicants

Two minterms can be combined to form a implicant (I) if and only if: • The integer values of the two minterms differ by 2k for some k ≥ 1 • The minterm with a larger integer value has more 1’s than the minterm with a smaller integer value Chapter 2: Combinational Circuits

50

Prime Implicants

0 0

A prime implicant is which is not fully contained in any other implicant i.e. there is no other implicant which contains all the minterms contained in this implicant.

1 8 2 6, 20, 24 3 7, 22, 26 4 30 5 31


51

Cover Table (0,8)

(6,7)

(6,22)

(22,30)

(30,31)

52

Essential Prime Implicants Essential prime implicants are those which cover minterm(s) not covered by any other prime implicant.

(20,22,24,26)

0 6 7 8 20 22 24 26 30 31



Any minimal function have to include the essential prime implicants

53


54

9

QM Method for Incompletely Specified Functions

QM Method: Steps • Order minterms by no. of 1’s (integer value) • Generate implicants by repeated combination of minterms and implicants • Identify prime implicants • Prepare a cover table • Identify essential and other implicants to cover all the minterms • Express the function as a sum of selected PIs

• Use don’t care minterms for generation of the implicants



55

• Ignore don’t care minterms during the covering process

56

10

Definitions Sequential Circuits : Definitions and Classification M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 3: Sequential Circuits

1

Classification

Chapter 3: Sequential Circuits

2

Representation

• Finite memory : Only a finite number of past inputs are required to generate the present output e.g. pattern recognition • Infinite memory : All the past inputs are required to generate the present output e.g. parity generator Chapter 3: Sequential Circuits

Machine M is a five tuple M = < I, O, S, f, g > • I : Input set • O : Output set • S : State space • f is a function mapping I Χ S ⇒ O • g is a function mapping I Χ S ⇒ S 3

Parity Generator Example • Define two states • S0: Number of 1’s received till now is even • S1: Number of 1’s received till now is odd

• Output is a function of not only the present input but also past inputs • In synchronous sequential circuits (one under discussion right now) the time is discretised using clock input • State captures the “relevant” history of inputs in a compact form


4

Pattern Recognition Example P = ‘1101’ S0: No match till time t S1: 1-bit match till time t S2: 2-bit match till time t S3: 3-bit match till time t

S0

S1

S0

S1 S2 S3


5


6

1

Temporal Iteration vs Spatial Iteration • Iterative Circuits:

Spatial iteration

• State machines:

Temporal iteration


Mealy Machine f: I Χ S ⇒ O o(t) = f(i(t), s(t)) g: I Χ S ⇒ S s(t+1) = g(i(t), s(t))

7


Moore Machine

State Encoding Consider a machine with n states and say k bits are required to encode it • 1-hot encoding: k=n kC ≥ n • 2-hot encoding: 2 • Minimal encoding: k = ⎡log2n⎤ • Any other encoding: n ≥ k ≥ ⎡log2n⎤

f: S ⇒ O o(t) = f(s(t)) g: I Χ S ⇒ S s(t+1) = g(i(t), s(t))


8

9


10

Terminology Sequential Circuits : State Equivalence & Minimization M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 3: Sequential Circuits

11

• • • •

Equivalent states Distinguishable states k-equivalent states k-distinguishable states


12

2

Parity Generator Example

Pattern Recognition Example

0/0

• States S0 and S1 are 1-distinguishable

0/0

S0 1/0

1/1

Pattern = ‘1101’ S0, S1 and S2 are 1-equiv. S2 and S3 are1-disting. S0 and S1 are 2-equiv.

S1

State Machine Minimization • Identify equivalent states

15

Proof: State Equivalence Theorem

Si

Sj

α⁄β

Si1

Sj1



S2 1/0 1/1 S3 14

Theorem for State Equivalence Two states Si and Sj are k+1 equivalent if and only if • they are k-equivalent • and their next states for all inputs are kequivalent

• Replace equivalent states by one state

α⁄β

S1 0/0

0/0

13


1/0 1/0 0/0

0/1 Chapter 3: Sequential Circuits

S0


16

Minimization Steps • Consider all states to be 0-equivalent • Identify 1-equivalent partition P1 based on outputs • repeat – identify i+1 equivalent partition Pi+1 based on Pi until (Pi+1 = Pi) • Replace each set of states in a Pi class by a state and define state transitions accordingly

Sik+1

Sjk+1

17


18

3

State Minimization: Example (contd.)

State Minimization: Example P0 = {Si,S0,S1,S00,S01,S10,S11} P1 = {(Si,S0,S1,S00,S10,S11)(S01)} Si P2 = {(Si,S0,S00)(S1,S10,S11) 1/0 0/0 (S01)} S0 S1 P2 = {(Si,S0,S00)(S1,S10,S11) 0/0 1/0 (S01)} 0/0 1/0 S00

S10

S01

S00

19

a

1/0

S0 0/0

S11


0/0

Si 0/0

1/0

S1 1/0

S10

0/0 S01

b

1/0 1/0 S11

0/0 0/0

1/1 c


20

Equivalent Mealy & Moore Machines • Mealy → Moore

State Machine Synthesis

– For every state with distinct outputs on incident edges, split it into as many states as number of distinct outputs – Associate the edge output with the state – Redirect the edges appropriately – Define the new edges from the split states as per the original Mealy machine Chapter 3: Sequential Circuits

21

Equivalent Mealy & Moore Machines

M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 3: Sequential Circuits

Transforming Mealy to Moore: Example 0/0

• Mealy → Moore – For every state with distinct outputs on incident edges, split it into as many states as number of distinct outputs – Associate the edge output with the state – Redirect the edges appropriately – Define the new edges from the split states as per the original Mealy machine Chapter 3: Sequential Circuits

22

23

0

S0

S00/0 1/0

1/1

S1 0/1 Chapter 3: Sequential Circuits

1

1

S11/1 0 24

4

Equivalent Machines: Waveforms

Transforming Moore to Mealy: Example

Clk

0/1

A/0

0

1

1/0

X

x Mealy

S0

S1

S1

S1

S0

Moore

S00

S11

S11

S11

S00


25

State Register Realization

0

0/1

AD

27

1/1

C

1


26

Q(t)

Q(t+1)

T(t)

0 0

0 1

0 1

1

0

1

1

1

1


28

State Machine Realization (contd.)

State Encoding

X

PS

NS

Excite (T)

Y

0

00

01

01

1

1

00

10

10

0

1/0

AD

00

X

01

00

01

0

C

B

01

0

10

00

10

1

10

1

10

01

11

1

X/0 B

D/1

1/1

B

Excitation Table: T Flip-flop

State Machine Realization

0/1

C/0 0

A set of Flip-flops • SR flip-flop Q(t+1) = R’(t)Q(t) + S(t) S(t)R(t) = 0 • JK flip-flop Q(t+1) = K’(t)Q(t) + J(t)Q’(t) • D flip-flop Q(t+1) = D(t) • T flip-flop Q(t+1) = T’(t)Q(t) +T(t)Q’(t) Chapter 3: Sequential Circuits

X/0

1

B/1

0/1

AD

C Chapter 3: Sequential Circuits

29


30

5

Circuit Realization x

Steps in State Machine Synthesis • • • • •

Convert the description into state machine Minimize the state machine Encode the states Choose a set of flip-flops for state register Use the excitation table to arrive the specification of the combinational logic • Synthesize the combinational logic

y Comb Logic

T1 T2 Chapter 3: Sequential Circuits

31


32

Registers & Latches State Machine Implementation Using Registers & Counters M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi

• An array of flip-flops • Edge triggered are generally referred to as registers while latches are level triggered (transparent latches) D

Q

Clk Chapter 3: Sequential Circuits

33

Register & Latch Waveforms


34

Register Control Variations

Clk D Level LD/EN

LD

OE

Edge Chapter 3: Sequential Circuits

35


36

6

Counters

Ripple Counter

• Ripple counter • Synchronous counters

T Q

– Synchronous controls – Asynchronous controls – Mixed controls

TQ

TQ

T Q

Clk Q0 Q1


37


Ripple Counter

38

Synchronous Counter

• Advantages – Simple low cost design – High speed operation possible if outputs are not required to be synchronous

T Q

TQ

TQ

T Q

Clk

• Disadvantages – Delay = no. of bits × flip-flop delay – Illegal transient states

Q0 Q1


39


Cascadable Synchronous Counters

Faster Synchronous Counter

T Q

TQ

TQ

T Q

40

En

ENT ENP

C

ENT ENP

C

ENT ENP

C

ENT ENP

C

Clk Carry delay is spread over 16 clock cycles Chapter 3: Sequential Circuits

41


42

7

Synchronous Counter with Synchronous Controls

Design Example: Mod 10 Counter s(t) + 1 if 0 ≤ s(t) ≤ 8 0 otherwise

S(t+1) =

D

Q

Synch Count

Counter

Clr

Clk Clr En Ld Chapter 3: Sequential Circuits

43

State Encoding

0/1

A

1/1

Clr


44

X

PS

NS

En, Clr, Ld

D

0

00

01

100

X

1

00

10

001

10

1/0

A

00

X

01

00

010

X

C

B

01

0

10

00

010

X

C

10

1

10

01

001

01

X/0 B

Dec 10

State Machine Realization (contd.)

State Machine Realization

0/1

Async Count

Dec 9


45

Circuit Realization


46

Sample Counter Specification Clr Ld En Clk D Q(t+1)

x

y Comb Logic D Q (PS)


1

X

X

X

X

0

0

1

X

r

D

D

0

0

1

r

X Q(t) +1

En, Clr, Ld

C N T

47


48

8

Steps in State Machine Synthesis using Counters • Encode the states • Choose a counter with appropriate control inputs to implement the state register • Use the counter functionality table to arrive at the spec. of the combinational logic • Synthesize the combinational logic


49

Steps in State Machine Synthesis using Counters

Multiple State Machine Implementation & Clock Period M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 3: Sequential Circuits

Applications of Sequential Machines

• Encode the states • Choose a counter with appropriate control inputs to implement the state register • Use the counter functionality table to arrive at the spec. of the combinational logic • Synthesize the combinational logic

• Pattern matching



51

– Overlapped or non-overlapped – Blocked or non-blocked

• Sequential decoding • Controllers • Memory based circuits

Interacting State Machines : Example • Search for a pattern P = ‘1101’ within blocks of 256 bits. The pattern should not cross block boundaries. • Design two state machines M1 and M2 – M1 is a modulo 256 counter – M2 is the pattern recognizer

0/0 A S0 S255

0/0

1/0 B

S1

1/0 S2

53

52

Example (Contd.)

• The 256th transition of M1 should initialize M2 Chapter 3: Sequential Circuits

50

1/1

1/0

C 0/0

0/0

D Chapter 3: Sequential Circuits

54

9

Example (Contd.)

Example (Contd.) 00,1x/0 00,1x/0

x -/1 M1

M2

y

S0

S255

A

-/0

01/0 1x/0

S1

-/0

B 01/0

-/0

Clk 55

Design Summary: Example • M1 : • M2 :

8-bit free running counter Counter with synchronous clear which dominates x

M1 8-bit Cntr

Clr

M2 Logic + 2-bit Cntr


56

Register & Latch Waveforms Clk S254

S253

Cntr y

00/0 X0/0, 11/1 D

01/1

-/0


01/0

C

S2

S0

S255

S1

Mod256


57


58

Multiple State Machines: Another Example

Second Example (Contd.)

• In a bit stream, count the number of “@” (ASCII Code) characters in blocks of 256 8bit characters • Three state machines: M1, M2 and M3

Specification of M1 y1 = 1 if = “@” and t mod 8 = 7 y2 = 1 if t mod 8 = 7

– M1: Pattern recognizer for “@” character – M2: 8-bit counter for counting 256 characters – M3: 8-bit Counter for counting no. of “@”

x

M1

y2

En

M2

y1

En

M3

Clr y


59


60

10

Clock Period Comb Logic

x

Clock Period Computation

y NS

PS SR Clk tsu

to: tns: td: tsu:

Critical path delay (x,PS) to y Critical path delay (x,PS) to NS SR delay Setup time of the SR

th:

Hold time of the SR

th

tclk ≥ max{ td + to, td + tns + tsu }


61


62

Classification of Memory Devices • ROM

Designing with Memories

– ROM, PROM, EPROM, EEPROM, UVPROM

• RAM – SRAM (Static RAM) – DRAM (Dynamic RAM)

M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 3: Sequential Circuits

63


SRAM Device Signals

64

SRAM Timing Adr

Address rd/wr

SRAM

Data

Rd/wr

cs

Data Chapter 3: Sequential Circuits

65


66

11

Circuit Example using Memory

Reading Memory in a SM

DBUS ADBUS

RO S1

Inc_Adr

RAM

Adr

S2

RI

Ld_Dat_Reg

Rd/Wr Chapter 3: Sequential Circuits

En_Adr_src

67

Writing Memory in a SM


68

Dynamic RAM Device Signals Address

S1

ras

Adr

cas

Data

rd/wr cs

S2

Data_out

SRAM Data_in

S3

Wr Chapter 3: Sequential Circuits

69


70

DRAM Timing System Design Case Studies

Adr ras


cas Chapter 3: Sequential Circuits

71


72

12

Data-Control Partition

Data Part

Status signals

Steps in System Design • Choose an algorithm • Identify the data modules (operators & storage) • Identify the control signals • Extract the state machine for control • Implement the state machine to complete the design

Control Part

Control signals Chapter 3: Sequential Circuits

73

Case Study1: GCD Computer

x

z


75

GCD Computer: Data Part

Comp

R3


GCD Algorithm


76

Modified GCD Algorithm (RTL) R1:= x, R2:= y; while ( R1 ≠ R2 ) do

R2

R1

74

Input x, y; while ( x ≠ y ) do if ( x > y ) then x := x - y else y := y - x endif; endwhile; z := x; end.

GCD Computer

y


if ( R1 > R2 ) then R1:= R1 - R2 else R2:= R2 - R1 endif; endwhile; R3:= R1;

SUB

77


78

13

GCD Computer: State Diagram S1

x

S2 S5

S4

GCD Computer: Interface

z GCD Computer

y

eoc

start

S3


79

Case Study 2: FIFO


FIFO: Data Part

Data Out

Data In FIFO

full

80

empty

Head

Memory

Tail

add

f

e

delete Chapter 3: Sequential Circuits

81


82

FIFO: State Machine

S0 S3

S1

S4

S2


83

14

Terminology • Input State • Secondary or internal state • Secondary or internal variables • Fundamental mode

Asynchronous Circuits M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 4: Asynchronous Circuits

1

z

x

Comb. Logic Y

y Delay

Chapter 4: Asynchronous Circuits

Illustrative Example

2

Total States

Consider a circuit with 2 inputs (x1 and x2) and 1 output (z). The output is “1” only when x1 and x2 are “1” with x1 being “1” first.

x1 x2

x1 z x2 z

1


3

3

4

1

4

5

1


Primitive Flow Table

4

Merger Graph

x1,x2

00

01

11

10

1

1 ,0

4

-

2

2

1

-

3

2 ,0

3

-

4

3 ,1

2

4

1

4 ,0

5

-

5

-

4

5 ,0

2


2

5

• Identify compatibility • Identify cliques

1 2

4

A B

(1,2,3) (4,5)

3 5


6

1

Reduced Flow Table

Final State Table

x1, x2

00

01

11

10

x1, x2

00

01

11

10

A

1 ,0

4

3 ,1

2 ,0

0

0 ,0

1 ,0

0 ,1

0 ,0

B

1

4 ,0

5 ,0

2

1

0 ,0

1 ,0

1 ,0

0 ,0

z = y’x1x2 y = x1’x2 + yx2 Chapter 4: Asynchronous Circuits

7


8

Asynchronous Circuit Asynchronous Sequential Circuit Design

z = y’x1x2 y = x1’x2 + yx2

M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 4: Asynchronous Circuits

9


Another Example

10

Total States

Consider a circuit with 1 input (x ) and 1 output (z). The output should suppress every alternate pulse on the input starting with the first.

x

x z z Chapter 4: Asynchronous Circuits

1 11

2

3

4

1


12

2

Primitive Flow Table x

0

1

1

1 ,0

2

2

3

2 ,0

3

3 ,0

4

4

1

4 ,1

State Encoding • Let us choose the following encoding 1 2 3 4


13

Final State Table y1 0 0 0 0 1 1 1 1

y2 0 0 1 1 0 0 1 1

x 0 1 0 1 0 1 0 1

Y1 0 0 1 0 1 1 0 1


: : : :

00 01 10 11


14

Asynchronous Circuit

Y2 0 1 0 1 0 1 0 1

z 0 0 0 0 0 1 0 1 15

z = y1.x Y1 = y1’.y2.x’ + y1.y2’+y1.x Y2 = x


16

Races & Cycles State assignment of secondary states could result in races and cycles. • Races


– Critical – Non-critical

• Cycles Chapter 4: Asynchronous Circuits

State Assignment in Asynchronous Circuits

17


18

3

Illustration for Races & Cycles

State Assignment

x1x2 y1y2

00

01

11

10

x

0

1

x

0

1

00

11

00

10

01

1

1

2

00

00

01

01

11

00

10

01

2

3

2

01

10

01

11

11

00

10

11

3

3

4

10

10

11

4

11

00

11

10

11

10

10

4

11


1


19

Alternative State Assignment x

0

1

x

0

1

1

1

2

00

00

01

2

3

2

01

10

01

11

10

00

10

3

3

4

11

4

1

4

10


Transition Graph Transition Graph is drawn to capture adjacency requirements

1

3

1

4

2

2

3

1

4

2

3

3

1

4

3

4

3

4

4

3


(01) (10)

(11)

(11)

(11) (11) (10)

4

23

2

1

2

1

3

22

Transition Diagram

(01) (10)

(01)

4

3


21

00 01 11 10

2

1

Another Transition Table x1x2 y1y2

20

3

x1x2 00 0 1 1

2

01 11 10 3 4 4 4

4 (11) (10)


24

4

Additional Permanent States 0 1 00 a

y1y2 y3y4

00 01 11 10

a

00

a

b

e

e

01 b d

01

a

b

f

f

11 b d

11

c

c

e

f

10 c

10

d

d

e

f

c


25

5

Data-Control Partition Microprogrammed Control Data Part


Control Part

Control signals

Chapter 5: Microprogrammed Control

1


Control Unit Design Options • Adhoc Design – Combination of MSI & SSI modules – Starting from a state machinedescription

• Microprogrammed control – Starting from a RTL description or even a modified state machine description 3

2

Terminology • • • • • • •

• Random logic implementation


Status signals

Microprogram Microinstruction Microoperations Microinstruction format Microsequencer Control/Microprogram ROM Microinstruction register


4

Microprogrammed Control: Advantages & Disadvantages

Block Diagram

• Advantages Seq

Control ROM

R E G

Data Part

– Flexible and structured design – Testing sequences can be easily incorporated – Easy to document and debug

• Disadvantages – Expensive especially for small designs – Slower than random logic


5


6

1

Microinstruction Format 2

1

3

Component Sizes • Data Part:

4

1: Data Part Control Signals 2:Sequencer control/action select 3: Status control select 4: Next address w (word length) = m + k + s + n

• Microsequencer: • Status mux:

m k s n


• Control ROM: • Microinst. Reg.: 7


Labeled Block diagram

Seq n

Control w R E ROM

m

k MUX


s

8

Clock Period Computation

Data Part

G 1

m control inputs, S status outputs k+1 inputs, n outputs S status inputs, s select lines, 1 output N Χ w bits w bits

S

9

• • • • • •

tdp :Maximum delay in data part tstatus : Maximum delay for status gen. tsta_mux : Delay of status multiplexer tseq : Microsequencer delay trom : Control ROM delay treg : Register delay


10

Performance & Clock Period tclk ≥

max { tdp, tstatus + tsta_mux + tseq + trom + treg} Total Time (T) = tclk Χ nclk Pipelining can be used to decrease the clock period but may also result in increasing the number of clocks. Chapter 5: Microprogrammed Control

11

Microprogrammed Control Design: Example M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 5: Microprogrammed Control

12

2

Design Steps

Case Study: GCD Computer

• Design the datapart and identify the control and status signals • Design the microsequencer based on the branchings required • From the schedule of operations finalize the size of the control ROM • Finalize the microinstruction format • Generate the microprogram Chapter 5: Microprogrammed Control

13

GCD Algorithm

x

z GCD Computer

y

eoc

start


14

GCD Computer: Data Part

s: wait till (start=1); input x, y; eoc := 0; while ( x ≠ y ) do if ( x > y ) then x := x - y else y := y - x endif; endwhile; z := x; eoc := 1; go to s; Chapter end.5: Microprogrammed Control

Comp

15

GCD Computer: State Diagram

S1

S6 Chapter 5: Microprogrammed Control

S3 S5

R3

eoc

SUB


16

Control Flow Requirements • Next microinstruction • If (cond) then … else “m(i + 1)” cond = {start’, .eq.,.gt.} • Go to “m(0)”

S0

S2

R2

R1

S4 17


18

3

Microsequencer Specifications

Block Diagram

Microsequencer instructions

n Seq n

• Next (or continue) • Conditional jump • Unconditional Jump

19

Microinstruction Format

Data Part

k MUX

s


S

20

Symbolic Microprogram

• Data part control signals – sel_R1, sel_R2, sel_sub1, sel_seb2, ld_R1, ld_R2, ld_R3, clr_eoc, pr_eoc

• Control Part signals – seq._ins (2 bits), cond_sel(2 bits), Next_adr(3 bits)

• Status signals – start’, .eq., .gt. Chapter 5: Microprogrammed Control

m

G 1


Control w R E ROM

21

• M0: s_ins = cjmp, c_sel = start’, NA=0 • M1: s_R1=x, s_R2 = y, ld_R1, ld_R2, clr_eoc, s_ins = cont • M2: s_ins = cjmp, c_sel = .eq., NA= 6 • M3: s_ins = cjmp, c_sel = .gt., NA= 5 • M4: sub1= R1, sub2 = R2, ld_R1, s_ins= jp ,NA=2 • M5: sub1= R2, sub2 = R1, ld_R2, s_ins= jp, NA = 2 • M6: pr_eoc, ld_R3, s_ins = jp, NA = 0 Chapter 5: Microprogrammed Control

22

Microsequencer Design Steps The role of the microsequencer is to generate the next address. • Enumerate the microsequencer instructions that need to be supported • Identify all the inputs to the “Next Address” multiplexer • Synthesize the logic for the select input of the “Next Address” multiplexer

Microsequencer Design M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 5: Microprogrammed Control

23


24

4

Microsequencer Synthesis: Example

“NA” Mux Inputs

Microsequencer instructions to be supported Instruction • NEXT • CJMP • JMP

µ P C

+1 BA

Encoding 0 0 0 1 1 0

NA Mux

NA

Cond Sel Logic µseq_inst


25


Next Address Select Logic Microseq. Instr. I1 I0 0 0 0 1 0 1 1 0 1 1

Cond C X 0 1 X X

26

A Generic Microsequencer

NA_sel S 0 0 1 1 X

b

Stack

NA Mux

BA

Cond

µ P C

+1

Lp cntr

“0” Dec 0 Sel Logic

Cond_en µseq_inst


27

NEXT (or CONT) JPC JMP JZERO JSUB RET LD_CNTR RPNZ


Block Diagram

µ seq

29

OE 28


Microsequencer Instructions • • • • • • • •

NA

Control ROM


µ Ins reg

Data Part

30

5

Timing Diagram

Multi-way Branching

Clk

NA

a

µseq_instr µinstr

a+1

b

NEXT

JSUB b

MI[a]

MI[a+1]

• Multiple address fields • Address mapping through look up tables • Address mapping through address translation and encoding MI[b]


31

Multiple Address Fields j c3

Si c1 Si+1

c2 Sj

c3 Sk c2+c3

Sta. mux

32

Multi-way Branching

k 0 1 MUX BA

Microsequencer



33

IR

• Mapping ROM or Address encoding • JMAP instruction

Mapping ROM BA Micro sequencer


34

Optimization Types Microprogram Optimization M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 5: Microprogrammed Control

• Vertical optimization • Horizontal optimization

Control ROM mXn

35


36

6

Vertical Optimization

Horizontal Optimization • Reducing the width of microinstructions

• Rescheduling or reassignment of control signals to control steps/microinstructions • Merging of microinstructions • Timing isssues


37

Microinstruction Formats

• Encode multiple microoperations/control signals in the same field Chapter 5: Microprogrammed Control

38

Microinstruction Format (contd.)

• Horizontal format

• Vertical format

– Separate bits (/fields) for all control signals (/microoperations) – No loss of concurrency – Large width of microinstructions and low utilization


– Compromising on the available concurrency in the data/control part – Without compromising the concurrency available

– Only one microoperation (or register transfer operation) per microinstruction – Difinite loss of concurrency – Smallest possible width of microinstructions and very high utilization

39


Microinstruction Format (contd.)

40

Encoding Example

• Minimally encoded format – Multiple microoperations (or register transfer operation) per microinstruction – Concurrency may or may not be compromised – Architecture driven or application driven encoding


41

En_A

A

En_B

B

Ld_D

D

Ld_E

E


En_C

Ld_E

C

F

42

7

Horizontal Format

Vertical Format Transfer _ X _ Y

En_A

En_B

En_C

Ld_D

Ld_E

Ld_F

0000 0001 …… 1001 Chapter 5: Microprogrammed Control

43

Minimal Encoding

Bus_Src 00 01 10

Ld_D

Transfer_C_F


44

Minimal Encoding (contd.)

• Architecture Dependent Bus_Src

No Operation Transfer_A_D

• Application Dependent Ld_E

Ld_F

Bus_Src

Bus_Src 00 A 01 B 10 C

A B C


45

Bus_Dest

Bus_Dest 00 01 10 11


Noop D&E E F 46

Complex Microinstruction Encoding & Formats

Impact of Encoding • Cost – Reduction in the control ROM size – Additional decoders

• Multiple level encoding • Nanoprogramming

• Performance – Increase in the clock period if the decoders are in the critical path


47


48

8

Input-Output Specification Microinstruction Optimization M. Balakrishnan Dept. of Comp. Sci. & Engg. I.I.T. Delhi Chapter 5: Microprogrammed Control

49

Inputs:

A horizontal microinstruction format Symbolic microprogram

Output:

Microinstruction format


GCD Example

Symbolic Microprogram

s: wait till (start=1); input x, y; eoc := 0; while ( x ≠ y ) do if ( x > y ) then x := x - y else y := y - x endif; endwhile; z := x; eoc := 1; go to s; end.

1 2 3 4 5 6 7


51

Sta_s, Seq_i, BA R1_s, R1_ld, R2_s, R2_ld, eoc_c, Seq_i Sta_s, Seq_i, BA Sta_s, Seq_i, BA Sub1_s, Sub2_s, R1_s, R1_ld, Seq_I, BA Sub1_s, Sub2_s, R2_s, R2_ld, Seq_I, BA eoc_p, R3_ld, Seq_i, BA


Horizontal Format A= D= G= J=

Sta_s(2) R1_s R2_ld S2_s

B= E= H= K=

Seq_I (2) R1_ld eoc_c R3_ld

C= F= I= L=

52

Disjoint Graph BA(3) R2_s S1_s eoc_p

53

A

L

C

B D

K J

E I

Microinstruction word length = 16 Chapter 5: Microprogrammed Control

50

H

G


F

54

9

Reflecting Control Signal Properties

Microinstruction Formats

• Non-linear cost reduction due to encoding {A,B,C,D,E,F,G,H,I,J,K,L}

– Reflect in “cost” computation

16

{(A,D,L),B,(C,H),(E,K),F,G,I,J}

• Nature of control signals: default value is fixed or don’t care

13

– Mark the nodes and reflect in clustering

• Width of control signals – Multiple copies of the same node with bit number Chapter 5: Microprogrammed Control

55

A

C

B D

K J

E I

H

G

{A,B,C,D,E,F,G,H,I,J,K,L}

16

{(A,D,L),B,(C,H),(E,K),F,G,I,J}

13

{(A1,E),(A2,G),B1,B2,(C1,H),C2,C3, (I,L),(J,K)} 9

F


56

Additional Microinstruction Formats

Modified Disjoint Graph L


57


58

Microinstruction Optimization Steps

Column Compatibility • Based on the optimized format, generate the binary microprogram • Based on the compatibility between columns, draw the compatibility graph • Again apply clique partitioning to eliminate redundant columns

• Generate the symbolic microprogram • Design a horizontal microinstruction format • Optimize to generate the fields in the optimized format • Generate binary microprogram • Eliminate redundant columns • Design the decoders and fanout logic



59

60

10

Domains of Description : Gajski’s Y-Chart

VHDL models

M. Balakrishnan Dept of Computer Science & Engg. I.I.T. Delhi Chapter 6: Introduction to VHDL

Structural domain

Behavioral domain

Introduction to VHDL

1

Physical domain Chapter 6: Introduction to VHDL

VHDL Development

Level of abstraction 2

HDL Requirements

• US DoD initiated in 80’s • Very High Speed ASIC Description Language • Initial objective was modeling only and thus only a simulator was envisaged • Subsequently tools for VHDL synthesis were developed

• • • •

Chapter 6: Introduction to VHDL


3

Abstraction Modularity Concurrency Hierarchy

4

Abstraction

Modularity

VHDL supports description of components as well as systems at various levels of abstraction • Gate and component delays • Clock cycles • Abstract behavior without any notion of delays

• Every component in VHDL is referred to as an entity and has a clear interface • The interface is called an entity declaration • The “internals” of the component are referred to as the architecture declaration • There can be multiple architectures at even different levels of abstraction associated with the same entity



5

6

1

VHDL Example

VHDL Description: AND gate entity AND2 is port (a, b: in bit ; c : out bit); end AND2;

a AND

c

b

architecture beh of AND2 is begin c execution order)

(textual order => execution order)

(Signals) + (Component instances + Port maps)

• Many sophisticated features in VHDL to make it more versatile:

• Sequential statements • Control constructs alter normal sequential flow

• Concurrent statements • Data flow (or rather data dependency restricts concurrency)

Called Behavioral description in VHDL

Called Data flow description in VHDL

* Variety of signal types * Generic components * Generate statements for creating arrays of component instances * Flexibility in binding components to design entities and architectures


15

Concurrent Statements in VHDL • • • • • • •

process statement concurrent procedure call concurrent signal assign. component instantiation generate statement block statement concurrent assertion stmt


-- behavior -- behavior -- data flow -- structure -- structure -- nesting -- error check 17


16

Example: 1-bit Full Adder entity FullAdder is port (X, Y, Cin: in bit; -- Inputs Cout, Sum: out bit); -- Outputs end FullAdder; X Y Cin

Sum FullAdder


Cout 18

3

Example: 1-bit Full Adder (contd.)

Example: 4-bit Adder

Architecture Equations of FullAdder is begin -- Concurrent Assignment Sum

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