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November 2011 Vol. 54 No. 11: 2236–2246 doi: 10.1007/s11432-011-4446-x

Principles, structures, and implementation of reconfigurable ternary optical processors JIN Yi∗ , WANG HongJian, OUYANG Shan, ZHOU Yu, SHEN YunFu, PENG JunJie & LIU XueMin School of Computer Engineering and Science, Shanghai University, Shanghai 200072, China Received December 29, 2010; accepted June 20, 2011

Abstract This paper discusses the principles, structures, and implementation procedures for reconfiguring a ternary optical processor (TOP). Typical structures, classifications, and naming of the TOP and basic operation units (BOUs) are described in this paper. The circuit implementations, commands, and processes for the reconfiguration are also discussed in detail. A simple analysis of the high performance and low power consumption of ternary optical computers is presented. Finally, an experiment is performed on reconfiguring a 1-bit BOU, which shows that the principles of reconfigurable TOPs are valid, and that the implementations and commands for the reconfiguration are effective. Keywords ternary optical processors (TOPs), reconfigurable processors, decrease-radix design principle, basic operation units (BOUs) Citation Jin Y, Wang H J, Ouyang S, et al. Principles, structures, and implementation of reconfigurable ternary optical processors. Sci China Inf Sci, 2011, 54: 2236–2246, doi: 10.1007/s11432-011-4446-x

1

Introduction

In 2000, Jin et al. [1] proposed the concept of and structures for a ternary optical computer (TOC), in which information is represented using three optical states—two polarization directions of the light that are orthogonal to each other plus a third state denoting total darkness, and optical processors can be constructed using basic elements such as liquid crystal and polarizers. In 2007, the decrease-radix design principle was proposed by Yan et al. [2] during the construction of a 360-bit experimental TOC system. The decrease-radix design theory pushed research on TOCs into a practical stage, in which optical computers are both implementable and applicable. Based on this theory, Li et al. [3, 4] explored the implementation of vector matrix multiplication algorithms on TOCs; Teng et al. [5] proposed algorithms for implementing high-performance cellular automata and random number generators on TOCs; and Shen et al. [6] discussed novel methods for solving NP-hard problems. In 2010, in light of the difficulties in constructing a parallel through carry adder [7] and the advantages of avoiding carry propagation when using modified signed digit (MSD) addition, Jin et al. [8] implemented an MSD adder based on the decrease-radix design theory and proposed data editing and arithmetic pipelining techniques. All this technical progress calls for the invention of a ternary optical processor (TOP) that can handle a large ∗ Corresponding

author (email: [email protected])

c Science China Press and Springer-Verlag Berlin Heidelberg 2011

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number of bits and is able to be reconfigured automatically, and this is the reason that Shen et al. [9] initially attempted to automatically reconfigure TOCs. In their attempts, they proposed a reconfiguration plan; however, this plan does not support the realization of two basic operation units (BOUs) whose input optical states are total darkness, while the output is a light with a particular polarization direction. In addition, the word length of the reconfiguration command adopted in their plan is 12, thus exceeding 8 bits, which means that the reconfiguration process takes a relatively long time. To overcome these drawbacks, Jin proposed a totally new design of reconfiguration circuitry in early 2010, which was later implemented by Wang during December 2010 in a 1-bit experiment using a small-scale FPGA device. Wang’s experiment proved the viability and validity of the original design. This paper discusses the new reconfigurable TOC in detail, including this novel design for circuit reconfiguration.

2

A brief introduction to decrease-radix design theory

The main conclusion of the decrease-radix design theory is that, if the D-state is included as one of the n physical states (n > 1) for information representation, then each of the 2-input, n-valued logic operators without carry generation (referred to as an n-valued logic operator in the sequel), can be constructed from no more than n × (n − 1) singleton basic operation units (singleton BOUs) following a determinate procedure, with up to n × n × (n − 1) types of singleton BOUs. The total number of different 2-input n-valued logic operators is known to be n(n×n) . The D-state is defined to be the state, when superimposed with any other physical state λ, would still generate state λ as a result of the superimposition. A singleton BOU is an n-valued logic operator with the simplest structure and the following feature: Only one combination of its input values can produce a non D-state as the output, whereas all the remaining input combinations invariably produce the D-state. According to this feature, one can deduce that there are up to n × n × (n − 1) types of different singleton BOUs. When BOUs are ready, based on the decrease-radix design theory, any n-valued logic operator can be synthesized by means of the following steps: 1. Encode the most frequently encountered symbol in the operator’s truth table with the D-state; and encode each one of the remaining symbols in the table with one of the remaining (n − 1) physical states, in a one-to-one correspondence. 2. Derive the corresponding singleton BOU for each non-D state entry in the truth table. Thus, one can deduce that the number of singleton BOUs composing any n-valued logic operator is bounded from above by n × (n − 1). 3. Physically superimpose the output signals of the BOUs derived in step 2, using a superimposing device. The output signal from the superimposing device forms the result of the n-valued logic operator. When applying this theory to TOCs, the state of total darkness is represented by the D-state; the total number of 2-input ternary logic operators is up to 39 ; the number of singleton BOUs is 18; the total number of singleton BOUs comprising any ternary logic operator does not exceed 6; and the superimposing device adopted is a beamsplitting mirror. In the case that the TOPs are implemented using liquid crystal, the two (or three) singleton BOUs whose outputs, as well as one of the inputs, denote the same state of light can be combined together to form what we call a compound basic operation unit (compound BOU) and implemented using only one liquid crystal pixel. Utilizing compound BOUs can greatly reduce the number of BOUs (both singleton and compound ones) constituting most of the ternary logic operators. Yan [10] studied the type and number of compound BOUs, as well as combination rules and methods. Wang X. C. and Wang H. J. conducted further detailed studies on this topic, and derived 18 compound BOUs composed of two singleton BOUs, and six compound BOUs composed of three singleton BOUs. Thus, there are 42 BOUs in total, including both singleton and compound ones, for building a TOC.

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Figure 1

3 3.1


Abstract structure of a BOU.

Structures and types of BOUs for building TOPs Structures of the basic operation units

In a TOP constructed using original-non-rotating liquid crystal and polarizers, the 42 basic operation units have the same abstract structure, which is shown in Figure 1. In this figure, transmission paths of the optical (electrical) signals are denoted by real (dashed) lines, while the components or transmission paths not belonging to the BOU itself are denoted by dotted lines. In this figure, the input signal to the main optical path is light beam a, which is generated by the main optical path’s encoder. The optical devices in the main optical path involve two polarizers (P1 and P2) with a liquid crystal (LC) in between, thus forming a sandwich-like structure. The input signal to the control optical path is light beam b generated by the control optical path’s encoder. In the control path, optical beam b propagates through polarizer P3 followed by phototube g. The phase of the electronic signal generated by g is automatically adjusted by the XOR gate (Y2) consisting of two tri-state gates (Y21 and Y22), and is used to control the optical rotation of LC. The other two XOR gates (Y1 and Y0 consisting of Y11 and Y12, and Y01 and Y02, respectively) are used to automatically control the phases of the input signals to the main optical path. The three controlling signals for the three XOR gates (K2, K1, and K0) come from the registers storing reconfiguration instructions, and are used to determine whether an input to an XOR gate is inverted or not. The three XOR gates have the same function: when Ki=1 (high level) with i=0, 1, 2, the input phase of Yi is inverted; otherwise when Ki=0 (low level), the phase of Yi’s output is the same as that of the input. As a result, K2 controls whether the output from g is automatically inverted. When K2=1, Y2 and LC form the original-rotating function of an LC. When K2=0, Y2 and LC form the original-non-rotating function. Therefore, K2 is called the “function code” for the LC. K1 and K0 are used to control whether the state of total darkness generated by the main path’s encoder should be changed into a light state with a particular polarization direction. In this way, an operation unit can be implemented that has no input light, but produces an output light beam. When K1K0=11, the light state of the total darkness generated by the encoder is automatically changed into a light state with horizontal polarization direction (W to H); when K1K0=01, the light state of the total darkness is changed into a vertical direction (W to V). Therefore, K1 and K0 are referred to as the “conversion code”. When light-controlled liquid crystals are applied to the design, phototube g is no longer needed in the control path, and Y2 should be implemented with an optical XOR gate instead. However, there exists neither light-controlled LCs nor optical XOR gates in the market. Meanwhile, the current main research subjects for TOCs focus on the underlying SW/HW frameworks and their potential application fields. As a result, electronic-controlled LCs, which are mature technology, are still used in the 1000-bit experimental system discussed in this paper. In this case, phototube g is used to change the control path’s

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input optical signal b into an electronic signal controlling the LC’s light rotation, and Y2 is implemented using a conventional electronic XOR gate. 3.2

Classification and naming of the basic operation units

According to the abstract BOU structure shown in Figure 1, the distinctions between any two BOUs are that the values of the controlling signal Ki (i=0,1,2) are different, and/or that the polarization directions of the three polarizers, P1, P2, and P3, are different. Note that P3 is absent in a BOU where both the horizontally and vertically polarized lights have the same effect in controlling the LC’s light rotation. In addition, P3 is opaque in a BOU whose control path is not needed. The main optical path in a BOU is classified into the following four types, according to the polarization directions of P1 and P2: Both P1 and P2 are vertically polarized (the corresponding main path is designated as the VV type); P1 is vertically polarized and P2 is horizontally polarized (the VH type); P1 is horizontally polarized and P2 is vertically polarized (the HV type); both P1 and P2 are horizontally polarized (the HH type). The control optical path can also be classified into the following four types, according to the polarization direction of P3: V-type if P3 is vertically polarized; H-type if P3 is horizontally polarized; D-type if P3 is transparent to both vertically and horizontally polarized lights; and N-type if P3 is opaque. Therefore, a basic operation unit can be identified and distinguished using an identifier series in terms of “main path type-control path type-K2-K1K0”. For example, VHD100 refers to an operation unit with VH type for its main path, D type for its control path, K2=1, K1=0, and K0=0. In this BOU, P1 is vertically polarized, P2 is horizontally polarized, P3 is transparent to both vertically and horizontally polarized lights, Y2 and LC form the original-rotating functionality, and the light state of the total darkness generated by the main path’s encoder is not converted to other light states. The identity series of other BOUs can be derived in a similar way following this naming convention. 3.3

Concentrated layout of BOUs and pixel bits

During the practical design of TOPs, main optical paths of the same type are always laid out in a particular area on the LC arrays in a concentrated way, and the control paths of the same type are laid out within one section of the polarizer. Thus, the LCs in the main path of a TOP are divided into four zones, VV, VH, HV, and HH, while the polarizers and phototubes in the control path are divided into zones V and H. Zones D and N are not required to be laid out explicitly for the control path, because the D-type control path can be implemented by performing the OR logic operation on the outputs from Vand H-typed ones, whereas the N-type control path can be implemented by turning off both the V- and H-typed paths. As a result, the optical components in a TOP are divided into six zones. For convenience of management, pixels at the same physical positions on the six zones are coordinated to form a particular operation unit. To this end, an (x, y) coordinate system has been developed to locate the pixels in the LCs, where the upper left point is the (0,0) origin. The six pixels at the same positions on the six zones are referred to as a pixel bit. Each pixel bit in a TOC includes four zones belonging to the main optical path, and as a result, at most four different BOUs can be constructed from each pixel bit. For a ternary logic operator that is composed of less than five basic operation units, each pixel bit corresponds to a data bit of the logic operator. However, if 5 or 6 BOUs are required to construct a logic operator, two pixel bits correspond to a data bit of the operator. This difference in the number of pixel bits corresponding to a data bit should be handled with special care in a monitor routine.

4

Structures and principles of the reconfiguration circuits

The core operation for reconfiguring a BOU is to set up its control optical path for the main optical path. According to the design idea of “light path for handling data computation, and electronic path

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Figure 2

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A BOU and its reconfiguration circuit.

for control”, we have adopted the circuitry demonstrated in Figure 2 for reconfiguring a BOU where the control optical path is set up automatically. As in Figure 1, light beams a and b are the two input optical signals, and c is the output optical signal. In Figure 2, light a is divided into four beams, which are simultaneously sent to the sub main optical paths, namely, its HH, HV, VH, and VV zones. Light b is divided into two beams, which are sent simultaneously to its V and H typed sub control paths. Output c is the physical superimposition of the output optical states from the four sub main optical paths using beamsplitting mirrors d1, d2, and d3. The optical devices P1 and P2 in Figure 1 are now in their concrete forms of vertical (V) or horizontal (H) polarizers, and thus the LCs have four zones. Similarly, the polarizer P3 in Figure 1 is implemented using vertical or horizontal polarizers, and phototube g is implemented using gh and gv. As a result, the sub control optical paths V and H are set up. The outputs of gh and gv are inputs to the OR gate Y3, whose output is the sub control path D. The three XOR gates (Y2, Y1, and Y0) for each sub main optical path have the same functions and controlling signals as those in Figure 1. The key components added in Figure 2 are the four reconfiguration circuits shown in the dashed boxes. The function of the reconfiguration circuit is to set up the appropriate control optical path for a sub main optical path and thus to construct a particular BOU. The four circuits share the same structure, as specified by that for the VV-typed sub main optical path. Each circuit consists of three tri-state gates (c0, c1, and c2) and a resistor (r) that is connected to ground. c0, c1 and c2 are controlled by signals K3, K4 and K5, respectively. When K3=1, K4=K5=0, only c0 is conducting and therefore, the D-type control optical path is selected to control the LC pixel in the sub main optical path. When K4=1, K3=K5=0, only c1 is conducting and thus the H-type control path is selected. When K5=1, K3=K4=0, only c2 is conducting and the V-type control path is selected. Finally, when K3=K4=K5=0, the N-type control path is selected. In this way, the selection of a control optical path is converted into a problem of assigning appropriate code values to K3, K4 and K5, which are referred to as “controlling code”. It is obvious that at most one “1” value exists in a valid controlling code. When a sub main optical path is not in use, i.e., its output remains in the state of total darkness no matter what values inputs a and b take, the sub-path is closed. In this case, the N-type control optical path is selected, and K2 should take the value of 1 (0) for the HH and VV (VH and HV) typed sub main optical paths. Therefore, the controlling signals (K5, K4, K3, and K2) to close a sub main optical path are “0001” for HH and VV typed paths, and “0000” for HV and VH typed paths. These value combinations are therefore referred to as “closing codes”. In addition, any code value of (K3, K4, K5) that has more than one non-zero value is not allowed and is thus called a “forbidden code”. This is to avoid the possibility of a short-circuit as the outputs of c0, c1, and c2 are wired together. After the appropriate values have been assigned to the six control signals K0–K5, the LC pixel in a sub main optical path as well as its control path form a particular BOU, and thus that operation unit

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Figure 3


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Circuit structure for superimposition function.

is reconfigured. To ensure that the operation unit is stable, these signals must be latched in a register. There are four such registers in Figure 2: Rhh, Rhv, Rvh, and Rvv, which store the controlling signals for HH, HV, VH and VV typed sub main optical paths, respectively.

5 5.1

Reconfigurable ternary optical processors Operations for the reconfiguration

Two reconfigurations are required to construct a TOP from its abstract structure shown in Figure 1: The first one is called “BOU reconfiguration”, by which a concrete basic operation unit is constructed from its abstract model. The second one is called “processor (or logic operator) reconfiguration” by which a particular TOP is implemented by combining the different BOUs. BOU reconfiguration involves assigning the appropriate values to the registers Rhh, Rhv, Rvh, and Rvv. Processor reconfiguration, however, requires the operations of first selecting the BOUs for constructing the processor, and then physically superimposing the outputs from these units. A simple regulation exists to determine the locations of the BOUs used to constitute one data bit of a processor: A data bit of the processor can only be built using the BOUs implemented on the same pixel bit or alternatively, the BOUs on two contiguous pixel bits, whereas the BOUs on one pixel bit form at most one data bit of the processor (the sub main optical path is closed if not in use). Difficulties arise in the use of beamsplitting mirrors for superimposition of the light outputs from the basic operation units (Figure 2). First of all, beamsplitting mirrors pose a problem in reducing the size of a processor because of their relatively large dimensions and the exact requirement in placing them (at a 45◦ angle to the light’s propagation direction). Secondly, very high standards of mechanical manufacture and calibration are required to align all the pixels in the four modules of the main optical path, which are not easily reached at the current stage. Considering that the response speed of the LCs should not exceed that of the electronic circuits in the foreseeable future, we temporarily resort to electronic circuits to implement the superimposition function in this paper, the structure of which is illustrated in Figure 3. In Figure 3, an output from an LC module in one of the four sub main optical paths belonging to a particular pixel bit is detected using a phototube. The outputs from phototubes ghh and gvh, corresponding to the HH and VH typed modules, are inputs to the XOR gate Y h; similarly, the outputs from phototubes ghv and gvv, corresponding to the HV and VV modules, are inputs to Y v. Outputs ch and cv, from Y h and Y v respectively, are the results of this circuit, which encode horizontal and vertical polarization directions of light c in Figure 2. From this perspective, reconfiguring a TOP amounts to assigning the appropriate values to the four registers Rhh, Rhv, Rvh, and Rvv. 5.2

Commands for BOU reconfiguration

As discussed in the previous section, the reconfiguration of a basic operation unit is carried out by assigning the appropriate values to one of the four 6-bit registers in Figure 2, namely Rhh, Rhv, Rvh, and Rvv. In addition, the 2–4 decoder in Figure 4 is adopted to address the registers, where bits d7 and d6 form the “addressing code”. In particular, register Rhh is selected when d7d6=00; Rhv is selected when d7d6=01; Rvh is selected when d7d6=10; and Rvv is selected when d7d6=11.

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Figure 4

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Registers for reconfiguration commands.

The byte comprising d7 to d0, referred to as the command for the BOU reconfiguration, includes the following four fragments of codes: addressing code (d7 and d6), controlling code (d5, d4, and d3), function code (d2), and input conversion code (d1 and d0). For example, R = 10 100 0 00 = 0a0h is the command to reconfigure a BOU that produces a horizontally polarized light when inputs a and b are both in the vertical polarization direction, and an output state of total darkness for other combinations of input values. With this command, the VH zone of the LC arrays is selected according to the addressing code; V-typed control optical path is set up by the controlling code; an original-non-rotating type of LC pixel is defined by the function code; and the input signals to the main optical paths will not be converted according to the input conversion code. If a CPU belonging to the 8086 series is used to execute the task of BOU reconfiguration, this command can be expressed using the following assembly language code: mov al, 0a0h out Adr, al where the highest two bits of the command ensure that the remaining 6 bits are stored in register Rvh to construct the target BOU at the pixel bit with address Adr. Adr is the address of the reconfiguration register for the pixel bit where the target BOU is to be constructed. It is obvious that a unique reconfiguration command exists for each BOU type; and therefore, a reconfiguration command for a basic operation unit can be used to identify that unit. 5.3

Processes for logic operator reconfiguration

Reconfiguration of a logic operator refers to the process of constructing the specified BOUs at a particular pixel bit, which in turn amounts to sending the reconfiguration command into the corresponding registers of that pixel bit. For this end, an 8-bit reconfiguration command register R(n) is allocated to each pixel bit of a TOP, as shown in Figure 4, where n is the relative address of the register as well as the index for the pixel bit, and R(n) contains the reconfiguration command. For example, the 8086 type instruction series for reconfiguring a logic operator composed of BOUs with identifiers (i.e., their reconfiguration commands) 0a0h and 10h, at the pixel bit with index number 76h is mov al, 0a0h out 76h, al; the least significant 6 bits of “0a0h” are loaded into register Rvh at pixel bit 76H mov al, 10h out 76h, al; the least significant 6 bits of “10h” are loaded into register Rhh at pixel bit 76H

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Furthermore, the program to construct the logic operator in the last example at each of the 48 pixel bits from address 50h to 80h is mov cx, 30h mov bx, 50h call YSQ10a0 ... YSQ10a0: mov al, 0a0h out [bx], al mov al, 10h out [bx], al inc bx loop YSQ10a0 ret In this program, the operator is labeled as “YSQ10a0”, where YSQ is the acronym for Chinese Pinyin of “operator”, while 10 and a0 (in the hexadecimal number system) are the identifiers of the BOUs comprising the logic operator, which are listed in increasing order. This label directly reflects the structure of a logic operator, and can be used as its name since each label uniquely corresponds to a logic operator. Following this convention, the longest label for a logic operator includes 6 BOU identifiers and contains 15 characters. To construct an M -bit logic operator beginning from the N th pixel bit of a TOP, all we need to do is to assign N to bx, M to cx, and call the corresponding label of the operator. Programs to construct this type of (M -bit) logic operator are called reconfiguration routines. When different reconfiguration routines are applied to different pixel bits of a TOP, these bits are constructed into different logic operators, and the TOP therefore becomes a compound logic operator. 5.4

High performance analysis of TOPs

The reconfiguration process of a TOP is accomplished by an embedded system; therefore, the holding time of the process is dependent on the slower of the embedded system’s frequency and the LC’s response speed. Note however that during the reconfiguration process of a TOP, no data is being computed. After the reconfiguration task finishes, the embedded system no longer controls the TOP, and a logic operator begins its data computation by producing the output c based on the input (a and b) values once its corresponding registers (Rvv, Rvh, Rhv, and Rhh) are correctly set up. As a result, the computation delay of a logic operator using optics is the time for light beam a to propagate through the optical devices in the main optical path, i.e., two polarizers and one LC pixel, under the control of light beam b. In most of the processors, the state of the LCs in the main optical path changes according to the signals from the control path, and thus the computation speed of the system depends on how fast the LC changes its state (i.e., the LC’s response frequency). Since current research on LCs is still focused on high quality monitors where MHz response frequency would suffice, the demand for LCs with higher frequency is lacking and as a result, formulas for LCs with a response frequency reaching an order of GHz have not yet been found. However, there exists a large development space for high response frequency LCs because the response frequency of an LC depends mainly on the degree of viscosity and cohesion among the molecules, both of which can be greatly affected by mixing different formulas. It is obvious that the increase in a TOC’s computation speed is proportional to that of the LC’s response frequency. On the other hand, one should not forget that the computation delay of a TOP is independent of the LC’s response frequency in a class of computations (e.g., inversion and comparison) where the LC state in the main optical path is maintained. The delay of this type of computation is the time (t) for light beam a to traverse two polarizers (P1 and P2) and one LC pixel held between the polarizers. Since t equals the distance of the main optical path divided by the light speed, t is directly proportional to the thickness of the polarizers and the LC arrays, as well as their refraction indexes. In the current TOC experiment system, the total sum of thickness of the polarizers and LC array in the main path is about 2 mm, and t

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Figure 5


A 1-bit TOP experimental system.

is therefore smaller than 1.14 × 10−11 s [7]. As a result, this type of operation has a computing frequency of up to 100 GHz. The frequency can be further improved by diminishing the refraction index and/or the thickness of the main optical path in a TOC. For example, if 0.2 mm thick LC arrays are applied to the main path, the computation frequency can reach 103 GHz. Note that for this type of operation, the key to improving the speed relies on finding high-speed encoders for polarized light and phototubes. The most promising encoder that can be applied is the Quantum Well Vertical-cavity Surface-emitting Laser, with a response frequency of up to 10 GHz [11], whereas the response frequency of a phototube reaches 25 GHz [12]. However, there is still plenty of time for them to catch up with the computing speed of a TOC. 5.5

Low power analysis of TOPs

As is well known, the change in molecular orientation of an LC is due to electrical field force. Liquid crystal itself has high resistance to electricity and as a result its power consumption is very low. The power consumption of a 1000-bit 100 GHz TOP is predicted to be less than 10 watts, whereas that of the LED light source and electronic controlling devices is about 500 watts. However, its computing capacity in terms of bit-main frequency product can reach as high as 1014 , which is 1000 times higher than that of a current mainstream PC. Therefore, it is reasonable to predict that the application of TOPs in large scale systems will greatly reduce their power consumption.

6

Experiments for the reconfiguration

To verify the functionality of the reconfiguration circuit and improve its structure, detailed experimental research has been carried out on all types of BOUs and those logic operators that are composed of no more than 4 BOUs. Operators with more than 4 BOUs are not fundamentally different in their hardware reconfiguration structure and the method for controlling them, but pose some difficulty in the design of the software for pixel bit assignment as two pixel bits are required to implement one data bit of a logic operator. In addition, the LC arrays used in the main optical path of our experiment are not suitable for constructing a logic operator out of two pixel bits. As a result, experiments in this paper include only BOUs and logic operators using one pixel bit. 6.1

Setting up the experimental devices

The experimental devices include a DICE-SEM II digital-analog experimental box and a self-made TOP with one pixel bit, as demonstrated in Figure 5. The circuits in Figures 2–4 are implemented using the

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programmable logic circuits in the experimental box (ACEX1K). The switches K1–K8 at the bottom of the box are used to set up a reconfiguration instruction on the data bus (d7–d0, the inputs to R(n) in Figure 4). K9 (CLK1) is for addressing R(n), i.e., the enable signal IE in Figure 4. K10 and K11 are the input signals to the encoder of the main optical path (i.e., a2 and a1), while K13 and K14 are the inputs to the encoder of the control optical path (i.e., bh and bv). K12 (CLK2) is the output enable signal for the two encoders for the main and control paths. The computation result is shown in the three digital number tubes in the middle of the box’s top area, where LED4 displays 1 if the computation result is the optical state of total darkness (W), LED5 displays 1 if the result is vertically polarized light (V), and LED6 displays 1 if the result is horizontally polarized light (H). The main optical path and its encoder in this experiment are constructed using three pieces of TNtyped liquid crystal (stroke segment styled) and four layers of polarizer. The control optical path and its encoder are constructed using the two red luminotrons at the bottom corner of the box and two phototubes on top of the luminotrons. Six TSL14s high-speed light density sensors are used to sample the output optical signals from the control and main paths. Other LEDs for the digital number tubes and luminotrons in the experimental box are used for run-time state monitoring. 6.2

Experimental procedure

The reconfiguration experiment was performed according to the following four steps: 1. Carefully arrange the experimental devices so that the complete panel of the experimental box, the main optical path, a page showing the BOU under examination, a page showing the operation state, and a hand signal marking the experiment results (thumb up for success and down for failure) can be captured in one photograph. 2. Set up a particular operation unit in one of the four zones of the main optical path, or alternatively close to the zone. 3. Observe the output optical state c for each input (light a and b) state combination. Record the result, signal it by hand, and capture the experimental result in a picture. 4. Repeat steps 2 and 3 until all the selected 22 logic operators, comprising all the 42 BOUs and covering the major cases of their combinations, have been examined. 6.3

Experimental results

All the 22 logic operators were tested for all the possible nine input combinations, and 198 photos were taken to record the experimental results. All the results comply with their theoretical prediction, which proves the correctness of the TOP reconfiguration theory and the effectiveness of the reconfiguration structures. Figure 5 shows the results of a simple experiment. The upper left page shows that the logic operator being examined is number 23, whose corresponding main path has only the HH zone set up as BOU number 23 and all the other three zones closed. To the right of this page is another page listing the nine experimental steps corresponding to all the possible input combinations. In particular, this photo illustrates the experiment results of step 4, where a=W and b=H. The correct output state for this input combination should be H, which is verified by the experimental results: Only the HH zone of the main optical path has a light dot on it, and at the same time, the LEDs on the experimental box demonstrate the correct encoding for the computation results (i.e., H=1, W=0, and V=0).

7

Conclusions

In this paper, we introduced one type of structure for a reconfigurable ternary optical processor and discussed it in detail, as well as the corresponding reconfiguration commands and processes. With these reconfiguration methods, a TOC can be successfully reconfigured into a concrete ternary logic operator according to a user’s request. In addition, a compound logic operator that comprises various logic operations can be constructed. The system described in this paper is a thorough and practical application

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of the decrease-radix design theory, while the reconfiguration methods discussed in this paper present a complete theoretical basis, as well as a technical enabler, for implementing ternary optical processors.

Acknowledgements This work was supported by the National Natural Science Foundation of China (Grant No. 61073049), the Shanghai Leading Academic Discipline Project (Grant No. J50103), and the Doctorate Foundation of Ministry of Education of China (Grant No. 20093108110016).

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