Priority Sorting Approach for Modular Multilevel Converter Based on

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 6, JUNE 2018

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Priority Sorting Approach for Modular Multilevel Converter Based on Simplified Model Predictive Control Jingjing Huang

, Bo Yang, Fanghong Guo , Member, IEEE, Zaifu Wang , Xiangqian Tong Aimin Zhang, Member, IEEE, and Jianfang Xiao, Member, IEEE

Abstract—In this paper, a priority sorting approach based on simplified model predictive control (MPC) is proposed for modular multilevel converter (MMC). It aims at reducing the computational burden of conventional MPC method while maintaining the system performance, especially under high voltage levels. The proposed approach mainly consists of three parts, i.e., grid-side current control (GCC), circulating current control (CCC), and capacitor voltage balancing control (CVBC). The GCC and CCC are separately designed with simplified MPCs, avoiding the weight factor. Meanwhile, the redundant calculations are eliminated in GCC by considering the desired predicted output voltage of equivalent MMC model. To further minimize the optional combinations of the switching states, the CCC is constructed by utilizing the output of GCC and the arm current. Besides, a novel priority sorting approach is proposed for the CVBC to alleviate the sorting operation. The submodules are divided into three groups according to the detected capacitor voltages. Moreover, the groups are assigned with different priorities based on the arm current, and only one group needs the sorting process. Additionally, a reduced frequency approach is introduced to decrease the power loss in the steady state. The effectiveness of the proposed approach is validated by both simulation and experimental results. Index Terms—Circulating current, model predictive control (MPC), modular multilevel converter (MMC), voltage balancing control, weight factor.

Manuscript received May 3, 2017; revised September 5, 2017 and October 2, 2017; accepted October 28, 2017. Date of publication November 16, 2017; date of current version February 13, 2018. This work was supported in part by the National Natural Science Foundation of China under Grant 51507138, in part by the Young Talent fund of University Association for Science and Technology in Shaanxi, China, under Grant 20160117, and in part by the China Scholarship Council (CSC). (Corresponding author: Aimin Zhang.) J. Huang, B. Yang, and X. Tong are with the Department of Electrical Engineering, Xi’an University of Technology, Xi’an 710048, China (e-mail: [email protected]; [email protected]; [email protected]). F. Guo is with the Experimental Power Grid Center, Agency for Science, Technology and Research, Singapore 627590 (e-mail: guo_ [email protected]). Z. Wang and A. Zhang are with the School of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an 710049, China (e-mail: [email protected]; [email protected]). J. Xiao is with the Energy Research Institute, Nanyang Technological University, Singapore 639798 (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2017.2774725

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I. INTRODUCTION HE modular multilevel converter (MMC) consists of several half- or full-bridge submodules (SMs) connected in series, generating numerous voltage levels [1], [2]. With the modular structure, it exhibits the merits of low switching frequency, bidirectional power flow, scalability, and high quality of the output voltage [3], [4]. These advantages make MMC especially well suitable for medium- and high-voltage applications, such as the high voltage direct current system (HVdc) [5], [6], reactive power compensator [7], and renewable energy system [8]. Generally speaking, in MMC systems, the grid-side current should be well regulated to its desired value, as it directly affects system’s steady-state accuracy and transient performance [9]. Besides, the circulating current and the unbalanced voltages among the submodule (SM), capacitors are also the challenges for MMC [10]. Therefore, there are three main control tasks for MMC: grid-side current control (GCC), circulating current control (CCC), and capacitor voltage balancing control (CVBC). The GCC is analyzed and developed most often based on the linear system theory, where proportional–integral (PI) or proportional-resonant (PR) controllers are usually utilized [11], [12]. In fact, MMC system is highly nonlinear and has a wide range of operational points. Therefore, it is quite difficult to guarantee its transient performance by applying PI or PR controllers. As a nonlinear approach, model predictive control (MPC) gains increasing attention in MMC applications due to its reserved nonlinearity property and flexible control objectives [13]–[15]. In MPC approaches, the best switching states are chosen by optimizing the predefined cost function. However, due to multiple objectives, such cost function may consist of several weight factors [14], which are technically hard to be tuned on-line. Besides, it makes the system implementation quite computationally costly. For example, in [15], the number of the considered N , where N indicates the SM number of each arm. statuses is C2N Obviously, its computational complexity will increase with the voltage level of MMC. In order to overcome this disadvantage, a finite control set MPC is analyzed and utilized in [16] and [17]. However, it is applied to the induction motor drive control rather than MMC. Therefore, the first motivation of this paper is to remove the weight factors and reduce the number of considered statuses.

T

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In MMC system, circulating current usually exists due to the parameter mismatch, switching transients, and unbalanced capacitor voltage of the SMs [18]–[22]. It increases the branch currents and consequently produces additional conduction loss to the system [18]. In order to suppress the circulating current, several methods have been proposed [19]–[21]. In [19], the accurate impedance angle of the converter leg is estimated to attenuate the circulating current. But it is technically difficult to be implemented. In [20], two PI controllers are employed to minimize the inner circulating current. However, this approach is designed based on the twice fundamental-frequency (2 ω), where the multiple coordinate transformations and decoupling techniques are needed. It is reported that MPC has also been applied in CCC to facilitate the implementation and reduce the system loss [22]. However, it also suffers from high computational cost, which motivates us to propose a simplified MPC in this paper. Apart from grid-side current regulation and circuiting currents suppression, capacitor voltage balancing in each SM is also a vital factor for the reliable operation of MMC [23]. Conventionally, some balancing methods based on the sorting technique are quite popular. However, in these sorting approaches [24], for each phase, the total number of switching states is N , which is acceptable if the number of SMs is small. In orC2N der to reduce the sorting burden, a grouping-sorting-optimized method is proposed in [25]. The SMs of each arm are evenly divided into several groups. However, the specific charging and discharging statuses of the capacitor voltage are not taken into account, resulting in certain needless sorting processes. Considering the aforementioned discussions, in this paper, a priority sorting approach based on simplified MPC is proposed for MMC. The ultimate goal is to regulate the grid-side current, suppress the circulating current, and balance the capacitor voltage with less computational cost. More specifically, compared to conventional MPC methods, in our proposed method, the GCC and CCC are designed individually without the weight factors. Moreover, the CVBC is built based on a priority sorting approach and a reduced frequency approach. In summary, the main contributions of this paper are threefold. 1) Different from conventional MPC approaches, the desired output voltage of the equivalent MMC circuit are introduced to obtain the approximate on-state SM number of each arm. Thus, a cost function of GCC is defined only with three considered statuses, regardless of voltage levels. This dramatically eliminates some redundant calculations. 2) Combining the circulating current error, the number of considered statuses in the designed CCC is reduced to minimum. Moreover, a method involving four additional candidates is introduced to further suppress the circulating current, which is suitable for some specific applications. 3) A priority sorting approach is designed for the proposed CVBC to operate during the transient-states. It divides the SMs into three groups and assigns them with the different priorities. Thus, only one group needs the sorting operation, which avoids some unnecessary computations.

The remainder of this paper is organized as follows. In Section II, the MMC model is presented. An MPC-based strategy involving GCC, CCC, and CVBC is designed and analyzed in Section III. Sections IV and V present the simulation and experimental results, respectively, to validate our method. This paper is concluded in Section VI. II. SYSTEM DESCRIPTION AND MMC MODELING Fig. 1 shows a three-phase MMC and its single-phase equivalent circuit. The dynamical model is given by [15] as di j − 2Ri j , j = a, b, c dt di cir j = vdc − 2L a , j = a, b, c dt

u n j − u pj = 2u s j − 2L

(1)

u n j + u pj

(2)

where u pj and u n j ( j = a, b, c) represent the upper- and lowerarm voltages of phase-j, respectively, u s j and i j ( j = a, b, c) indicate the grid-side voltage and current, respectively, i cir j ( j = a, b, c) is the circulating current, vdc is the dc-side voltage, R and L denote the equivalent resistance and inductance of the total inductor and transmission line, respectively. The inductance L can be obtained as L = L s + 12 L a , where L a and L s represent the arm and grid-side inductance, respectively. According to Fig. 1, the output voltage u cj ( j = a, b, c) in the equivalent circuit is u cj =

u n j − u pj , 2

j = a, b, c.

(3)

From (1) and (2), it can be concluded that the grid-side current i j is related to the difference between the lower-arm voltage u n j and upper-arm voltage u pj , while the total capacitor voltages of the upper- and lower-arms influence the circulating current i cir j ( j = a, b, c). In traditional MPC methods, the optimal switching states N combinations. However, the extensive are selected from C2N predicted statuses and resultant computational cost make it impractical under the high voltage levels. Thus, in the following section, a priority sorting approach based on simplified MPC is proposed to facilitate the implementation and reduce the computational burden. III. PROPOSED MPC-BASED STRATEGY Motivated by MPC and capacitor voltage balancing approaches in [22] and [25], a priority sorting approach based on simplified MPC is proposed for MMC in this paper. Its control diagram is shown in Fig. 2. The outer control loop adopted from [15] is designed to obtain the desired grid-side current. Besides, three main control blocks are designed including GCC, CCC, and CVBC. The relationship among these three parts is summarized as follows. 1) Utilizing the desired grid-side current i ∗j (t + Ts ) obtained from the outer control loop and the measured grid-side voltage and current, an individual cost function is developed for GCC to determine the on-state SM number of each arm n pj and n n j ( j = a, b, c).

HUANG et al.: PRIORITY SORTING APPROACH FOR MODULAR MULTILEVEL CONVERTER BASED ON SIMPLIFIED MPC

Fig. 1.

Three-phase MMC and its single-phase equivalent circuit.

Fig. 2.

Proposed control diagram for MMC.

2) Combining the output of GCC and the status of the circulating current, the CCC updates n pj and n n j ( j = a, b, c) by considering the tradeoff between suppressing the circulating current and deteriorating the grid-side current. 3) In the designed CVBC, a preset criterion is employed to achieve the corresponding objective. When the capacitor voltage error (CVE) is large, a priority sorting approach is proposed to balance the voltages of SMs. When the error is relatively small, a reduced frequency approach is employed to alleviate the system loss. The detailed design is presented subsequently. A. Grid-Side Current Control In conventional MPC approaches, more than N + 1 statuses are considered in GCC [15], [25], which involve some needless calculations. In order to overcome this disadvantage, in this section, a simplified GCC is proposed and its design procedure is elaborated in the following steps. Step 1) Obtain the desired predicted output voltage u ∗cj (t + Ts )

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Combining (1) with (3), the mathematical equation governing the dynamic behavior of the grid-side current is described by L

di j = −Ri j + (u s j − u cj ), dt

j = a, b, c.

(4)

By using the Euler approximation, (4) is rewritten as i j (t + Ts )

  L 1 u s j (t + Ts )−u cj (t + Ts )+ i j (t) = L/Ts +R Ts

(5)

where Ts is the sampling period, u s j (t + Ts ) is the predicted grid-side voltage, which can be directly obtained by u s j (t), and u cj (t + Ts ) can be calculated as u cj (t + Ts ) =

1 [u n j (t + Ts ) − u pj (t + Ts )], 2

j = a, b, c.

(6)

Depending on the output of the outer control loop, the desired grid-side current in the next sampling period can be obtained as i ∗j (t + Ts ) ( j = a, b, c). According to (5), we can get the desired

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 6, JUNE 2018

predicted output voltage u ∗cj (t + Ts ) ( j = a, b, c) as u ∗cj (t + Ts ) = u s j (t + Ts )   L L + R i ∗j (t + Ts ) + i j (t). − Ts Ts

(7)

Step 2) Approximate the total on-state SM number of each arm The total number of on-state SMs per phase should be N in our system [22], hence, u pj (t + Ts ) and u n j (t + Ts ) ( j = a, b, c) can be expressed as  u pj (t + Ts ) = u av j k1 , k1 = N , N − 1, ....., 1, 0 (8) u n j (t + Ts ) = u av j k2 , k2 = N − k1 where u av j is the average capacitor voltage of SM capacitor in phase j ( j = a, b, c), k1 and k2 indicate the total on-state SM number of the upper- and lower-arm in phase-j, respectively. According to (6)–(8), we have  2u ∗ (t+Ts ) k2 − k1 = cju av j =  . (9) k2 + k1 = N The upper- and lower-arm voltage levels are always integers, hence, k1 and k2 in (9) can be approximated as  ) k1 = round( N − 2 (10) k2 = N − k1 where round(·) is a rounding function, which outputs the integer part of any real number, e.g., round (3.4) = 3. Step 3) GCC design To obtain the desired grid-side current i ∗j (t + Ts ) ( j = a, b, c), the cost function associated with the predicted gridside current error is defined as   (11) J1 j (n cpj , n cn j ) = i ∗j (t + Ts )−i j (t + Ts ) , j = a, b, c where |i ∗j (t + Ts ) − i j (t + Ts )| denotes the absolute value of i ∗j (t + Ts ) − i j (t + Ts ); n cpj and n cn j indicate the on-state SM number of the upper- and lower-arm in phase-j, respectively. It is observed that k1 obtained in (10) is not accurate enough, hence, we relax its value to the range [η1 , η2 ], where η1 = k1 − 1 and η2 = k1 + 1. In this range, we can always find a best pair of n cpj and n cn j , named as n pj and n n j , which minimize the cost function defined in (11). The detailed calculation flowchart is shown in Fig. 3, where J1 j min denotes the minimum value of J1 j (n cpj , n cn j ), initially setting as a very large constant value C. Remark 1: Compared to the conventional MPC methods, our method is designed based on the operating situation, avoiding the needless calculations. No more than three possible statuses are considered even under high voltage levels. Besides, our proposed MPC approach is also much easier to be implemented, as no additional information and weight factor are required. B. Circulating Current Control Motived by the work in [22], a new circulating current suppression method is proposed in this section, which is presented as below.

Fig. 3.

Proposed MPC flowchart for GCC.

Based on (2), the circulating current at t + Ts is Ts [vdc − u pj (t + Ts ) − u n j (t + Ts )] + i cir j (t). 2L a (12) The desired circulating current i cir∗ j ( j = a, b, c) is set as [22], [26] i cir j (t + Ts ) =

i cir∗ j =

PAC Idc = , 3 3vdc

j = a, b, c

(13)

where Idc is the dc-side current of MMC, and PAC indicates the active power. From (13), we conclude that the desired circulating current i cir∗ j cannot be zero as long as PAC = 0. Then in order to regulate the circulating current to its desired value, the cost function for CCC is defined as ∗ J2 j (n cpj , n cn j ) = |i cir j − i cir j (t + Ts )|,

j = a, b, c.

(14)

According to (5), the grid-side current will not be affected when u n j (t + Ts ) and u pj (t + Ts ) are added to or subtracted from the same voltage level n. The smallest n introduces the least impact on SM capacitor voltages of MMC. Therefore, n = 1 is selected, i.e., two voltage levels are introduced to suppress the inner circulating current [22]. In other words, only three candidates J2 j (n cpj = n pj , n cn j = n n j ), J2 j (n cpj = n pj + 1, n cn j = n n j + 1), and J2 j (n cpj = n pj − 1, n cn j = n n j − 1) are considered here. In fact, these three statuses do not need to be considered in every sampling period. By calculating the circulating current

HUANG et al.: PRIORITY SORTING APPROACH FOR MODULAR MULTILEVEL CONVERTER BASED ON SIMPLIFIED MPC

Fig. 4.

Proposed MPC flowchart for CCC.

error error = i cir∗ j − i cir j (t), we can simplify the comparison to update the on-state SM numbers n pj and n n j as below. 1) If error > 0, the upper- and lower-arm voltages can be subtracted from the same voltage level to increase i cir j (t + Ts ). 2) If error ≤ 0, the upper- and lower-arm voltages can be added to the same voltage level to decrease i cir j (t + Ts ). The proposed MPC strategy for suppressing the circulating current is shown in Fig. 4. The final voltage levels of the upperand lower-arm are updated by minimizing J2 j . Besides, the more available choices of n cpj and n cn j can ensure the better circulating current suppression. If the specific application needs to further suppress the circulating current, additional four candidates J2 j (n cpj = n pj + 1, n cn j = n n j ), J2 j (n cpj = n pj − 1, n cn j = n n j ), J2 j (n cpj = n pj , n cn j = n n j + 1), and J2 j (n cpj = n pj , n cn j = n n j − 1) can be introduced at the cost of slightly deteriorating the grid-side current quality. The process is similar to Fig. 4, and thus omitted here. It is worthy to point out that in the circulating current suppression control, the negative sequence current control loop in [22] and [27] is needed if the grid-side voltage is unbalanced. However, this would become another research topic, as its objective varies with the different control requirements and applications, affecting current quality and the stability of the SM dc voltage. Due to the page limit, we omit the details here and recommend it as a potential future work direction. Remark 2: Compared to [22], the CCC is designed based on the circulating current error, which reduces the considered statuses to only one step. Moreover, additional four statuses are recommended in some specific applications when the requirement on the grid-side current quality is relatively low. C. Capacitor Voltage Balancing Control CVEs between SMs will be restricted into a small range when the MMC reaches its steady state with the conventional control methods [23], [25]. In this case, no frequent sorting operation is needed, as pointed out in [22]. However, this approach cannot guarantee the transient-state performance when CVEs are large. To address this concern, a novel CVBC approach is proposed in this section. As shown in Fig. 2, there are two options to

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balance the capacitor voltage, i.e., priority sorting approach and reduced frequency approach. These two options can be switched based on a predefined criterion |u dcav1 − u dcav2 |, where u dcav1 and u dcav2 are the voltages of the first two SMs of each arm. The reason why we choose the first two SMs is that the CVEs are usually the same for each arm when the capacitor voltages of SMs are balanced. Certainly, we can choose more SMs, but this will lead to a higher computational cost. Besides, in order to avoid the frequent switching between these two options, the time 10Ts is selected as the period of determining the operational condition. In the following, based on the instantaneous value of the criterion |u dcav1 − u dcav2 |, two cases are considered. Case 1: |u dcav1 − u dcav2 | < λu av j , where λ is called the error coefficient. In this case, the system is usually in its steady state; hence, the method in [22] is introduced to reduce switching times. Case 2: |u dcav1 − u dcav2 | ≥ λu av j . In this case, the system is treated as in its transient state. Therefore, a priority sorting approach is proposed to decrease the CVEs, which is presented subsequently. Just taking the upper-arm as an example, the detailed illustration is listed as follows. There are only three statuses for each SM, i.e., charging, discharging, or idle in each operating period. First, according to the measured capacitor voltage of SMi u dcavi , we can categorize the whole operating period into three groups. Group N1 : u dcavi > (1 + μ)u av j , where μ(> 0) is called the boundary coefficient. In this case, the capacitor voltage is comparably high. Therefore, the capacitor should be discharged in the next switching period. Group N2 : u dcavi < (1 − μ)u av j . It means u dcavi is relatively low, and the capacitor should be charged. Group N3 : (1 + μ)u av j ≥ u dcavi ≥ (1 − μ)u av j . It indicates u dcavi is close to its desired value. If the high control precision is not required, group N3 can be directly selected without sorting. Second, we assign the priority to above three groups as follows. 1) If the upper-arm is in discharging, the priority is sorted as p(N1 ) > p(N3 ) > p(N2 ). 2) If the upper-arm is in charging, the priority is sorted as p(N2 ) > p(N3 ) > p(N1 ). Finally, the on-state SMs can be determined based on n pj and n n j obtained from the CCC and the direction of the arm current i pj . According to the priority assigned above, we can put one or two groups into operation without sorting, reducing the computational burden. The overall CVBC procedure is shown in Fig. 5. Remark 3: In all, the CVBC designed in this paper takes both the transient and steady states into account simultaneously. In the transient state, the main task is to reduce the CVE. While in the steady state, the goal is to reduce the switching frequency and avoid needless calculations. In this way, the number of sorting operation time is decreased significantly, which greatly facilitates the implementation of the designed CVBC especially under the high voltage level condition.

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Fig. 5.

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 65, NO. 6, JUNE 2018

Grouping and sorting approach for CVBC. TABLE I PARAMETERS OF MMC SYSTEM

Fig. 6.

Parameters

Values

Rated grid-side voltage Desired dc-bus voltage of MMC Fundamental frequency f Capacitor of SM Arm inductance Grid-side inductance AC-side equivalent resistance Rated active power Number of SMs per arm

35 kV 60 kV 50 Hz 2 mF 10 mH 1 mH 0.2  60 MW 20

Schematic of the conventional approach in [25].

IV. SIMULATION RESULTS In this section, a MMC system is established to illustrate the effectiveness of our proposed method in PSCAD/EMTDC environment. The specific system parameters are summarized in Table I. For comparison, the conventional control in [25] is also applied to our system. Its detailed schematic is shown in Fig. 6, where its cost function Jc is defined as a combination of (11) and (14) by weight factors λ2 and λ3 , respectively.

A. Boundary Coefficient μ and Error Coefficient λ Design In most applications, the permitted capacitor voltage range of SM is usually set as [0.95 u av j , 1.05 u av j ], which means μ < 5%. We normalize the maximum differences of |u dcavi − u av j | as |u dcavi − u av j |/μ=5% , where μ=5% is the maximum value of |u dcavi − u av j | with μ = 5%, which are shown in Fig. 7(a). Since group N3 may operate without sorting, the larger range of N3 will result in less computational cost. But it will bring more SM dc voltages to the range (1 + μ)u av j ≥ u dcavi ≥ (1 − μ), thus leading to the more unbalanced SM dc voltages output. Considering the computational burden and control precision, μ = 2% is selected in our system. Note that both group N3 and reduced frequency approach can decrease the sorting process; thus, we select λ as λ ≤ μ. Similarly, the maximum difference of |u dcav1 − u dcav2 | is then normalized as |u dcav1 − u dcav2 |/λ=2% , where λ=2% is the value of |u dcav1 − u dcav2 | with λ = 2%. The results are shown in Fig. 7(b). It can be observed that all these normalized differences are in an acceptable range. However, the smaller λ will result in the higher computational cost. Thus, a tradeoff value λ = 2% is finally selected. B. Grid-Side Current Control In this section, comparison studies with the conventional GCC approach in [25] are carried out to analyze the grid-side current. For a fair comparison, the same CVBC approach designed in this paper is applied in both methods. Note that we have tried our best to regulate the weight factors as λ2 = 0.9 and λ3 = 0.1 for the conventional GCC. The sampling period is set as 200 μs. The results are shown in Fig. 8. For the conventional GCC, the total harmonic distortion (THD) of the grid-side current is 4.5%. While it is reduced

HUANG et al.: PRIORITY SORTING APPROACH FOR MODULAR MULTILEVEL CONVERTER BASED ON SIMPLIFIED MPC

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Fig. 7. (a) Normalized difference of the maximum |u dcavi − u av j | with various μ; (b) Normalized difference of the maximum |udcav1 − udcav2 | with various λ.

Fig. 9. Circulating current suppression: (a) total on-state SM number of phase a; circulating current with (b) 200 μs and (c) 100 μs sampling period; (d) circulating current before and after transferring the active power with the proposed controller.

Fig. 8. Grid-side current under (a) conventional GCC control in [25] and (b) proposed GCC control with 200 μs sampling period.

to 3.9% in our proposed method, which indicates that our proposed GCC approach can achieve slightly better performance on regulating grid-side current but with less computational cost as the weight factor tuning is avoided and the considered statuses are reduced. It is observed from Fig. 8 that the grid-side current can track its reference well, even though there exists some delay time.

Fig. 10. Capacitor voltages of SMs and the average number of SM switching under (a), (b) the conventional control and (c), (d) the proposed control.

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TABLE II SIMULATION COMPARISONS Item THD Average switching frequency of each SM

Approach in [25]

Proposed approach

Improvement

4.5% 990 Hz

3.9% 520 Hz

13.3% 47.5%

However, as pointed out before, there is a tradeoff between the circulating current suppression and grid-side current quality. Therefore, such slightly distorted grid-side current is acceptable when the circulating current suppression is also taken into account.

Fig. 11.

Experimental platform.

C. Circulating Current Control The performance of the designed CCC is demonstrated in Fig. 9. As shown in Fig. 9(a), the total number of the on-state SMs remains at N before introducing CCC. It is added to or subtracted from two voltage levels with CCC to suppress the circulating current. If the sampling period is 200 μs, the ripple range of the circulating current is 60 A. It is reduced to 30 A with 100 μs sampling period, as presented in Fig. 9(b) and (c), respectively. Apparently, shorter sampling period brings higher control precision, but also results in higher sampling and computational burden. It is observed from Fig. 9(d) that the circulating current is varying with the active power. During 0.7 s < t < 0.9 s, only reactive power is transferred, and thus the desired circulating current is zero. It is regulated to 0.167 kA when transferring the active power from t ࣙ 0.9 s. These results verify the effectiveness of the designed CCC. D. Voltage Balancing Control In this section, the proposed CVBC is compared to the conventional CVBC approach in [25] with the same GCC and CCC designed in this paper. The sorting process is triggered with a fixed-frequency 5 kHz. The results are shown in Fig. 10. It is observed from Fig. 10(a) and (c) that both these two approaches can adjust the fluctuation range of capacitor voltage within 160 V; meanwhile, the voltage difference among the SMs is basically the same, approximately 25 V. The average numbers of SM switching in these two methods are given in Fig. 10(b) and (d), respectively. It is observed that before t = 0.6 s, they are almost the same. However, after t = 0.6 s, compared to the result in Fig. 10(b), the average value of switching frequency for the proposed CVBC presented in Fig. 10(d) is decreased nearly half. These results indicate that the proposed CVBC can achieve the better grid-side current than the conventional one with less switching loss and lower computational burden. In Table II, we summarize the comparison result. It is observed that compared to the conventional control approach in [25], the ac current THD obtained in our proposed method is reduced by 13.3% whereas the average switching frequency of each SM is decreased by 47.5%.

Fig. 12. Grid-side current with (a) conventional GCC in [25] and (b) proposed control.

V. EXPERIMENTAL VALIDATION In this section, an experimental prototype is built to validate the proposed control method with SM number N = 10 in each arm, as shown in Fig. 11. A digital signal processor (DSP TMS320F28335) and a field-programmable gate array (ALTERA Cyclone III-EP3C16Q240) are employed in the controller design. The sampling period is set as 150 μs. The rated grid-side voltage and the desired dc-bus voltage are chosen as 380 and 700 V, respectively. The rated active power is 50 kW. The other remaining parameters are the same as those in the simulation. A. Verification of GCC In this section, the grid-side current performance obtained by the proposed GCC is compared with the GCC approach in [25]. MMC operates from the capacitive condition to the inductive condition, and the desired reactive current is changed from 10 to −11 A. The results are presented in Fig. 12. Comparing the results in Fig. 12(a) and (b), our proposed method can achieve better grid-side current quality than the GCC approach in [25] no matter the condition is capacitive or inductive. More specifically, the THDs are 5.2% and 4.3% in the inductive condition and 5.3% and 4.4% in the capacitive condition for the approach in [25] and the proposed one, respectively. Besides, in our proposed method, the settling time

HUANG et al.: PRIORITY SORTING APPROACH FOR MODULAR MULTILEVEL CONVERTER BASED ON SIMPLIFIED MPC

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Fig. 13. CCC verification. (a) Circulating current and grid-side current; (b) the THD of the grid-side currents; (c) the lower- and upper-arm currents of phase a with and without the designed CCC; (d) the circulating current; (e) the THD of the grid-side currents in the conventional control [25]; (f) circulating current; and (g) grid-side currents THD of the designed CCC with additional four statuses.

from capacitive to inductive condition is less than 10 ms, which is almost half of that in [25], where it is around 20 ms. B. Comparison of CCC In this section, the performance of the proposed method for suppressing the circulating current is verified. And it is also compared with the CCC approach in [25] while employing the

same CVBC designed in this paper. The desired reactive current is set as 15 A under the purely capacitive condition. Hence, the desired circulating current is zero. As shown in Fig. 13(a), before the proposed CCC is activated, the circulating current fluctuates periodically. However, when the proposed CCC is activated, the amplitude of circulating current is reduced to 0.3 A within 1 ms. Besides, it is also observed from Fig. 13(a) and (b) that the grid-side current remains un-

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TABLE III NUMBER OF CONSIDERED STATUSES OF THE CONVENTIONAL AND PROPOSED APPROACHES Approach Conventional MPC [15] Improved MPC1 [22] Improved MPC2 [25] Proposed approach

GCC

CCC

N = 10

Improvement

N C2N N+1 N+1 3

3 N+1 1

184 756 14 22 4

99.99% 71.43% 81.82% -

TABLE IV RESOURCE UTILIZATION IN FPGA OF THE PROPOSED CVBC Items

Fig. 14. Capacitor voltages of the conventional control in [22] and the proposed control.

changed with its THD being around 3.7%, which indicates the proposed CCC has almost no impact on the grid-side current. In addition, the proposed CCC can also drive the upper- and lower-arm currents to balance, as shown in Fig. 13(c). Fig. 13(d) shows the results of the CCC approach in [25]. It can be seen that the amplitude of circulating current is reduced to 0.25 A when the CCC is activated, which is slightly better than ours. However, it is achieved by sacrificing the quality of the grid-side current, whose THD is increased to 4.4%, as shown in Fig. 13(e). Besides, its settling time is 5 ms, almost five times slower than ours. In order to further improve the circulating current suppression ability of our proposed method, four additional candidates J2 j (n cpj = n pj + 1, n cn j = n n j ), J2 j (n cpj = n pj − 1, n cn j = n n j ), J2 j (n cpj = n pj , n cn j = n n j + 1), and J2 j (n cpj = n pj , n cn j = n n j − 1) introduced in Section III-B are added. The experimental results are shown in Fig. 13(f) and (g). It is observed that the amplitude of the circulating current is further reduced to 0.1 A. As in the additional four statuses, the on-state SM numbers of the upper- and lower-arm n cpj and n cn j are not added to or subtracted from the same voltage level. The quality of the grid-side current is then affected with its THD increased to 5.3%. These results indicate that there is a tradeoff between the suppression of the circulating current and the quality of the grid-side current. C. Comparison of CVBC In this section, the performance of the proposed CVBC is demonstrated and is also compared with the CVBC approach in [22]. The capacitor dc voltages in the upper-arms of phase a are given in Fig. 14. It is shown that when the CVBCs are activated, both these two approaches can regulate the voltage error among the SMs from 5 to 0.5 V. However, the settling time of the proposed CVBC is 40 ms, which is almost two times faster than the approach in [22]. These results validate the advantages of our CVBC approach over the one in [22], which are stated in Remark 3.

Pre-process Grouping Sorting Package Total Chip available Utilization

Logical cell

Dedicated logic registers

43 548 2677 468 3736 15 408 24.2%

32 327 1435 374 2168 15 408 14%

D. Comparison of Computational Burden In order to compare the computational burden, the considered statuses are summarized in Table III for the MMC with different approaches in each phase. For the conventional MPC in [15], the total number of conN . While, the total considered statuses sidered statuses is C2N are reduced to N + 4 and 2N + 2 for GCC and CCC in [22] and [25], respectively. However, in our proposed method, the number of considered statuses is always 4 even under the high voltage levels. It is observed from Table III that compared to the conventional MPC approaches, the considered status of our approach is reduced by more than 71.43% under N = 10. Note that in our system, the GCC and CCC are implemented in DSP (TMS320F28335), with the oscillator frequency being 150 MHz. This indicates that one clock cycle time T is 6.67 ns. For the method in [15], the operating time is much longer than 6.67 ns × 184 756 = 1232 μs, which is beyond the sample time (150 μs) in our system. Therefore, this method may not be suitable for our system. In order to alleviate the DSP burden, the CVBC is implemented in FPGA. The resource utilization of the designed CVBC is summarized in Table IV, and the executing clock cycle is shown in Fig. 15. The maximum utilization in FPGA (MUF) is only 24.2% with respects to logic cells. Therefore, there is adequate resource to implement the designed CVBC in the selected FPGA chip. If the system clock of FPGA is set as 30 MHz, then the maximum computational time of CVBC is about 5.5 μs. The comprehensive comparison results are summarized in Table V. It is verified that there is a tradeoff between the gridside current quality and the circulating current suppression. Besides, compared to the CVBC in [22], the transient settling time of the SM capacitor voltage is decreased by nearly half. Note that in [22] only reduced frequency approach is implemented to

HUANG et al.: PRIORITY SORTING APPROACH FOR MODULAR MULTILEVEL CONVERTER BASED ON SIMPLIFIED MPC

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then, the CCC is embedded with a cost function involving the circulating current error to reduce the computational burden. Finally, the CVBC is designed to guarantee the transient performance of capacitor voltage and reduce the switching frequency in the steady state. Simulation and experimental results have shown that the proposed strategy achieves better performance than conventional methods with lower computational cost. Since the computational time of the proposed strategy always keeps unchanged for GCC and CCC, and slightly increases with the number of SMs for CVBC, it is especially suitable for the applications where a large number of SMs are required. In future, the stability analysis of the SM dc voltage will be carried out.

Fig. 15.

REFERENCES

Execution clock cycle of the proposed CVBC in FPGA. TABLE V PERFORMANCE COMPARISONS

Scheme

THD(Capacitive) THD(Inductive)

Transient settling time

Proposed GCC GCC in [25]

4.4% 5.3%

4.3% 5.2%

10 ms 20 ms

Scheme

THD

Transient settling time

Proposed CCC Proposed CCC with additional 4 statuses CCC in [25]

3.7% 5.3%

Suppressed Circulating current 0.3 A 0.1 A

4.4%

0.25 A

5 ms

Scheme

Transient settling time

Proposed CVBC CVBC in [22] Approach Improved MPC1 [22] Improved MPC2 [25] Proposed approach

1 ms 3 ms

40 ms 75 ms GCC+CCC in CVBC in steady Total Time DSP state 15 μs 4.5 μs 19.5 μs

MUF 23.9%

19 μs

4.9 μs

23.9 μs

36%

10 μs

4.5 μs

14.7 μs

24.2%

achieve MUF of improved MPC1 [22], resulting in the relatively lower MUF than the proposed approach. Comparably, the total calculation time of the proposed approach is reduced by more than 24%. Moreover, our approach will be more superior to the other approaches when the voltage level is higher, as summarized in Table III. These performances further demonstrate the superiority of the proposed control approach. VI. CONCLUSION In order to reduce the computational burden of conventional MPC methods, a priority sorting approach based on simplified MPC is proposed for MMCs in this paper. Its main objective is to regulate the grid-side current, suppress the circulating current, and balance the capacitor voltage. The GCC is first designed based on the desired predicted output voltage of the equivalent MMC circuit to get rid of the redundant statuses. After

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Jingjing Huang received the B.S. degree from the Henan University of Science and Technology, Luoyang, China, in 2008, and the Ph.D. degree from Xi’an Jiaotong University, Xi’an, China, in 2014, both in electrical engineering. She has been with Xi’an University of Technology as a Lecturer since April 2014. She is currently a Postdoctor at Nanyang Technological University, Singapore since December 2016. Her research interests include renewable energy system, high-frequency transformer, hybrid ac/dc microgrid, and high-power converters.

Bo Yang received the B.S., M.S., and Ph.D. degrees in electrical engineering from Xi’an University of Technology, Xi’an, China, in 2006, 2009, and 2014, respectively. He has been a Lecturer in the Department of Electrical Engineering, Xi’an University of Technology since 2014. His research interests include multilevel converters and power quality control.

Fanghong Guo (M’16) received the B. Eng. degree in automation science from Southeast University, Nanjing, China, in 2010, the M. Eng. degree in automation science and electrical engineering from Beihang University, Beijing, China, in 2013, and the Ph.D. degree in sustainable earth from the Energy Research Institute @NTU, Interdisciplinary Graduate School, Nanyang Technological University, Singapore, in 2016. He is currently a Scientist with the Experimental Power Grid Center, Agency for Science, Technology and Research, Singapore. His research interests include distributed cooperative control, distributed optimization on microgrid systems, and smart grid. Dr. Guo received the 2015 National Award for Outstanding Selffinanced Chinese Students Study Abroad in 2015.

Zaifu Wang received the B.S. degree in electrical engineering from Qufu Normal University, Rizhao, China. He is currently working toward the Ph.D. degree in electrical engineering at Xi’an Jiaotong University, Xi’an, China. His main field of interests includes VSC-HVdc and flexible ac transmission systems.

Xiangqian Tong received the B.S. degree from the Shaanxi Institute of Technology, Hanzhong, China, in 1983, the M.S. degree from Xi’an University of Technology, Xi’an, China, in 1989, and the Ph.D. degree from Xi’an Jiaotong University, Xi’an, China, in 2006, all in electrical engineering. He is currently a Professor and the Academic Leader of electrical engineering with the Xi’an University of Technology. His research interests include the application of power electronics in power system and control of power quality, especially the power filter, static synchronous compensator, and high voltage direct current.

Aimin Zhang (M’12) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Xi’an Jiaotong University, Xi’an, China, in 1983, 1989, and 2008, respectively. Since 1983, she has been with the School of Electronic and Information Engineering, Xi’an Jiaotong University, where she is currently a Professor. Her current research interests include adaptive control, new energy control systems, and embedded intelligent measurement and control systems.

Jianfang Xiao (S’11–M’16) received the B.Sc. degree (with first-class honor) in mechanical and aerospace engineering and the Ph.D. degree in electrical and electronic engineering from Nanyang Technological University (NTU), Singapore, in 2011 and 2015, respectively. He is currently a Research Fellow with the Energy Research Institute of NTU.