micromachines Article
Process Variability—Technological Challenge and Design Issue for Nanoscale Devices Jürgen Lorenz 1, * , Eberhard Bär 1 , Sylvain Barraud 2 , Andrew R. Brown 3 , Peter Evanschitzky 1 , Fabian Klüpfel 1 and Liping Wang 3 1
2 3
*
Fraunhofer Institut für Integrierte Systeme und Bauelementetechnologie, Schottkystrasse 10, 91058 Erlangen, Germany;
[email protected] (E.B.);
[email protected] (P.E.);
[email protected] (F.K.) CEA, LETI, MINATEC campus and Univ. Grenoble Alpes, 38054 Grenoble, France;
[email protected] Synopsys Northern Europe Ltd., Glasgow G3 8HB, UK;
[email protected] (A.R.B.);
[email protected] (L.W.) Correspondence:
[email protected]; Tel.: +49-9131-761-210
Received: 8 December 2018; Accepted: 15 December 2018; Published: 23 December 2018
Abstract: Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated. Keywords: process simulation; device simulation; compact models; process variations; systematic variations; statistical variations; FinFETs; nanowires; nanosheets
1. Introduction Aggressively scaled transistors are affected by three kinds of process variations. Most frequently and since long discussed in the literature are statistical process variations which are caused by the granularity of matter, such as Random Dopant Fluctuations (RDF). However, as summarized earlier [1] a diversity of systematic process variations is caused by non-idealities of process equipment, like inhomogeneity of gas flow or temperature distributions, or imperfect control of parameters like the distance between the last lens and the wafer in lithography, the so-called defocus. Moreover, layout effects caused, e.g., by pattern density also affect the results of various process steps [1]. Especially for aggressively scaled three-dimensional devices such as FinFETs or nanowires as shown in Figure 1, not only systematic variations of simple geometrical parameters such as the gate length must be considered, but also three-dimensional shapes may vary, critically affecting device performance. These requirements are being addressed and met in the cooperative project SUPERAID7 [2] funded by the European Commission within the Horizon 2020 programme.
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Figure1.1.Example Example transistor addressed in SUPERAID7: (a) Trigate; (b) stacked nanowire; Figure ofof transistor as as addressed in SUPERAID7: (a) Trigate; (b) stacked nanowire; (c) (c) stacked nanosheet. stacked nanosheet.
Whereasthe theimpact impactof ofstatistical statisticalvariations variationssuch suchas asRandom RandomDopant DopantFluctuations Fluctuations(RDF), (RDF),Metal Metal Whereas Gate Granularity (MGG), and Line Edge Roughness (LER) have been frequently and since long Gate Granularity (MGG), and Line Edge Roughness (LER) have been frequently and since long discussedininthe theliterature literature(e.g., (e.g., [3–5]), effects of systematic process variations sogot far discussed in in [3–5]), thethe effects of systematic process variations havehave so far got much less attention. Some publications with involvement of authors of this paper referred to much less attention. Some publications with involvement of authors of this paper referred to bulk bulk transistors [1,6–9]. Two examples for the impact of patterning processes on FinFET transistors transistors [1,6–9]. Two examples for the impact of patterning processes on FinFET transistors were were presented [10–12], the latter discussing impact staticrandom-access random-access presented earlierearlier [10–12], in theinlatter casecase alsoalso discussing thethe impact onona astatic memory (SRAM) cell. However, these papers did not discuss the key differences between the different memory (SRAM) cell. However, these papers did not discuss the key differences between the patterning processesprocesses in terms of and impact onimpact design.on Furthermore, the generalthe case where different patterning invariability terms of variability and design. Furthermore, general not only two three geometrical parametersparameters of the transistor, fin width gate length, are case where notoronly two or three geometrical of the e.g., transistor, e.g., and fin width and gate changed but also the shape of a fin or of nanowires was not considered length, are changed but also the shape of a fin or of nanowires was not considered Inthe thefollowing, following,the themain mainprocesses processesavailable availablefor forthe thepatterning patterningof ofthree-dimensional three-dimensionalnanoscale nanoscale In transistors are discussed concerning their simulation and their variability, and a method toextract extract transistors are discussed concerning their simulation and their variability, and a method to compact models which include both systematic and stochastic variations which may also affect the compact models which include both systematic and stochastic variations which may also affect the shapeof ofthe thetransistor transistorisispresented. presented. shape 2. Materials and Methods 2. Materials and Methods This paper reports about results obtained in the cooperative project SUPERAID7 [2], funded This paper reports about results obtained in the cooperative project SUPERAID7 [2], funded within the Horizon 2020 programme of the European Union, and partly about related background within the Horizon 2020 programme of the European Union, and partly about related background work from Fraunhofer IISB, and from partners as cited. Within SUPERAID7 a software system for work from Fraunhofer IISB, and from partners as cited. Within SUPERAID7 a software system for the simulation of the impact of systematic and statistical process variations on advanced More Moore the simulation of the impact of systematic and statistical process variations on advanced More Moore devices and circuits down to the 7 nm node and below has been developed, including especially devices and circuits down to the 7 nm node and below has been developed, including especially interconnects. Besides enhanced and new software tools this needs improved physical models and interconnects. Besides enhanced and new software tools this needs improved physical models and extended compact models. In terms of software integration and application, SUPERAID7 and this extended compact models. In terms of software integration and application, SUPERAID7 and this paper are partly based on the SENTAURUS simulation system from Synopsys [13], which is for paper are partly based on the SENTAURUS simulation system from Synopsys [13], which is for academic use also available via EUROPRACTICE [14]. Topography simulation for this paper has academic use also available via EUROPRACTICE [14]. Topography simulation for this paper has been performed with the tools Dr.LiTHO [15], ANETCH [16], and DEP3D [17], which are available been performed with the tools Dr.LiTHO [15], ANETCH [16], and DEP3D [17], which are available under license from Fraunhofer IISB, and also with ViennaTS which is available from TU Wien as Open under license from Fraunhofer IISB, and also with ViennaTS which is available from TU Wien as Source [18]. Open Source [18]. 3. Results 3. Results 3.1. Nanoscale Patterning Processes and Their Variations 3.1. Nanoscale Patterning Processes and Their Variations Besides the physical properties of the semiconductor material used, which among others limit Besides the physical properties the semiconductor material used,challenging. which among limit carrier mobility, the patterning of theof transistors has increasingly become Thisothers is both due carrier mobility, the patterning of the transistors has increasingly become challenging. This is both to the ever-smaller feature sizes needed and the complex three-dimensional geometries employed for due to the ever-smaller feature sizes needed and the complex three-dimensional geometries
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employed for nanoscale transistors in order to achieve good channel control. In the following, this nanoscale transistors in order to achieve good channel control. In the following, this development is development is outlined especially in view of process variations and design implications. outlined especially in view of process variations and design implications. 3.1.1. Lithography 3.1.1. Lithography For traditional bulk CMOS, mainly gates and their spacers had to be patterned. In corresponding For traditional bulk CMOS, mainly gates and their spacers had to be patterned. In corresponding simulations of lithography, etching, and deposition mainly, the resulting footprint of gate and spacer simulations of lithography, etching, and deposition mainly, the resulting footprint of gate and spacer was relevant, because this defined the physical gate length L and width W. In turn, variations in these was relevant, because this defined the physical gate length L and width W. In turn, variations in patterning processes led to variations of L and W, which could readily be considered during the these patterning processes led to variations of L and W, which could readily be considered during extraction of compact models [8]. In most cases, standard optical lithography was used, partly the extraction of compact models [8]. In most cases, standard optical lithography was used, partly including water immersion [19]. Such lithography steps are subject to variations of the distance including water immersion [19]. Such lithography steps are subject to variations of the distance between the last lens of the optical system and the photoresist to be developed (which can be between the last lens of the optical system and the photoresist to be developed (which can be transferred transferred into the so-called focus position or focus) and of the illumination dose used. These lead into the so-called focus position or focus) and of the illumination dose used. These lead to variations to variations of the feature size printed, the so-called critical dimensions (CD). Generally, best of the feature size printed, the so-called critical dimensions (CD). Generally, best resolution is obtained resolution is obtained for so-called dense lines, that is, a regular pattern of lines and spaces of the for so-called dense lines, that is, a regular pattern of lines and spaces of the same width (duty factor same width (duty factor 1:1). However, the situation encountered during circuit fabrication usually 1:1). However, the situation encountered during circuit fabrication usually deviates from this situation. deviates from this situation. In Figure 2, the CD of the intensity distribution of the light just above In Figure 2, the CD of the intensity distribution of the light just above the resist (the so-called aerial the resist (the so-called aerial image) is shown for 65 nm lines and 130 nm spaces (duty factor 1:2). image) is shown for 65 nm lines and 130 nm spaces (duty factor 1:2). The figure illustrates how The figure illustrates how the variations of focus and dose lead to variations of the CD of the aerial the variations of focus and dose lead to variations of the CD of the aerial image, which would then image, which would then during resist development be transferred into variations of the CD of the during resist development be transferred into variations of the CD of the resist structures. Moreover, resist structures. Moreover, the distribution of the CDs is shifted from the nominal 65 nm to larger the distribution of the CDs is shifted from the nominal 65 nm to larger values. Figure 3 shows the values. Figure 3 shows the dependence of the CD on focus and dose: Here, the central curve shows dependence of the CD on focus and dose: Here, the central curve shows the combinations of focus and the combinations of focus and dose which lead to the nominal CD of 65 nm. The two other curves dose which lead to the nominal CD of 65 nm. The two other curves show the combinations of focus show the combinations of focus and dose which result in a CD increased (upper line) or decreased and dose which result in a CD increased (upper line) or decreased (lower line) by 10%, respectively. (lower line) by 10%, respectively. A standard task in the lithography community is then to optimize A standard task in the lithography community is then to optimize the lithography process in terms of the lithography process in terms of its stability against variations of dose and focus. Here, the soits stability against variations of dose and focus. Here, the so-called process window is maximized, called process window is maximized, which is the largest rectangle in the space of focus and dose which is the largest rectangle in the space of focus and dose which results in CDs which deviate not which results in CDs which deviate not more than 10% from the targets values. With the duty factor more than 10% from the targets values. With the duty factor of 1:2 shown in Figure 3a, the process of 1:2 shown in Figure 3a, the process window is rather small. For the ideal case of dense lines with window is rather small. For the ideal case of dense lines with a duty factor of 1:1, shown in Figure 3b, a duty factor of 1:1, shown in Figure 3b, the process window is much larger. This illustrates that both the process window is much larger. This illustrates that both the resolution and also the variability of the resolution and also the variability of a lithography process critically depend not only on the size a lithography process critically depend not only on the size but also on the layout of the features or but also on the layout of the features or circuits to be printed. circuits to be printed.
Figure 2. Impact of variations of focus and dose on a 193 nm dry lithography process with adapted Figure 2. Impact of variations of focus and dose on a 193 nm dry lithography process with adapted illumination for 65 nm lines/130 nm spaces (duty factor 1:2): Variation of (a) focus and (b) threshold illumination for 65 nm lines/130 nm spaces (duty factor 1:2): Variation of (a) focus and (b) threshold considered; (c) resulting variation of CD. considered; (c) resulting variation of CD.
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Figure3.3.Aerial Aerialimage-based image-basedprocess processwindow windowonona a193 193nm nmdry drylithography lithographysystem systemwith withadapted adapted Figure illuminationasasininFigure Figure2,2,for for(a) (a)65 65nm nmlines/130 lines/130nm nmspaces spaces(duty (dutyfactor factor1:2). 1:2).(b) (b)6565nm nmdense denselines: lines: illumination 65nmlines linesand andspaces spaceswith withaaduty dutyfactor factorofof1:1. 1:1. 65nm
Anotherimportant importantnon-ideality non-idealitywhich whichchallenges challengesaggressive aggressivepatterning patterningsteps stepsisisthe theprinting printingofof Another defects. These include especially defects in the multilayer mirrors used for masks and instead of lenses defects. These include especially defects in the multilayer mirrors used for masks and instead of in an Extreme Ultraviolet (EUV) lithography step, or defects the mask [20]. Equipment lenses in an Extreme Ultraviolet (EUV) lithography step, orofdefects of structures the mask structures [20]. and mask makers generally trygenerally to compensate defectsmirror [20]. Contamination with particles during Equipment and mask makers try tomirror compensate defects [20]. Contamination with the handling ofthe masks can beofcompensated the use of pellicles which move the particles out particles during handling masks can beby compensated by the use of pellicles which move theof the mask area and in turn make sure that they do not print [21]. The effect of defects of the mask particles out of the mask area and in turn make sure that they do not print [21]. The effect of defects should be considered as a processasvariation as the patterns on the wafer ofitself the mask itself should be considered a processinsofar variation insofar as thegenerated patterns generated on may the deviate from the shapes which would be generated a defect. Figure 4 shows an 4example for wafer may deviate from the shapes which would be without generated without a defect. Figure shows an mask defect printing as frequently simulated in the lithography community. However, the impact on example for mask defect printing as frequently simulated in the lithography community. However, device level so far nothas been systematically. In order to study this effect, the this subsequent the impact onhas device level soconsidered far not been considered systematically. In order to study effect, etching of the underlying to be patterned byto thebelithography must be considered. needs the subsequent etching oflayer the underlying layer patterned step by the lithography stepThis must be the intimate coupling of lithography and etching simulation, which is one of the core topics of considered. This needs the intimate coupling of lithography and etching simulation, which is one the of SUPERAID7 Figure 5 shows how the image of the mask shown in Figure is transferred the core topicsproject. of the SUPERAID7 project. Figure 5 shows how defect the image of the mask 4defect shown the underlying layer for extreme cases anisotropic and isotropic The etching ininto Figure 4 is transferred intothe thetwo underlying layeroffor the two extreme cases etching. of anisotropic and simulator ANETCH [16] used for this example can be calibrated to the specific etching process isotropic etching. The etching simulator ANETCH [16] used for this example can be calibratedapplied to the and therefore assessment of defectenables transferthe to assessment patterned layers. specific etchingenables processthe applied and therefore of defect transfer to patterned Shrinking device dimensions have led to more complex device architectures in order to maintain layers. sufficient electrostatic control of the channel, low leakage and high drive currents. In order to extend CMOS scaling to its limits, first buried oxide layers were introduced for the so-called SOI (silicon-on-insulator) transistors. This has been followed by transistor architectures such as FinFETs, (stacked) nanowires and (stacked) nanosheets. These small and truly three-dimensional structures lead to considerable challenges for the patterning processes and for their simulation. As outlined below, they also generate different problems in terms of variability and impact on design. The problem starts from the basic limitation of optical lithography, where the minimum half pitch printed is given by d = k1 ·λ/NA, where k1 is the technology factor with minimum value of 0.25 for dense lines, λ is the wavelength of the light used, and NA is the numerical aperture, equal to the sine of the opening angle of the last lens times the refractive index of the medium between lens and wafer (1 for air, and 1.44 for water). With 193 nm being the minimum wavelength at which lenses are sufficiently transparent, a minimum half pitch for dense lines of about 34 nm results in case of water immersion lithography.
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Figure 4. Example for defect printing in 193 nm dry optical lithography. Mask defects considered (65 nm dense lines/spaces with (a) 30 nm extrusion and (b) 50 nm intrusion;Mask (c) and (d) considered resulting resist Figure 4. Examplefor fordefect defect printing in dry optical lithography. defects (65 Figure 4. Example printing in193 193nm nm dry optical lithography. Mask defects considered geometries for (a) and (b), respectively, for lithography with ideal focus and dose.. nm dense lines/spaces with (a) 30 nm extrusion and (b) 50 nm intrusion; (c) and (d) resulting resist (65 nm dense lines/spaces with (a) 30 nm extrusion and (b) 50 nm intrusion; (c) and (d) resulting resist geometries for (a) and (b), respectively, for lithography with ideal focus and dose..
geometries for (a) and (b), respectively, for lithography with ideal focus and dose.
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Figure 5. Simulation of oxide etching using the resist shape of Figure 4c as a mask. (a) Isotropic
Figure Simulationofofoxide oxide etching using of of Figure 4c as mask. (a) Isotropic etching. Figure 5. 5.Simulation usingthe theresist resistshape shape Figure 4caas a mask. (a) Isotropic etching. (b) Anisotropic etching. To allow better visualization of the etched material, the resist mask (b) Anisotropic etching. To allow betterbetter visualization of theofetched material, the resist mask is not etching. (b) Anisotropic etching. To allow visualization the etched material, the resist mask is not shown. The lateral width of the simulation domain is 190 nm. shown. TheThe lateral width of the simulation domain is 190 nm.nm. is not shown. lateral width of the simulation domain is 190
Shrinking device dimensions have led to more complex device architectures in order to maintain
The favorite industrial approaches patterning of nanoscale devices smaller than that limit Shrinking device dimensions have ledfor tothe more device sufficient electrostatic control of the channel, low complex leakage and higharchitectures drive currents.inInorder orderto tomaintain extend are various kinds of double or even quadruple patterning. In Litho-Etch-Litho-Etch (LELE) [22] and sufficient electrostatic control theburied channel, low leakage high drive currents. InSOI order to extend CMOS scaling to its limits,of first oxide layers wereand introduced for the so-called (silicon-onLitho-Freeze-Litho-Etch (LFLE) [23] the number features is doubled and the pitch halved, by CMOS scaling to its limits,This first has buried layers were introduced for the so-called SOIsize (silicon-oninsulator) transistors. beenoxide followed by of transistor architectures such as FinFETs, (stacked) exposing the wafer twice with two different masks (e.g., the mask shifted by half the pitch nanowires and (stacked) Thesebysmall and truly three-dimensional lead for to the insulator) transistors. This hasnanosheets. been followed transistor architectures such as structures FinFETs, (stacked) second illumination), employing some memory thesimulation. photoresist finally developing considerable challenges for the patterning processes andtruly forof their Asand outlined below, they to nanowires and (stacked) nanosheets. These small process and three-dimensional structures lead the resist after the second illumination. Consequently, focus and especially dose variations not also generate different problems in terms of variability and impact on design. The problem starts considerable challenges for the patterning processes and for their simulation. As outlined below,are they from the basic limitation of optical lithography, where the minimum half pitch printed is given by d correlated between these two incremental lithography steps. This has severe consequences on circuit also generate different problems in terms of variability and impact on design. The problem starts = ke.g., 1·λ/NA, where k1 is the technology factor with value of 0.25 for dense lines,6.λ As is the level: forlimitation an SRAM cell the densest structures areminimum the gate lines, see Figure shown from the basic of optical lithography, where the polysilicon minimum half pitch printed is given by d wavelength of the light used,T1, andT2, NAand is the numerical aperture, equal toillumination the sine of thestep, opening angle the therein, the three transistors T6 are patterned with one whereas = k1·λ/NA, where k1 is the technology factor with minimum value of 0.25 for dense lines, λ is the transistorsofT3, and T 5 and are patterned with the other illumination step. focus and dose wavelength theT4, light used, NA is the numerical aperture, equal to the sineInofturn, the opening angle variations correlate within each of the two triples of transistors, but especially in terms of dose
resist after the second illumination. Consequently, focus and especially dose variations are not correlated between these two incremental lithography steps. This has severe consequences on circuit level: e.g., for an SRAM cell the densest structures are the polysilicon gate lines, see Figure 6. As shown therein, the three transistors T1, T2, and T6 are patterned with one illumination step, whereas Micromachines 2019, 10,T4, 6 and T 5 are patterned with the other illumination step. In turn, focus and 6dose of 16 the transistors T3, variations correlate within each of the two triples of transistors, but especially in terms of dose not between the two triples. This has severe consequences for variability-aware circuit simulation. not between the two triples. This has severe consequences for variability-aware circuit simulation. Considering dose variations in the double patterning step for example, one value of the varying dose Considering dose variations in the double patterning step for example, one value of the varying dose must be used for the first triple and a (likely different) value for the second triple. In turn, the dose must be used for the first triple and a (likely different) value for the second triple. In turn, the dose variations may, e.g., cause an increase of the CD for the first triple and a decrease for the second one, variations may, e.g., cause an increase of the CD for the first triple and a decrease for the second leading to negative consequences for circuit performance. This was discussed in more detail one, leading to negative consequences for circuit performance. This was discussed in more detail elsewhere [10]. elsewhere [10].
Figure 6. Top-view of lithography simulation of an SRAM cell. Black vertical features are the active Figure 6. Top-view of lithography simulation of an SRAM cell. Black vertical features are the active silicon areas, the horizontal light grey and dark grey features are the polysilicon gate areas generated silicon areas, the horizontal light grey and dark grey features are the polysilicon gate areas generated with the first and the second incremental lithography step, respectively. Transistors T1 to T6 are with the first and the second incremental lithography step, respectively. Transistors T1 to T6 are explained in the text. explained in the text.
A different situation holds for Self-Aligned Double Patterning (SADP): Here, first a carbon layer A different situation holds for Self-Aligned Patterning (SADP): followed Here, firstbya back carbon layer is patterned by optical lithography. Then, spacersDouble are created by deposition etching, is patterned Then, spacers are created by deposition followed by back see Figure 7.by Inoptical result, lithography. the pattern density is doubled compared with the initial pattern of theetching, carbon see Figure 7. In result, the pattern density is doubled compared with the initial pattern of lines. The CDs of the final spacers are nearly independent of the lithography step, and the are carbon largely lines. The of the finaland spacers areprocesses nearly independent of the lithography step, largely defined byCDs the deposition etching used. Variations of the CDs depend onand the are parameters defined by the deposition and etching processes used. Variations of the CDs depend of the etching and deposition processes [24]. Because etching and deposition partly dependon on the the parameters of the etching and deposition processes [24]. Because etching and deposition partly open view angle of the surface element towards the reactor volume, a layout dependence of the CD depend on theThe open angle ofisthe surfacefrom element towards reactor volume, atarget layout is introduced: CDview of outer lines different the CD of innerthe lines. An important of Micromachines 2018, 9, xCD FORisPEER REVIEW The CD of outer lines is different from the CD of inner lines. 7 ofAn 17 dependence of the introduced: process optimization is the tuning of the deposition and etching processes in order to minimize their important target of process optimization is the tuning of the deposition and etching processes in order variability across the wafer and the layout impact explained above. to minimize their variability across the wafer and the layout impact explained above.
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Figure 7. Example for the simulation of Self-Aligned Double Patterning: (a) carbon lines patterned by optical lithography; (b) layer deposition; (c) spacer pattern pattern after after back back etching. etching.
For current FinFET transistors, usually SADP is applied for the patterning of the fins as dense lines, whereas LELE is used for gate patterning, patterning, because because it it is is more more flexible flexible in in terms terms of of the the layouts. layouts. Another design issue appears appears in case of EUV. Here, soft X-rays with 13.5 nm wavelength are instead of of laser laser light. light.Because Becauselenses lensesare arenot notsufficiently sufficiently transparent light below used instead transparent forfor light below 193193 nm,nm, in in EUV instead of refractive optics, reflective optics are used, consisting of multilayer mirrors and EUV instead of refractive optics, reflective optics are used, consisting of multilayer mirrors and new new absorber materials [20]. Whereas dose and defocus continue to besources major sources of systematic absorber materials [20]. Whereas dose and defocus continue to be major of systematic process process variability, EUVtoleads to an additional issue, has which so far notaddressed been addressed variability, EUV leads an additional design design issue, which so has far not been when when discussing process flows for the fabrication of advanced transistors. Because the reflected light discussing process flows for the fabrication of advanced transistors. Because the reflected light must be separated from the incoming light, illumination of all mirrors and especially of the mask is not vertical but tilted by a so-called “chief ray angle” of about 5.3°, see Figure 8. In turn, features generate an asymmetric shadowing relative to the plane of incidence, resulting in a position shift, a CD increase and a telecentricity error. The first two effects can be compensated by the so-called “Optical Proximity Correction” (OPC) techniques. The third effect introduces an additional source of
Another design issue appears in case of EUV. Here, soft X-rays with 13.5 nm wavelength are used instead of laser light. Because lenses are not sufficiently transparent for light below 193 nm, in EUV instead of refractive optics, reflective optics are used, consisting of multilayer mirrors and new absorber materials [20]. Whereas dose and defocus continue to be major sources of systematic process Micromachines 2019, 10, 6 7 of 16 variability, EUV leads to an additional design issue, which has so far not been addressed when discussing process flows for the fabrication of advanced transistors. Because the reflected light must be separated from from the incoming light,light, illumination of allofmirrors and and especially of the is not must be separated the incoming illumination all mirrors especially of mask the mask is vertical but tilted by a so-called “chief ray angle” of about 5.3°, see Figure 8. In turn, features generate ◦ not vertical but tilted by a so-called “chief ray angle” of about 5.3 , see Figure 8. In turn, features an asymmetric shadowing relativerelative to thetoplane of incidence, resulting in in a aposition CD generate an asymmetric shadowing the plane of incidence, resulting positionshift, shift, aa CD increase and a telecentricity error. The first two effects can be compensated by the so-called “Optical increase and a telecentricity error. The first two effects can be compensated by the so-called “Optical Proximity Correction” Correction”(OPC) (OPC) techniques. introduces an additional source of Proximity techniques. The The thirdthird effect effect introduces an additional source of variations variations since it causes a focus dependent position of the features. Furthermore, the absorber since it causes a focus dependent position of the features. Furthermore, the absorber features are features are thick compared to the illumination wavelength resulting in phase deformations causing thick compared to the illumination wavelength resulting in phase deformations causing mask-induced mask-induced like effects. Finally, a new class of defects, the multilayer defects, aberration like aberration effects. Finally, a new class of defects, the multilayer defects, introduce newintroduce issues in new issues in the field of defect detection and repair. the field of defect detection and repair.
Figure Figure 8. 8. Principle Principle of of illumination illumination of of an an EUV EUV mirror mirror and and mask. mask. ϕ ϕ denotes the chief ray angle.
In In summary, summary, various various kinds kinds of of systematic, systematic, layout-dependent layout-dependent and and defect-induced defect-induced variations variations influence the patterns generated in a lithography or multiple patterning process. There are major even influence the patterns generated in a lithography or multiple patterning process. There are major qualitative differences in terms of variability between optical lithography, SADP and other double even qualitative differences in terms of variability between optical lithography, SADP and other patterning processes.processes. Etching and deposition, which are key components SADP, are discussed in the double patterning Etching and deposition, which are keyofcomponents of SADP, are next chapter. discussed in the next chapter. 3.1.2. Deposition and Etching In semiconductor technology, a large variety of deposition and etching processes is employed. Deposition processes differ among others in terms of the properties of the deposited layers and the layer conformality. The latter for instance critically influences the filling of contact holes and trenches. Etching processes differ, e.g., in terms of selectivity concerning the materials to be etched, etch-induced damage, and the degree of isotropy and anisotropy. Equipment simulation tools such as CFD-ACE+ [25] and Q-VT [26], which model the electrical, thermal, fluid-dynamical, and plasma properties of the reactor can be used to predict the fluxes and energies of different species (ions, neutrals) above the flat or patterned wafer. Using these as boundary conditions, feature-scale simulation allows one to simulate the evolving geometry during deposition or etching. To this end, the interaction of the different species with the substrate is considered and local values of the different fluxes are extracted which allow one to determine local etching or deposition rates. Examples for this approach are given in [27] for deposition and in [28] for etching. The discussion of the large variety of deposition and etching processes is beyond the scope of this paper. Deposition and etching processes are subject to several sources of systematic variability. Depending on the process in question, these include the inhomogeneity of gas flow and temperature in the etching or deposition reactor, the non-homogeneous emission of metal atoms, e.g., from a sputter target, or the finite size of a sputter target. These sources lead to variations of deposition and
3.1.2. Deposition and Etching In semiconductor technology, a large variety of deposition and etching processes is employed. Deposition processes differ among others in terms of the properties of the deposited layers and the layer conformality. The latter for instance critically influences the filling of contact holes and trenches. Micromachines 2019, 10, 6 8 of 16 Etching processes differ, e.g., in terms of selectivity concerning the materials to be etched, etchinduced damage, and the degree of isotropy and anisotropy. Equipment simulation tools such as CFD-ACE+ [25] and Q-VT [26], which model the electrical, thermal, fluid-dynamical, and plasma etching rates across the wafer. Furthermore, non-vertical incidence of contributing species can lead to properties of the reactor can be used to predict the fluxes and energies of different species (ions, layout-dependent deposition or etching rates, as discussed above for the SADP process. An overview neutrals) above the flat or patterned wafer. Using these as boundary conditions, feature-scale of sources of variability intodeposition and etching processes is given elsewhere [1]. To this end, simulation allows one simulate the evolving geometry during deposition or etching. DEP3D and ANETCH allow the simulation of these deposition and etching processes, provided the interaction of the different species with the substrate is considered and local values of the different that physical/chemical models suitable for the process in question have been implemented, parameters fluxes are extracted which allow one to determine local etching or deposition rates. Examples for this have approach been calibrated, thefor required boundary conditions above the wafer of are known, e.g., from are givenand in [27] deposition and in [28] for etching. The discussion the large variety of deposition and etching beyond scope of this paper.of three-dimensional simulations equipment simulation. As an processes example,isFigure 9 the shows cross-sections Deposition and process etching for processes are subject to several sourcesof of variability. of a contact hole etching two different angular distributions thesystematic rate determining species: Depending on the process in question, these include the inhomogeneity of gas flow and temperature Figure 9a shows the result for purely physical sputter etching with a highly directional ion flux, in the etching or deposition reactor, the non-homogeneous emission of metal atoms, e.g., from a Figure 9b depicts the result for chemical dry etching, that is, for an isotropic angular distribution sputter target, or the finite size of a sputter target. These sources lead to variations of deposition and of the etching species. Figure 10 shows simulation results for long-throw sputter deposition into a etching rates across the wafer. Furthermore, non-vertical incidence of contributing species can lead contact structure fordeposition different positions the wafer. The asymmetry of the deposited to hole layout-dependent or etchingon rates, as discussed above for the SADP process. layer An for the off-axis positions of the contact hole is clearly visible. overview of sources of variability in deposition and etching processes is given elsewhere [1].
x (µm) (a)
x (µm) (b)
Micromachines 2018, 9,9.x Example FORfor PEER REVIEW 9 of 17 Figure for the simulation of contact hole etching: (a) sputter with highly Figure 9. Example the simulation of contact hole etching: (a) sputter etchingetching with highly directional directional ion flux; (b) chemical dry etching with an isotropic angular distribution of the etching ion flux; (b) chemical dry etching with an isotropic angular distribution of the etching species. species. material to(for be etched (for instance isinshown in dark red. The mask which is of the deposition into a The contact hole structure for different positions the wafer. The asymmetry The material to be etched instance oxide) is oxide) shown darkon red. The mask which is assumed be not affectedpositions by the etching process is depicted in clearly yellow. visible. deposited assumed layer fortothe off-axis of the contact hole is
to be not affected by the etching process is depicted in yellow.
DEP3D and ANETCH allow the simulation of these deposition and etching processes, provided that physical/chemical models suitable for the process in question have been implemented, parameters have been calibrated, and the required boundary conditions above the wafer are known, e.g., from equipment simulation. As an example, Figure 9 shows cross-sections of three-dimensional simulations of a contact hole etching process for two different angular distributions of the rate determining species: Figure 9a shows the result for purely physical sputter etching with a highly directional ion flux, Figure 9b depicts the result for chemical dry etching, that is, for an isotropic angular distribution of the etching species. Figure 10 shows simulation results for long-throw sputter
Figure 10. Example for the simulation of long-throw sputter deposition into a contact hole structure Figure 10. Example for the simulation of long-throw sputter deposition into a contact hole structure for different positions on the wafer. Ballistic transport of the metal atoms in the reactor is assumed, for different positions on the wafer. Ballistic transport of the metal atoms in the reactor is assumed, the target diameter and the distance between target and substrate were set to 300 mm and 150 mm, the target diameter and the distance between target and substrate were set to 300 mm and 150 mm, respectively. The step coverage (= ratio of the thickness at the sidewall bottom to the thickness on top) respectively. The step coverage (= ratio of the thickness at the sidewall bottom to the thickness on top) for the feature position at the center, 50 mm off-center, and 100 mm off-center is here given for sidewall for the feature position at the center, 50 mm off-center, and 100 mm off-center is here given for left | sidewall right: 0.16 | 0.16, 0.16 | 0.12, and 0.20| 0.05, respectively. sidewall left | sidewall right: 0.16 | 0.16, 0.16 | 0.12, and 0.20| 0.05, respectively.
3.1.3. Integrated Topography Simulation As outlined above, advanced nanoscale devices generally employ truly three-dimensional geometries. Furthermore, the approximation of these structures using rectangular shapes is no more
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3.1.3. Integrated Topography Simulation As outlined above, advanced nanoscale devices generally employ truly three-dimensional geometries. Furthermore, the approximation of these structures using rectangular shapes is no more possible, because the electrical performance depends on details, such as taper angles of FinFETs or corner rounding. Moreover, as discussed above already basic features such as line width depend on the three-dimensional interim structures generated during the patterning flow, e.g., in the form of non-vertical and/or non-straight resist edges. In turn, one of the key tasks in the SUPERAID7 project has been the development of an integrated three-dimensional topography simulator, which combines Dr.LiTHO [15], ANETCH [16], DEP3D [17], which all output a triangle-based surface representation, and the level-set based etching and deposition simulator ViennaTS [18]. To this end, DEP3D and ANETCH have been seamlessly integrated into the Python [29] simulation framework of Dr.LITHO. The ViennaTS level-set-method-based tool has been exposed to the Python programming language to allow the usage as a Python module. A common geometry conversion engine has been developed to handle the different data representations used in the tools, including surface and volume meshes, structured and unstructured grids. The physical models from DEP3D, ANETCH and ViennaTS are available in the integrated topography simulator and enable the simulation of a large variety of deposition and etching processes. Figure 11 shows the architecture of the integrated topography simulator. Micromachines 2018, 9, x FOR PEER REVIEW 10 of 17
Figure 11. Integrated 3D topography simulation, combining Dr.LiTHO, DEP3D, ANETCH, and Figure 11. Integrated 3D topography simulation, combining Dr.LiTHO, DEP3D, ANETCH, and ViennaTS. ViennaTS.
Figure 12 depicts an example for the combined simulation of lithography and etching: As layout, 12 depicts an example for the combined simulation of lithography and etching: As layout, an SRAMFigure cell pattern on polysilicon level has been used. The lithography simulation was performed an SRAM cell pattern on polysilicon level has been used. The lithography simulation was performed with Dr.LiTHO assuming 193 nm water immersion with a strong off-axis illumination and unpolarized with Dr.LiTHO assuming 193 nm water immersion with a strong off-axis illumination and light.unpolarized Dr.LiTHO provides the resist profile as a triangulated surface. To reduce the number of surface light. Dr.LiTHO provides the resist profile as a triangulated surface. To reduce the elements for the etching simulation, footprint of the resist was extracted, smoothed and the 3D number of surface elements for thethe etching simulation, the footprint of the resist was extracted, resistsmoothed region was generated with steep sidewalls. Figure 12a shows one polysilicon line forming and the 3D resist region was generated with steep sidewalls. Figure 12a shows one part of thepolysilicon SRAM layout. To study effect of layout. varying on the etchedparameters profile, it on is efficient line forming part the of the SRAM Toparameters study the effect of varying the etched profile, is efficient to simulate etching of a slice located at the position where, according to gate to simulate etchingit of a slice located at the position where, according to the SRAM layout, the the SRAM layout, the gate electrode above the active region. Thehave etching simulations electrode located is above the active located region.is The etching simulations been carried have out with been carried out with ANETCH using simulation coupling to thus equipment simulation allowing oneof to the study ANETCH using coupling to equipment allowing one to thus study the effect feature the effect of the feature position on the wafer. Details are provided elsewhere [28]. Briefly, an position on the wafer. Details are provided elsewhere [28]. Briefly, an inductively-coupled plasma inductively-coupled plasma reactor is simulated, which is operated at a pressure of 1.5 Pa and reactor is simulated, which is operated at a pressure of 1.5 Pa and powered with 1500 W, and the powered with 1500 W, and the substrate is biased with 200 V. Cross sections of the etched gate electrode for two different positions on the wafer are shown in Figure 12b and 12c respectively. It can be seen that the shape particularly at the foot of the gate electrode significantly depends on the position on the wafer.
polysilicon line forming part of the SRAM layout. To study the effect of varying parameters on the etched profile, it is efficient to simulate etching of a slice located at the position where, according to the SRAM layout, the gate electrode located is above the active region. The etching simulations have been carried out with ANETCH using coupling to equipment simulation thus allowing one to study the effect2019, of the Micromachines 10, 6 feature position on the wafer. Details are provided elsewhere [28]. Briefly, 10 of 16an inductively-coupled plasma reactor is simulated, which is operated at a pressure of 1.5 Pa and powered with 1500 W, and the substrate is biased with 200 V. Cross sections of the etched gate substrate is biased 200 V.positions Cross sections the etched gate electrode positionsItoncan electrode for twowith different on theofwafer are shown in Figure for 12btwo anddifferent 12c respectively. thebewafer are shown in Figure 12b,c respectively. It can be seen that the shape particularly at the on footthe seen that the shape particularly at the foot of the gate electrode significantly depends of position the gate electrode significantly depends on the position on the wafer. on the wafer.
(a)
(b)
(c)
Figure 12. Coupled simulation of lithography and etching: (a) 3D simulation of the resist line geometry (yellow) above the polysilicon (purple); (b) simulated etched gate electrode for a position close to the center of the wafer (distance to center axis = 0.14 cm); (c) Simulated etched gate electrode for a position at the wafer rim (distance to center axis = 9.7 cm). The unit for the x axis in (b) and (c) is micron.
3.2. Integration with other Tools In terms of process simulation and systematic process variations, the SUPERAID7 project has focused on topography simulation and the variations affecting the topography processes lithography, etching, and deposition: These processes and variations raise new challenges especially for three-dimensional nanoscale transistors as addressed in SUPERAID7 and in this paper. For the simulation of the other process steps, especially ion implantation and dopant activation/diffusion, the well-established process simulator Sentaurus Process [13] has been used. To this end, results from SUPERAID7 topography simulation are transferred to Sentaurus Process via the DF-ISE file format of Synopsys. More specifically, the exported results are used by Sentaurus Process to update an initial structure by means of Boolean operations. Device simulation has been carried out with Sentaurus Device [13], and statistical device simulation with Garand of GSS (now belonging to Synopsys). To this end the SUPERAID7 topography simulation tools have been integrated with Sentaurus Process, the Sentaurus Workbench, and the statistical device simulator Garand. This overall hierarchical approach implemented in SUPERAID7 to simultaneously simulate the impact of systematic and stochastic variations on devices and circuits has been discussed elsewhere [30]. 3.3. Compact Model Extraction Because conventional compact models are not suitable for the three-dimensional devices as studied in SUPERAID7, a novel compact model (LETI-NSP) based on surface potential has been developed by CEA/Leti and used for the compact model extraction work in SUPERAID7. This model has among others been presented at IEDM 2016 [31]. Within SUPERAID7 the hierarchical approach developed at GSS (now Synopsys) to extract statistical compact models [8] has been used and extended. In the traditional approach illustrated in Figure 13 (without the red extension “and/or process parameters”), first a so-called “uniform” compact model is extracted from device simulations without taking process variations into account. Then, process corners are defined for the process results (e.g., channel length L and width W) generated by the systematic variations (e.g., focus F and dose D in a lithography step) to be considered. Following this, an extended compact model is extracted from device simulations at these process corners, using a
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first group of compact model parameters defined during this extraction. Finally, this compact model is further extended into a statistical compact model, extracted from statistical device simulations carried out at each of the process corners. This compact model then allows one to calculate for relevant electrical device data A (e.g., the threshold voltage or the leakage current) the probability distribution P(A,s) that certain values of A occur. This distribution depends on values s (e.g., L and W) of the process results generated by the systematic variations of process input (or equipment) data r (e.g., Micromachines 2018, 9, x FORinPEER 12 of are 17 F and D) considered the REVIEW study. In order to get the final distribution of A, process simulations carried out to calculate the dependence s(r) of the process results on the (equipment) parameter r. would be necessary to find the root cause of their dependence, and express this by relating them to The final distribution PA of the electrical device data is then given as: some (hidden) parameters which cause the (partial) correlation. Z Since one statistical variation may influence several process results (e.g., the channel length of PA = P(A,s(r)) · f(r) dr (1) one transistor and the channel width of another), s(r) is generally a matrix. This also allows the proper description of correlations, which arise in the case that an input parameter r influences more than one where f(r) is the probability distribution of the (equipment) parameter r, e.g., the distributions of focus (intermediate or final) result parameter. The same holds for P(A,s). F and dose D.
Figure13. 13.Extraction Extractionand andgeneration generationofof hierarchicalcompact compactmodel modelaware awareofofsystematic systematicand andstatistical statistical Figure hierarchical processvariations. variations. process
in general A is a vector, variouscorners electrical properties considered. As soon as InHere, examples studied earlier (e.g.,because in [8]), process referred to theare minimum and maximum more of than one variation occurs,affected also r isbya systematic vector. It should noted thatsuch in case of more values two or statistical three discrete parameters processbevariations, as channel than one statistical variation, the components of r should be statistically independent. Otherwise length and width, influenced among others by focus and dose variations in lithography. However,it would be necessary tonanoscale find the root cause systematic of their dependence, and express this by themtoto for three-dimensional devices process variations might notrelating only lead some (hidden) parameters which cause the (partial) correlation. variations of such discrete parameters, but also change the shape of the device, e.g., the channel cross Since one statisticalcan variation influencewith several results channel length of section. Such variations hardly may be described the process variation of just(e.g., onethe or two geometrical one transistor thethe channel width ofcompact another),model s(r) is generally a matrix. allows the proper parameters. In and turn, hierarchical extraction strategyThis hasalso been extended in description of correlations, which arise in the case that an input parameter r influences more than one SUPERAID7 as illustrated in Figure 13 (red text): The extended uniform compact model is not only (intermediate or final) result The same forbut P(A,s). based on process corners (e.g.,parameter. channel length and holds width), may also be based on the minimum In examples studied (e.g., in [8]), process corners referred (e.g., to thefocus minimum and maximum and maximum values of earlier statistically varying process parameters F and dose D in values of two or three discrete parameters affected by systematic process variations, such as lithography). In turn, compact model extraction is then not based only on the results of channel device length andbut width, among others by focusand and device dose variations in lithography. However, for simulation, alsoinfluenced on the result of coupled process simulation, needed in order to trace three-dimensional nanoscale devices systematic process variations might not only lead to variations the impact of the parameter r on the device properties. If the extended uniform compact model isof such discrete parameters, butprocess also change the shape of the device, (1) e.g.,will thesimplify channel to: cross section. Such based on statistically varying parameters r only, Equation variations can hardly be described with the variation of just one or two geometrical parameters. In turn, PA strategy = P(A,r)has · f(r) dr extended in SUPERAID7 as illustrated (2) the hierarchical compact model extraction been in Figure 13 (red text): Theboth extended uniform model is not only process based on process corners The mixed case where process cornerscompact s and statistically varying parameters r are (e.g., channel length and width), but may also be based on the minimum and maximum values used in the extraction of the extended compact model must be treated with some care, because onlyof
variables can be used in the compact model extraction which do not depend on each other and can therefore be treated independently. In turn, it must be differentiated between varying process parameters r1 which influence process corners s, and varying process parameters r2 which do not influence process corners s. The probability distribution of an electrical device performance parameter A is then given by
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statistically varying process parameters (e.g., focus F and dose D in lithography). In turn, compact model extraction is then not based only on the results of device simulation, but also on the result of coupled process and device simulation, needed in order to trace the impact of the parameter r on the device properties. If the extended uniform compact model is based on statistically varying process parameters r only, Equation (1) will simplify to: PA =
Z
P(A,r) · f(r) dr
(2)
The mixed case where both process corners s and statistically varying process parameters r are used in the extraction of the extended compact model must be treated with some care, because only variables can be used in the compact model extraction which do not depend on each other and can therefore be treated independently. In turn, it must be differentiated between varying process parameters r1 which influence process corners s, and varying process parameters r2 which do not influence process corners s. The probability distribution of an electrical device performance parameter A is then given by Z PA =
P(A,s(r1 ), r2 ) · f1 (r1 ) · f2 (r2 ) dr1 dr2
(3)
where f1 (r1 ) and f2 (r2 ) are the probability distributions of the varying process parameters r1 and r2 , respectively. The selection of the process corners and/or the varying process parameters to be considered in the extraction of the group I parameters (see Figure 13) depends on an a-priori assessment of the relevant variations. This assessment can be based on technological knowledge on which variations are most important, and/or on numerical simulation where each potentially relevant variation is considered alone. Then, the most relevant systematical variations are identified and used in the compact extraction process outlined above. Generally, several different systematic variations may influence a device. Tracing all their combinations in parallel through the full simulation of the process sequence would require far too much effort. In turn, suitable design-of-experiment approaches must be used to limit the number of simulation splits. A simple and efficient approach is to first disregard variations which are due to expert knowledge already known to have negligible impact. Next, the impact of the remaining variations should be considered one by one, to identify a small number of most important variations. These variations could then either be considered in parallel, or more refined design-of experiment techniques could be employed to skip some or several elements of the full matrix of simulation splits. 3.4. Example for Compact Model Extraction Figure 14 shows a TEM micrograph of a nanowire transistor investigated in the benchmarks carried out in the SUPERAID7 project. The process flow included among others the deposition of a sacrificial SiGe layer on top of an SOI substrate, plus an upper Si layer. Self-Aligned Double patterning was used to create Si/SiGe/Si fins, and optical lithography for gate patterning. For this device architecture and the process flow used, ten potentially relevant systematical variations were identified. Their relative impact on the transistor performance was studied with coupled process and device simulation. Among these parameters, the three most important ones were identified [30]: (1) The SiGe mole fraction xGe which influences the etching of the inner spacers; (2) the fin SADP deposition factor dsadp which gives the relative variation of the deposition thickness from the nominal thickness in the SADP spacer creation process; (3) the defocus FGate of the lithography step used to pattern the gate. Both for n-type NMOS and p-type PMOS MOSFETs, Fgate had the largest impact on both saturation current and leakage current. Coupled process and device simulation was then carried out for the process corners of these three statistical variations. Figure 15 shows as an example the impact of these variations on NMOS and PMOS, respectively. The horizontal axis shows the minimum, the nominal and the maximum value
combinations in parallel through the full simulation of the process sequence would require far too much effort. In turn, suitable design-of-experiment approaches must be used to limit the number of simulation splits. A simple and efficient approach is to first disregard variations which are due to expert knowledge already known to have negligible impact. Next, the impact of the remaining variations should be considered one by one, to identify a small number of most important variations. Micromachines 2019, 10, 6 13 of 16 These variations could then either be considered in parallel, or more refined design-of experiment techniques could be employed to skip some or several elements of the full matrix of simulation splits.
of the varying parameters. Except for the parameter studied for each of the curves, the parameters 3.3. Example for Compact Model Extraction have their nominal values. For instance, for the blue curve in Figure 15, xGe is varied whereas dsadp Figure shows a TEM micrograph of a nanowire transistor in the benchmarks and Fgate have14 their nominal values. The V-shape for the impact of investigated Fgate is an intrinsic feature of the carried outofinCD theon SUPERAID7 The process flow included among others deposition a dependence defocus in project. lithography, discussed above in connection with the Figure 2. For dof sadp a sacrificial SiGe layer on top of an was SOIassumed. substrate,Its plus an upper Si layer. smaller Self-Aligned Double technologically appropriate variation impact was, however, than the impact used to create Si/SiGe/Si and optical lithography for gate will patterning. For this of patterning numerical was discretization errors. In turn,fins, in further work, a larger variation be assumed here device architecture and the process flow used, ten potentially relevant systematical variations were for the extraction of the compact model, whereas the realistic value can and will then be introduced Their relative impact on the transistor performance was studied with coupled process and viaidentified. the probability distribution f(dsadp ) in Equation (2). Based on these variations, the extended device simulation. Among these parameters, the three most important ones were identified [30]: (1) compact model was extracted, using the Mystic [13] tool from Synopsys. Figure 16 shows as an The SiGe mole fraction xGe which influences the etching of the inner spacers; (2) the fin SADP example the comparison between the saturation current simulated by TCAD and the results from the deposition factor dsadp which gives the relative variation of the deposition thickness from the nominal extended compact model extracted. Further work includes among others the updated extraction of thickness in the SADP spacer creation process; (3) the defocus FGate of the lithography step used to the dependence on the variations of XGe and the final extraction of the statistical compact model, as pattern the gate. Both for n-type NMOS and p-type PMOS MOSFETs, Fgate had the largest impact on indicated in Figure 13. The result willcurrent. be reported elsewhere. both saturation current and leakage
(a)
(b)
Micromachines 2018, 9, x FORof PEER REVIEWtransistors Figure 14.Example Example ofnanowire nanowire transistors considered considered in Figure 14. in this this work: work: (a) (a)cross crosssection, section,including including14 of 17
identification Hf, andSiSilayers; layers;(b) (b)cut cutalong along source-drain source-drain direction, identification ofof Hf, Ti,Ti, and direction,with withSiN SiNinner innerspacers. spacers.
(a)
(b)
Figure extended compact compact model: model: Results Resultsfor forsaturation saturationcurrent currentofof Figure15. 15. Example Example for for extraction extraction of extended (a) (a) NMOS; (b) PMOS. Key: blue—x ; orange—d ; yellow—F . The horizontal axis shows the Ge; orange—dsadp sadp; yellow—Fgate . The horizontal axis shows the NMOS; (b) PMOS. blue—xGe gate minimum, minimum,the thenominal nominaland andthe themaximum maximumvalue valueofofthe thevarying varyingparameters. parameters.
Coupled process and device simulation was then carried out for the process corners of these three statistical variations. Figure 15 shows as an example the impact of these variations on NMOS and PMOS, respectively. The horizontal axis shows the minimum, the nominal and the maximum value of the varying parameters. Except for the parameter studied for each of the curves, the
then be introduced via the probability distribution f(dsadp) in Equation (2). Based on these variations, the extended compact model was extracted, using the Mystic [13] tool from Synopsys. Figure 16 shows as an example the comparison between the saturation current simulated by TCAD and the results from the extended compact model extracted. Further work includes among others the updated extraction of the10, dependence on the variations of XGe and the final extraction of the statistical compact Micromachines 2019, 6 14 of 16 model, as indicated in Figure 13. The result will be reported elsewhere.
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(a)
(b)
(c) Figure Figure16. 16.Example Examplefor forextraction extractionofofextended extendedcompact compactmodel: model:Comparison Comparisonbetween betweenresults results(a) (a)from from TCAD; (b) from the extended compact model for the saturation current (color scale in Ampere TCAD; (b) from the extended compact model for the saturation current (color scale in Ampereof ofaa nanowire nanowireNMOS; NMOS;(c) (c)relative relativeerror error(color (colorscale scaleinin%) %)ofofthe thecompact compactmodel modelcompared comparedwith withTCAD. TCAD.
4.4.Discussion Discussion Especially Especiallyfor forthree-dimensional three-dimensionalnanoscale nanoscaletransistors, transistors,the thedetails detailsof ofthe thegeometries geometriesgenerated generated during device fabrication are important both for the nominal device performance during device fabrication are important both for the nominal device performanceand andfor forits itsstability stability against systematic variations caused by process equipment and/or by layout effects. Other than against systematic variations caused by process equipment and/or by layout effects. Other thanfor for statistical stand-alone statistical statistical device devicesimulation, simulation,there thereisisa statisticalvariations variations which which can can be be simulated simulated with with stand-alone ahuge hugevariety varietyof of potential potential systematic systematic variations, variations, which which must must be be addressed addressed with withvarious variousequipment equipment simulation simulationtools toolsand andprocess processsimulation simulationmodules. modules. In Inturn, turn,ititisisindispensable indispensablefor foroptimized optimizeddevice device and to well well identify identify and andcharacterize characterizethe thesources sourcesofofsystematic systematic variability, and circuit circuit manufacturing manufacturing to variability, to to sort out those with the largest impact, depending on the device and circuit in question, and to sort out those with the largest impact, depending on the device and circuit in question, and to quantify joint impact on the product. The impacts of systematic and statistical quantifytheir their joint impact on final the nanoelectronic final nanoelectronic product. The impacts of systematic and variability must be simulated and minimized in parallel, by adapting process flows, but statistical variability must be simulated and minimized in parallel, by adapting processpotentially flows, but also device architectures even fabrication equipment. In this paper, a In holistic approach to use potentially also device and architectures and even fabrication equipment. this paper, a holistic coupled equipment, process and device simulation combined with the extraction of variation-aware approach to use coupled equipment, process and device simulation combined with the extraction of compact models compact has beenmodels presented with some examples. The examples. approach The is partly basedis variation-aware has together been presented together with some approach on well-established tools used in tools industry, on additional and extensions are partly based on well-established usedpartly in industry, partly onmodules additional modules and which extensions compatible to such standard frameworks. The suggestions made are intended to support industry in which are compatible to such standard frameworks. The suggestions made are intended to support their efforts to optimize the stability of their products against all kinds of process variations. industry in their efforts to optimize the stability of their products against all kinds of process
variations. Author Contributions: J.L. coordinated the acquisition of the funding and managed the overall SUPERAID7 research P.E. and J.L. E.B.coordinated carried out the and topography simulation. Author project. Contributions: the lithography acquisition of the funding and managedS.B. thedefined overall benchmarks SUPERAID7 and provided experimental data. F.K., A.B., and L.W. carried out benchmark simulations. J.L. wrote the paper, research project. P.E. and E.B. carried out the lithography and topography simulation. S.B. defined benchmarks with figures provided by all co-authors. All authors critically reviewed the manuscript. and provided experimental data. F.K., A.B., and L.W. carried out benchmark simulations. J.L. wrote the paper, with figures provided by all co-authors. All authors critically reviewed the manuscript. Funding: The research leading to these results has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 688101 SUPERAID7. Acknowledgments: The authors want to acknowledge the discussions with and the contributions of all members of the SUPERAID7 team at Fraunhofer IISB, CEA/Leti, University of Erlangen-Nuremberg, University of
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Funding: The research leading to these results has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 688101 SUPERAID7. Acknowledgments: The authors want to acknowledge the discussions with and the contributions of all members of the SUPERAID7 team at Fraunhofer IISB, CEA/Leti, University of Erlangen-Nuremberg, University of Glasgow, Synopsys and TU Wien, especially of the work package leaders A. Asenov and C. Millar who are not among the co-authors. Conflicts of Interest: The authors declare no conflict of interest.
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