Apr 16, 1986 - receiver delays and the inter-chip delay is illustrated in. Figure. 3.13. The delay is measured when the feedback select switch is in each of ...
J
JPL Publication 89-1 J
Product Assurance Technology for Procuring Reliable, Radiation-Hard, Custom LSI/VLSI Electronics Report for Period" October 1984 - September 1986 M. R. B. K.
G. Buehler A. Allen R. Blaes A. Hicks
G. A. Jennings Y.-S. Lin C. A. PiSa H. R. Sayah N. Zamani
Janua_
Prepared
1989
for
Defense Advanced Research Projects Agency, U.S. Department of Defense and
National Aeronautics and Space Administration by
Jet Propulsion Laboratory California Pasadena,
Institute
of Technology
California N 'L,-,'n2
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JPL Publication 89-1
Product Assurance Technology for Procuring Reliable, Radiation-Hard, Custom LSI/VLSI Electronics Report for Period" October 1984 - September M. G. Buehler R. A. Allen B. R. Blaes K. A. Hicks G. A. Jennings Y.-S. Lin C. A. PiSa H. R. Sayah N. Zamani
Janua_
Prepared
1989
for
Defense Advanced Research Projects Agency, U.S. Department of Defense and
National Aeronautics and Space Administration by
Jet Propulsion Laboratory California Pasadena,
Institute California
of Technology
1986
The
work
Laboratory, fense the
California
Advanced National
described Research Aeronautics
in this Institute
report
performed
of Technology,
Projects and
was
Space
Agency,
the
Administration.
and
by was
National
the
Jet
sponsored Security
Propulsion by the Agency,
Deand
Abstract In this chips
are
needed use.
effort,
advanced
described.
These
to qualify
This
work
specialists,
Their
custom
ICs
from
of test
chips
has
Satellite) The
Chip,
a test
technical
were
cause
failures
seven
versions
Development gate-oxide
of new
mechanisms
4.
time-dependent
run.
data
demonstrating
.
Two parts
chip
from
structures
from
Chips sufficient
1986. Radiation were performed
runs
of two
another
on Asymmetrical
of test
defects
a set Effects
structures
used
In addition,
are
In the
testing
most
likely
reporting
techniques and
that
are
to
period,
for measuring
propagation
used
and
extraction
delay.
to evaluate
contact
failure
electromigration
were
Strips
on
for the
shipped
the
second structure
requirements
the
run
on
the
Cells
iii
Chip
CRRES
Dose
CRRES
wafer
(for example,
CRRES
to the
Integrated
one
sites
for evaluating
test
to characterize
of drop-in
SRAM
procedures
wafer-level
data
runs
papers:
Chip,
prepared.
Chips
Test
number
tests (Total on these parts.
7. Publication
a series
effects.
defects.
capacitance,
to analyze
fabrication
de-
breakdown.
and
that
these
which
been
parameter
used
dedicated
a set
interconnect
was
parts
Radiation
radiation
circuits.
and
of Reliability
space
include:
contains
gate-overlap
a limited
space
for (IC)
goal
a Fault and
process-induced
have
dielectric
of Test
This
acquired
that
Strip,
data
for obtaining
of this
Release
effort
fabricated
of MOSFET characteristics.
Evaluation
Test
(Combined
in CMOS/Bulk:
Development subthreshold ,
test
of a set
In pursuit
to determine
fault
capacitance,
Development
fault-tolerant-circuit technology
of various
developed
(ASICs)
the
a Parametric
in concurrently of the
Circuits
test the
of integrated-circuit
foundries.
Chip
in acquiring
and
of this
density
to be used
effort
for monitoring
of a Fault the
procedures
and
circuit
microelectronic
engineers,
CRRES
accomplishments
to evaluate
.
the
use
on developing
silicon
developed: and
that
Integrated
test-chip focused
CMOS/bulk
1. Development
2.
Specific
were
been
intended
the collaborative
physicists,
Chips,
methods
are
Application
efforts
of Reliability
chips
represents
device
signers.
measurement
and
Split-Cross for Single-Event
could
be
nine).
flight
parts.
program Single
wafer
Flight
in March, Event
Bridge Upset
Upset)
Resistor Analysis.
and
Acknowledgements The present address of C. A. Pifia is University of Southern formation Sciences Institute, Marina del Rey, California and the of G. A. Jennings
is Department
of Computer
Engineering,
California/Inpresent address
University
of Lund,
Sweden.
PRECEDING
PAGE
BLANK
NOT
FILMED
PAGE,,iV
INTENTf0NAH.T BLANK
Contents
1
Introduction
2
Test 2.1
Chip
1 Sets
2.2
Fault 2.2.1
Test 3.1
..............................
Test Chip Abstract
6
............................ ............................
10 10
2.2.2
Introduction
2.2.3
Fault
2.2.4
Pinhole
2.2.5
Comb/Serpentine/Cross-Bridge Contact Chain and Contact
2.2.6
3
5
Introduction
.........................
Chip
Organization
Array
Capacitor
2.2.7
Floating
2.2.8
Matrixed
Inverters
2.2.9
Matrixed
Transistors
2.2.10
Fault
Chip
2.2.11
Fault
Prioritization
2.2.12
Circuit
2.2.13
Fault
2.2.14
Future
2.2.15
Conclusion
Gate
...................
16
40
Results
41
Process
Testing
................ ................. due
to Gate
......................
.........................
Oxide
Pinholes
.
48 50 51
..........................
Capacitors
57
........................
Introduction Theory
3.1.3
Capacitor
3.1.4
Measurement
3.1.5
Equipment
3.1.6
Results
BLANK
46
59
Oxide
3.1.2
PAGE
32 40
Structures Gate 3.1.1
20 25
..................
Degradation
Work
Resistor .......... Chain Matrix .........
.....................
NOT
60
.........................
60
............................ Structure
60
Design
Techniques
................. ..................
.......................... and
Conclusions
FILMED
61 64 68
................... vii
PRECEDING
12
......................
Summary
Chip
...................
Transistors
Timing
10
72
CONTENTS
..°
VIII
3.2
3.3
3.4 4
Sampler Array ........................ Introduction .........................
3.2.2
Direct
Measurement
3.2.3
Muller
C-Element
3.2.4 3.2.5
Data Analysis ......................... Conclusions ..........................
Proximity
Structures
3.3.1
Introduction
3.3.2
Structure
3.3.3 3.3.4
Experimental Conclusions
The
4.3
4.4
4.5 Device 5.1
5.2
73
..........
79 85 90 90
.........................
90
.....................
90 92 92
...................
94
Structures ..............................
Electromigration
Layer 4.2.1
Electromigration Test Structures
.......................
Methods
Contact 4.3.1
Electromigration Test Structure
4.3.2
Test
Structure
4.4.2
Test
Method
4.4.3
Analysis
and
Introduction
5.1.2
Subthreshold
5.1.3 5.1.4
Parameter Results
5.1.5
Conclusions Circuit
5.2.2
Progress
Breakdown
...............
110 110 110
.......................
and
Future
112
Work
...............
116
Simulation
5.1.1
Objectives
ll0
.........................
Subthreshold
5.2.1
108 108
........................
Method
117
Parameter
Extraction
...........
......................... Expression
...................
123 ...............
128 129
.......................... on the
135 Hypercube
........................... and
Results
118 118
Extraction Algorithms ............................
Simulation
104
108
.........................
of Results
.....
104 104
...................... ........................
Dielectric
Test
(TDDB)
.........................
Method
4.4.1
104
Breakdown
........................ ........................
Test
Time-Dependent
103 104
Dielectric
4.2.2
Integrated
...........
Sampler
.........................
Resistor
Time-Dependent
Models
Delays
Results .................... ..........................
4.1.2
MOSFET
of Circuit
Geometry
4.1.1
Summary
72 72
as a Timing
Split-Cross-Bridge
Reliability Test 4.1 Introduction
4.2
5
Timing 3.2.1
.....................
.........
135 135 136
CONTENTS
ix
5.2.3
6
7
5.2.4
Significance Personnel
of the Results ...........................
5.2.5
Publications
..........................
..................
136 137 137 139
A Test Ch'p Case Study 6.1 Introduction .............................. 6.2
Areas
6.3
Test
6.4
Geometry
6.5
Wafer
6.6
Test
6.7 6.8
of Investigation Chip
........................
and
Test
Strip
and
Test
Program
and
Disposition
Probing Strip
140
Design
140 ..................
Generation
..............
144
of Data
..............
146
Wafer
Map
Parametric
Test
Strip
Wafer
Map
Comparisons
6.9
Mean
Value
Comparisons
......................
6.10
Mean
Value
Comparisons:
Summary
6.11
Wafer
Maps
Purpose
7.3
CRRES SRAM
7.4 7.5 7.6 7.7
Preliminary Probing
Results
.............
147
...................
147
.......................
158 161 Results
...........
161
..............................
165 171
CRRES Project 7.1 Introduction 7.2
144
..............................
172
................................
172
Chip Description .................................
......................
172 182
1986 NSREC Paper ......................... MOSFET Matrix ...........................
190 195
Timing 7.7.1
Sampler ............................ Test Hardware and Measurement
197 204
7.7.2
Data
7.7.3
Conclusions
7.8
Conclusions
7.9
Future
7.10
CRRES
Bibliography
and
Results
Procedure
.......................
205
..........................
210
..............................
Work Chip
213
............................. Test
Configuration
........
213 Pin
Outs
.............
214 223
List
of
Figures
2.1
Fault
2.2 2.3 2.4
Two
2.5
P-PAC
test
results
for run
M44E,
wafer
4
2.5
P-PAC
test
results
for run
M44E,
wafer
4 (Continued)
2.6
N-PAC
test
results
for run
M44E,
wafer
4
2.6
N-PAC
test
results
for run
M44E,
wafer
4 (Continued)
2.7
First-Layer
Metal
2.8
Schematic
diagram
2.9
Run
2.10
Contact
Chain
Structure
2.11
Contact
Chain
Matrix
Structure
2.12
Contact
Chain
Matrix
Structure
2.13
Contact
resistance
2.14
M62Z
2.15
Floating
2.16
Test
2.17
Floating-Gate
2.18
Run
2.19
Experimental the conduction
2.20
Chip
No.
5
...........................
13
Fault
Chip
No.
7
............................
15
Gate
Oxide
origin
17
defect
types
of Pinhole
M61P
Poly
contact gate
setup
Array
Capacitor
of the
transistor
21
Two types Transistor
of the Matrix
2.22
SEM
Photos
2.23
Fault
prioritization
2.24
Fault
models
2.25
Circuit configuration n-channel transistors
22 23
......
24
Resistor test
26
.......
27
results
.
28
models
floating
.............
(Schematic) analysis
analysis gate
29
Metal
process
for n- and
32
contacts
....
33
...................
transistors
34
...............
35
.................... gate
36
transistor
analysis
.......
37
overlap length variations transistor ..........
Serpentine
on 39
............ showing
a wire
40 43 break
.....................
p-channel
xi
. .
44 48
devices
and timing table .........................
FILMED
31
..........
p+Poly/Metal
of the gate poly of the n-channel
of M61P
30
...........
method
faulted inverter structure test circuit ....................
NOT
.......
.............
Resistor
(Layout)
analysis
results state
18
.......................
probability
n-channel
.....
.............
Comb/Serpentine
probability
device
PAGE BLANK
structures
Comb/Serpentine/Cross-Bridge
2.21
PRECEDING
(PAC)
Comb/Serpentine/Cross-Bridge
for floating
M61P
.......................
used
............. for simulating
51 faulty 52
LIST
xii 2.26
Circuit
configuration
p-channel 2.27
and
transistors
Change
oxide
delay
pinhole
Automated
2.29
Slotted-chuck
chip
3.1
The
Annular
MOSFET
3.2
The
Racetrack
3.3
Schematic
3.4
Cross
wafer
Inversion
3.6
Gate sured
and
holder
data
test
capacitor
to a MOSFET
3.8
of capacitance measurement The accumulation method
3.9
Error
in the
by using
Timing
sampler
3.12
Differential
3.13
Measuring
inter-chip
3.14
Two-input
Muller
3.15
Positive
3.16
CMOS
3.17
Restoring
3.18
Block
delay
the
diagram
delay
level
the
latch
Timing
Timing
3.23 3.24
Timing sampler fitted data ..................... Collision Test Structures .......................
4.1
The
4.2
Cross
4.3
Electromigration
electromigration section
inverter
of the
structure
76 .......
77 80 ....
81
structure
. . .
............ data
element
85 ..........
86
........
86
...........
87 89 91
................. second
83 84
a tau model
electromigration and
a staticizer
..............
pair
using chain
first
.........
82 with
Array
inverter
calculations
test
of part
74
a C-Element
Array
3.22
Sampler
69 70
71
..................
CMOS
array
..........
sampler
C-Element
3.21
sampler
Co_ .
measurement
sampler
using
Sampler
as-measured delay
capacitance,
78
as a timing
One
circuit
method
......................
measurement
Timing
mea-
............
timing
Timing
of the
67
.................
3.20
sampler
oxide
paths
3.19
stage
....
n-MOSFET
accumulation
measurement
of the
65
method
curve
capacitance
with
C-Element of the
inversion
. .
68
measurement
C-Element
logic
the
annular
probe/matrix
delay
dynamic
an
accumulation
measurement
transition
64
66
..................... for measuring
to delay
delay
63
capacitance
n-MOSFET
to perform
different
approach
56
......................
Connections
3.11
using
55
.........
for measuring
while
system .......
..........
structure
Capacitance-Voltage
introduced
due
acquisition testing
structure
test
method
capacitance
transistors
54 chip
capacitor
3.7
Traditional
p-channel
parametric
Capacitance-Length plot for in inversion ...........................
method
faulty 53
for automated
inversion
method
3.10
for simulating
...................
of an n-MOSFET
for measuring 3.5
prober
MOSFET
section
used
of n- and
resistance
2.28
of the
table
.........................
in propagation
to gate
timing
OF FIGURES
105 test
structure
metal
layers
.... .....
105 107
LIST
xiii
OF FIGURES
4.4
The
metal-n-t-diffusion
4.5
The
time-dependent
5.1 5.2
The The
p-MOS n-MOS
5.3
Subthreshold
5.4
¢2 > ¢1 ................................ Subthreshold characteristics
5.5
¢2 > ¢1 ................................ The model of an n-MOSFET tance
contact
electromigration
dielectric
reference reference
case case
breakdown
test
structure
structure
.
........
lll
...................... ......................
characteristics
118 119
for a p-MOSFET
at radiation
levels
for an n-MOSFET
at radiation
levels
120 121 where
the
drain
and
source
resis-
is R ...............................
Charge
5.7
formly doped n-MOSFET ...................... MOSFET drain characteristics for VDS
= 5.0V
.........
124 133
5.8
MOSFET
drain
for VDS
= 0.05V
.........
134
6.1
Four-inch
diameter
from
VTI-2
.........
141
6.2
Map
of the
6.3
Test
Chip
6.4 6.5
wafer maps and maps
and
metal
Chip _
wafer 10
Chip
electric
potentials
run
for
a uni-
.......................
sheet
VTI
for
resistance
from
for the from
142
sheet
the
VTI
and
2, Wafer
resistance
2, Wafer
and
#10
contact
linewidths #10
of
.....
linewidths
166 of
..........
resistances
167
from
VTI2,
voltage,
VTO,
..............................
wafer
conduction
maps
Chip
wafer
7.1
The
JPL
7.2
The
CRRES
Satellite
7.3
JPL
CRRES
chip
7.4 7.5
The JPL Transistor
7.6
Geometry
7.7
JPL
7.8 7.9
Design errors Encroachment
KP,
maps
CRRES
168
for the
factor,
Test
7.10
wafer
for the
maps
6.7
matrix
and
p-t-diffusion
wafer
Test and
VTI-2 wafer
Chip
Wafer 6.6
silicon
n+poly
Test
field,
characteristics
n+diffusion
Test the
electric
122
5.6
the
density,
109
transistor for n- and
for the
Chip
inverter
threshold p-channel VINV
and
MOSFETs...
169
Gain
170
......
........................
173
.........................
SRAM
logic
175
diagram
..............
177
CRRES Chip MOSFET Matrix ............. locations in the MOSFET matrix ............ of cells
CRRES
decoder
Chip
in MOSFET Timing
Matrix
Sampler
...............
Circuit
Expansion of the p-well cell ...................................
180
............
in the 4 kbit SRAM cell ............... of the p-well into the p+diffusion circuitry
178 179 181 182
in the
transistor
....................... around
design
183 boundaries
in the
SRAM 184
xiv
LIST
OF
FIG URES
7.11
Voiding
in the
interlevel
7.12
Circuit
diagram
of one
7.13
Symmetrical
7.14
Asymmetrical
7.15
Transistor
7.16
Pre-
7.17
CRRES
7.18
Threshold
7.19
Timing
7.20
Apparatus
7.21
Timing
7.22
Positive
7.23
Wafer
map
average
inverter-pair
delay
for positive
edges
7.24
(Wafer Wafer
4) ............................... map of the average
inverter-pair
delay
for negative
edges
7.25
Test
specifications
for the
JPL
CRRES
Chip
SRAM
7.26
Test
specifications
for the
JPL
CRRES
Chip
Timing
7.27
Test
specifications
for the
JPL
CRRES
Chip
MOSFET
leakage
voltage analysis
edge
4)
upset
for the
inverter-pair inverter-pair
dose chip
JPL
186
......
188
......
189
array
curves
.......
198 199
p-channel
timing chip
data
data
196
...............
CRRES
delta
response
MEP
...............
for n- and
CRRES
on the
response
MOSFET
total
dose
Chips
ion upset
n-channel
versus
of the
ion
heavy
versus
185
CRRES
configuration
for measuring sampler
heavy
lk SRAM
post-irradiation Chip
....................
of JPL
lk SRAM
cell,
measurement
and
(Wafer
cell,
oxide pair
MOSFETs
sampler timing
203
.......
204
sampler
. . . 206
..............
from
one
chip
207 ........
208 211
...............................
212 ....... Sampler Matrix
216 .
218 220
List
of Tables
2.1
Critical
parameters
2.1
Critical
parameters
2.2
Abbreviations
2.3
The
Fault
2.4
Test
structures
2.5
Test
structures
2.6
Pinhole
Array
Capacitor
defect
classes
2.7
Pinhole
Array
Capacitor
defect
identification
2.8
Fault
Chip
Report
1
.........................
42
2.9
Fault
Chip
Report
2
.........................
45
2.10
Fault
Chip
Report
3
.........................
47
2.11
Example
2.12
Priority
3.1
Results
3.2
Diode
3.3
Design
4.1
The
4.2
Dimensions
4.3
Examples
used Chip
4.3
Results
5.1
Individual MOSFETs
5.2
Individual parameters
test
parametric
structures
structures
(Continued).
test
and
structures
associated
7 8
.......
parameters
9 ....
12
No.
5
................
14
for Fault
Chip
No.
7
................
16
...............
19 ...........
20
............................
tests
49
defects
of Round voltages
indicated
for the
of various
by Collision
of modeled
Wires
for
circuit
50 72
Test
Test
Structures
Test
Chip
step-stress
Structures
.
93
...........
106 Structure
oxide
.
data
(continued) from
analysis
MOSFET
113 for
the
step-stress
oxide
breakdown
....................... of the
data
parameters
114
in Table based
4.3
...........
on individually
115 fitting
four
............................. MOSFET given
130
parameters
in Table
106
breakdown
.............................. of modeled
92
........
Electromigration
the
......
.............. Collision
in Layer
data
example
MOSFETs
Electromigration
of Metal
experiment 4.4
associated
.........
Chip
Interconnect
Examples
and
for the
structures
for Fault
breakdown
experiment
test
of likely
from
rules
associated
test
circuit listing
and
5.3
derived ....................
XV
from
the
global
FET 131
LIST
xvi 5.3
Global
MOSFET
parameters
6.1
Transistor
6.2
Metal
to n+poly
contact
6.3
Metal
layer
resistance
6.4
"Full"
Wafer
6.5
"Avenue"
Wafer
6.6
Test
Strip
ST5102
results
6.6
Test
Strip
ST5102
results
7.1
Summary
7.2
JPL
7.3
Chip
7.4
CRRES
7.5 7.6
Comparison n-MOSFET
of n-MOSFET Matrix Co-60
Matrix radiation
7.7
p-MOSFET
Matrix
radiation
test
7.8
Summarized
data
timing
samplers
Geometries sheet Map:
....................
Map:
Chip
placement Chip
histogram
Metal
...........
148
............... contact
to n+Poly
149
resistance
contact
......
resistance
150 ....
...................... (Continued)
to the dose
Irradiation
Co-60 the
151 154
................
Projects
expected
Cobalt-60
from
histogram
to n+Poly
deliveries
and
145
resistance
Metal
TABLES
132
........................
of CRRES/MOSIS
CRRES
OF
155
as of March, CRRES rate
1987
program
for the
MEP
.....
176
.......
180
.......
187
.................
196
Test Results test results results
.......... ..........
200 201
..........
202
on four
wafers
....
209
Chapter Introduction
1
2
CHAPTER
The
goal of this effort
low the silicon
foundries
The
use
widespread being
of test
chips are
report
acterize
and
three
evaluate
test
analyze
initial
identify
the
the
defect
the
Release effect
Radiation on
chips
as a means
of
promises
to
Circuits
failure
the
defect
CRRES
basis
for
strip
used
to
type,
Chip
The
to
used
to
(Com-
in the early chips
the
and
CRRES
12 JPL-designed This
Chip
reliability
will be launched
contains the
common the
test
to characterize
Fault
long-time and
to char-
on one
used
the
to radiation.
Satellite)
form
Strip
most
modes,
fabrication
(MEP)
Technology
is based
Test
expected
microelectronics.
methodology
test
Integrated
parameters,
the
Effects
which
Monitor
SPICE to identify
of the
system
is
reliability
approach
Assurance
runs
Process
and
Package
test
Product
to characterize
of radiation
associated
CMOS
customers
Currently,
This
from
as spacecraft.
and
Application-Specific
foundry
long-time
Its Microelectronics the
process.
will al-
manner.
to extract
response
and
standards
CMOS
density
used
expected
characterize
a
and
Chip
military
cost-effective
particular
chips:
parameters
Reliability
and
describes
process
acceptance.
and
such
for quantifying
for wafer
in the
of custom
in a timely
This
a basis
that circuits
manufacturers control,
UCTION
LSI/VLSI
applications
circuit
for process
of a manufacturing
qualification
(ASICs)
bined
by integrated
INTROD
methodology
custom
use in critical
essential for use
quality
assurance
radiation-hard,
their
for providing
the
the
and
permit
contemplated
evaluating allow
and
and
a product
of reliable,
for they
parameters, are
is to develop
procurement
I.
1990s.
to analyze
family
of structures
integrated
circuit
and
the
qualification
procedures. One dures and
key element
to determine outlier
wafer
sample
exclusion
which
veloped smaller
size
test
area
than
and
that
frequency,
needed
incorporating
in order
and
Another data
base.
values
with
key element This those
on target
and
As part
of this
allows
errors
measured
if the
process
effort,
probed
test
in predicting
time is the
to compare
parameter
on previous
runs,
tolerances chips
on
types
contacts.
addressing,
used an
and
to decide
to characterize
entire
3-#m
effort
of a
we de-
allows
using
the
a much "smart"
individual must
ac-
Dielectric be ana-
values.
establishment and
area
This
allows
to failure
mean
functions,
which
study of the Time-Dependent 1600 or more test structures
in this methodology one
different
proce-
limited
of this
resistance
of four
column
distribution to the
As part
contact
for individually row
to minimize
due
structures.
contacts
of statistical
parameter
to measure
of 464
development
is important
for use for test
cess to all 464 contacts. Simulation Breakdown Structure revealed that lyzed
is the
This
structure
characterization
structure,
methodology
methods.
is available
a special
statistical test
in this
of a parameter standard
deviation
if the parameters them
CMOS/Bulk
are
are
acceptable. p-Well
wafer
run were evaluated. For this particular run, the lot toleranceswere: for the gate linewidth, 0.18 jum, for the threshold voltage, 0.017mV, and for the conduction factor, 7 percent. From Cobalt 60 testing, the radiation damage factor was found to be about 32 mV/krad(Si). In our estimation, theseare excellent values for microelectronics intended for usein a natural spaceenvironment. A final element in this methodology is the development of innovative test structures that allow one to quickly measure key parameters. During this period three structures of note were developed: (a) the contact resistor matrix mentioned above, (b) the gate-oxide capacitor (round and race track versions) and (c) electromigration test structures (a 15-segmentedstructure for metal, and a 16-elementstring for contact evaluations). In order to "exercise" the product assurancetechnology,a chip was designed for the CRRES MEP and two dedicatedfoundry runs undertakenfor theseparts. On eachfoundry run ProcessMonitor Test Strips and drop-in Test Chips (containing a set of structures from the ProcessMonitor and the Fault Chip) were included alongsidethe CRRES Chips. From the secondrun, four 3-_m CMOS pWell wafers wereanalyzed in detail. Numerousparameters were mapped across the wafers and results obtained from nine drop-ins were compared with those from about 90 ProcessMonitors. This analysis led to the conclusion that nine sites placed in a 3 × 3 grid are sufficient to characterizethe wafer and to distinguish acceptablewafersfrom unacceptablewafersfor current CMOS processing. The reader is encouragedto study the following report. For those with questions, the technical staff of the VLSI TechnologyGroup is happy to discuss technical details and can be reachedat (818) 354-2083.
Chapter Test
PRECEDING
PAGE
2 Chip
BLANK
NOT
Sets
FILMED
PAGE
_
INTENTIgMAI_t_ BLANK
CHAPTER
6
2.1
TEST
CHIP
SETS
Introduction
As
a result
several tion
of the
years,
required
of this
effort,
Product
structures
to evaluate
custom
it has
become
for industrial
for a specific
application
families
of test
chip. rameter
set
Form
Chip In this
tions,
as well as those
These
parameters
though
the
types the
critical
parameters into
have
test
the
1. PROCESS stability
are
needed
and
the
following
proven
dopant
and
used
interlayer
of the
oxide
thickness,
contact
were
the
and/or
test
2.
and
final
[2] and
report
DEVICE from
test
circuits.
structures.
set. the
Al-
different
Table
2.1
used
structures scribed
methods
PARAMETERS. The as
device
inputs and
in the
test
used
The
first
described
The
parameters
used
parameters
are
elsewhere
to monitor variables
control
Some
of these
majority
simplest
parameters
to device
and
methods
used
previous
PAT
final
described
3.4 of this
of the same
such different quantities
provide
process
circuit
simulation
report
[2].
used these
previous
parameters
found
to determine
in the
as
PAT
report.
of these
device
the
of a manufacturing
process
linewidth
are
3.1 and
The
of the
lists
parameters.
2.2.
are
significant
resistances.
in Sections
measurements
MOSFET. are
the
JPL
or lot evalua-
are required as inputs by the level 2 and 3 SPICE MOSFET models in circuit and device simulation. The structures used to determine parameters
pa-
scheme:
those
some
using
wafer
to obtain
these
Intermediate
sets
morphologically
parameters
by measuring
determine
critical
required
which
These
from
CMOS
of devices
in Table
classification
a reliability
or deleted
designed the
general
the rule
the
is designed
and
in Caltech
twenty
explained
six categories
concentrations,
layers,
specially
less than
prepares three
chip
to perform
behavior
structures
PARAMETERS. that
the
to extract
are
to be a good
of a process
process
from
is large,
structure
chips design
needed
to model
determined
structures
for each
arranged [1] and
are
test
to cover
parameters
required
of which
be added
of these
conduct
developed
can
for different
informa-
each
a fault
past
the
that
chips,
the
In the
method
is adequate
descriptions
over
circuits.
we have
chip,
effort
to provide
VLSI
test
structures
generated
list of parameters
of test
symbols
test
Assembler (TCA). section we list the
developed
end,
test
composition
be easily
(PAT)
an efficient
To this
a parametric
their
can
that
use is to develop
[1]. Geometrical
(CIF)
has been
evident
individual
if necessary,
Technology
or semi-custom
or use.
chips:
Although
chips
Assurance
a set of test
methodology
Test
2.
are obtained
in MOS control
these
circuits:
the
information
and
programs. parameters
The are
test de-
2.1.
INTRODUCTION
Table
2.1:
Critical
parameters
and
associated
Parameters
Test
1. Process 1.1 Layer
Sheet
1.2 Layer
Linewidth
1.5 Substrate 1.6 Field
Abbreviation
XBR XBR,
Dopant
Oxide
1.8 Junction 1.9 Bulk
Density Voltage
Breakdown Lifetime
Gate
Oxide
Device
RO-TR
CAP, TR
TR
TR, DI PFPR
Voltage
Resistivity
Bulk
CAP,
ALI
Alignment
1.11
SXBR
CR, CR-ARR
Resistance
Threshold
1.10
DI, CAP CAP
Breakdown
Parameters
2.1 VTO
(Threshold
2.2 Gamma
(Conduction
2.4 WE
(Effective
2.6 Lambda 2.7 IDSO
Effect
Channel
(Channel
2.9 VDBBD CGSO
TR
Factor)
(Channel
2.8 IDBLEAK
TR
Factor) Width)
TR
Length)
TR
Channel
(Effective
TR
Voltage)
(Body
2.3 KP
2.10
Structure
Resistance
1.7 Layer-layer
2.5 LE
structures.
Parameters
1.3 Metal-Layer Contact 1.4 Oxide Thickness
.
test
Length
Modulation)
Leakage
2.11
CGBO
(Gate-Body
2.12
CGDO
(Gate-Drain
Leakage)
TR
Breakdown)
TR
Diode
(Source-Drain (Gate-Source
TR
Current)
(Source-Drain
Diode
Capacitance) Capacitance)
2.13
CJ
(Junction
2.14
MJ
(Exponential
2.15
CJSW
(Junction
2.16
MJSW
(CJSW
2.17
VPT
(Punch-through
2.18
VBG
(Gate-Oxide
Capacitance)
RTR-TR,
ROTR
RTR-TR,
ROTR
RTR-TR,
ROTR
RTR-DI-
Capacitance)
RTR-DI
Factor) Sidewall
TR
Capacitance)
RTR-DI
Factor)
RTR-DI
Exponential
TR
Voltage) Breakdown
Voltage)
CAP
8
CHAPTER
Table
2.1:
Critical
parameters
and
associated
Parameters
Test
3: Circuit
test
TEST
structures
Structure
CHIP
(Continued).
Abbreviation
Parameters
3.1 VH
(Inverter
VHIGH)
INV,
INV-ARR
3.2 VL
(Inverter
VLOW)
INV,
INV-ARR
3.3 VINV 3.4 GAIN
(Inverter (Inverter
3.5 VNM 3.6 Tau 4. Layout
(Inverter (Gate Rules
4.1 Layer
VIN -- VOUT) Gain)
INV,
INV-ARR
INV,
INV-ARR
Noise
INV,
Margin)
Delay)
Linewidth
4.4 Poly
Gate
Overlap
4.6 Active
Area
SXBR, CR Over
Field
Oxide
of Contact Overlap
Of Contact
5. Defect Density 5.1 Oxide Defects 5.2 Layer
TS
XBR
Extension
4.5 Metal
INV-ARR
RO,
4.2 Layer Spacing 4.3 Contact Size
6,
2.
TR,
CS
CR, CR
CS
CS
CAP-ARR
Bridging
CMB
5.3 Open Layer at Step 5.4 Contact Resistance
STP
5.5 Inverter
INV-ARR
CR,
Variability
CR-ARR
Reliability 6.1 Time-Dependent Dielectric 6.2 Radiation Hardness 6.3 Electromigration 6.4 Oxide Instabilities 6.5 Contact 6.6 Latch-Up
Reliability
Breakdown
TDDB RO-TR CR,
CMB
TR,
CAP
CR, CR-ARR LUTR
SETS
2.1.
INTRODUCTION
Table
.
2.2:
Abbreviations
ARR
Array
CAP CMB
Capacitor Comb structure
CS
Collision
CR
Contact
DI
Diode
INV
Inverter
LUTR
Latch-up
RO
Ring
RO-TR RTR
Round, Annular transistor Racetrack transistor
TDDB TR
Time dependent Transistor
TM
Timing
STP
Step
XBR
Cross-bridge
CIRCUIT
provide
for using
circuit
structures described
RULES.
important
to both
control, of
determine
a given
rules.
these
a given set
oscillator
dielectric
breakdown
sampler resistor
parameters,
information
simulation.
in Section
of layout
transistor
These
which in the
Typically
or a simple
to determine
LAYOUT
set
resistor
The
these
combination
circuit
designer or not
Although
parameters
of geometrical
and
circuit
a circuit
of simple to circuit
by
these
user.
The
test
to the
delay are
of inverters,
the
can
prime
can provide design
essential
of gate
parameters
and
provided
their
process
are
meadeter-
such
as a
gates may be design. The methods
used
report.
information
whether
manufacturing
parameters
3.2 of this
form
these
Other simple gates or combinations the timing information so essential
used
structures.
structure
timing
an inverter
ring oscillator. used to obtain
test
structure
PARAMETERS. designer,
mined
group
parametric
Structure
surements
.
for the
Abbreviations
circuit
are
used
The
is not
that
produce
structures
used
is in this
using
information
to consistently rules.
parameters
be designed
purpose
important
measurements a given
of process
on the devices
ability within
to determine
10
CHAPTER
these
parameters
of this
DENSITY.
circuit
yield.
expressed
The
in terms
pinholes,
parameters
structures
provide
faults
of structures
and
test
ters and
can be used to predict contact electromigration
reduce
circuit
Fault
Test
Chip
described
SETS
in Section
3.3
effort,
been
developed
the faults
a measurement
defect.
Defect
faults,
reduce
of defect
densities
metal
that
for gate
opens,
2.2 contains
density,
and
oxide
metal
step-
a discussion
of the
These
parameters or limit
life. Chapter time-dependent
five test
chips
were
characterize
the faults
life.
parame-
circuit
These
4 details the test for layer dielectric breakdown. developed.
Abstract Chip
has
CMOS/bulk
integrated
ing wafers, induced sity
in the
circuit
to proper
to characterize
(IC)
incomplete
by photolithographic
is essential
To this Poisson
processes.
These
and
patterning
of layers.
design,
removal
simulation,
and
end, the Fault Chip enables estimation distribution of defects. Defect densities of each
fault
type
geometry.
Fault
Chip
analysis
has
oxide
pinholes
of different has
defects
deposition
likelihood
also
resistive
2.2.2
faults enabled oxide
from the
for a specified
simulation
pinhole
defects
originate and
Knowledge
3-/_m
in start-
in the
of the
faults
defect
of integrated
den-
circuits.
of defect densities based can be used to determine
the
based
on the
circuit's
characterization
to contact
of timing
in the
of layers,
testing
circuit
enabled
found
resistance
degradation
on a the layout
of a number distributions.
of simple
gates
It
due
to a
fault.
Introduction goal
CMOS/bulk and
CHIP
methods.
circuit and
of this
A Fault
The
are
characterize
performance
course
2.2.1
used
Section
PARAMETERS.
either
2.2
per
bridging
can be determined.
that
In the
methods
These
integrity,
RELIABILITY
.
test
of elements
contact
coverage types
the
TEST
report.
DEFECT
.
and
2.
of this
process
to develop
predicting
effort
circuit
is to prioritize
before
suitable
test
degradation
stressing; circuits resulting
faults
found
to develop to verify from
in test
static the
structures
CMOS/bulk
correctness
physical
failures.
in a 3-#m fault
of the
models;
models
in
2.2.
FAULT
Our
TEST
approach
in a 3-/_m
has
Southern
be tested
developed,
Fault
meets
The
current
a stuck-at which
that
systematic
stuck-at
information
data
approach
bases
is taken
foundry
wafers
The
general
according
here
conducting metal, the
and
For
analysis
bad
in one
of accompanying the discovery those gate
that
The string
Chip the
approach,
encountering
mean
turned has
original which
also
off and
several
not
hundred
resistance, contact.
the
information individual spread
in the
silicon
which from
transistors thus,
are
floating-
turned
structure
integrity
design. a long
yield.
allows the
on.
was
on parametric and
in
are different
charge;
contacts,
metal
low yield resulted
of open-gated
in values,
section. between
the
diffusion
test
and
of broken with
pinholes
into
a layer
layout,
of oxide
contact
or
phenomena.
p-MOSFETs
insight
same
to distinguish
this
positive
are
grouped
in a later
number
analysis
Chip
process, design,
large
for evaluating provide
the
n-MOSFETs
a small new
between
noteworthy
floating-gate
provided
been
many
in n-type
on
Fault
have
detail
to correlate
A novel appear
tests.
the
The
able
first fault
reports.
single-metal
been
uses
a circuit is the
as they
on
region.
analysis
case,
to have
approach does
using contact
an open
tend
ac-
Further,
Chip
circuit
found
of faulty
[n another
gates are
Fault
of the
are terminated characteristics
failure
in greater
able
case,
fabrication
Traditionally,
structures
an abnormally were
wafer
wafer
Fault
a defect
observed
and
The defects.
field
test
we have
fully
foundry
or to ground.
integrated
have
chips
acquisition
fault
characterized
Chip,
and
p-MOSFETs.
from
or a bulk
In another
pinholes
floating
of contacts
current
Fault we saw
electrical
n-MOSFETs
For example,
tion
the
faults.
is discussed
coverage
circuits.
of faulty
showed
case
voltage
of such
four
of
When
on
CMOS/bulk
diffusion,
runs,
step
that
that
In a 3-#m
of the
with if a given
structures
first
data
is issued.
circuits
characterizes
structures
foundry
due to poor
implies
layers.
parametric
a hard
directly
test
the
a structure
of these
example,
wires
that
so the
of integrated
realistic
of the
Notice
poly-silicon,
of each
From
are
to establish
to whether
is either
good
derived
categories 2.3.
different testing
been
MOS
developed
introduces
the only
faults
the
University
simulation
nature
have
through
found
microcircuits.
supply
where
in order
in Table
are the
defects
Institute,
report
qualified
power
faults
to measure
and
in conjunction
approach
to the
was
for deciding
for fault
This
pulled
attempt
used basis
standard
chuck
prober
for space
approach.
monthly
Sciences
a summary
will be the
to characterize
is fabricated
wafer
requirements
is either
it is assumed
listed
Chip
Chip
wafer
is analyzed,
industry
fault
chip
A special
to form
the
a Fault
Information
automated
data
procedures
process
node
an
the
the
ceptance
This
(MOSIS),
(USC).
by
After
to develop
process.
Service
California
system.
11
been
fabrication
Implementation can
CHIP
The
determina-
probability
of
12
CHAPTER
Table
2.3:
The
Fault
Chip
Structure
structures
and
Parameter
Pinhole
Array
Different
Capacitor Comb
test
Layer
Pinhole
Resistor
Serpentine
Same
Resistor
Contact
Matrix
Inverter
Layer
Gap
Resistance
Same Wire
Layer Resistance
Vinv,
Matrix
Layer Resistance
Vhigh,
Vlow, Transistor
TEST
associated
and
Timing
2.2.3
Fault
The
Fault
field
oxides,
Figure
Element
Analysis
Transistor
Elements/Defect
Wire
Elements/Defect
Gap
Wire
Elements/Defect
Contact
Probability
Inverter
Open Contact Parameter
Gain Transistor
Operating Domain
Transistor
Initial
listed
the
in Table
The
objective
crossovers)
The versions Revision
requires
to acquire must
Fault
to date.
with
2: Cross-Bridge
fault
through
contacts from
Resistor
This
improves
were:
to the
p-PAC
gate added
to the
and
to Metal
contains No.
test
5 are
structure.
transistors because
defect
or metal the
number
densities
revisions
structure
substrate
and
in
structure.
by each
is difficult
and
As seen
Chip
in each
design
revisions
added
on a side,
(for example,
data.
in gate
layers.
on Fault
consumed
five major
design
the
of elements area
as pinholes
within
7.1mm
elements
as processing
major
injected
in the
such
shorts included
the number
enough
has gone
1: Substrate
and
approximately
meaningful
The
defects
opens
The structures
tradeoffs
increase
Chip
rent Revision
is square,
is to include
of elements lower.
and
structures.
2.4 along
design
Voltage
to characterize
integrity,
chip
of test
Gate
Organization
is designed
contact
of
Variability
and
Conduction State
Chip
Chip
2.1,
a number
The
Devices
SETS
parameters.
Different Layer Short Resistance Open-Gate
CHIP
Resistance
Different Contact
Matrix
2.
and
become
seven
to collect
through
Comb/Serpentine
oxide
major
the
cur-
defects.
Resistor
to
2.2.
FAULT
TEST
CHIP
13
Figure
2.1:
3-#m
CMOS/Bulk
Fault
MOSIS
test
strip
shown
top
at the
Chip of the
No. 5 (7.1mm chip.
by 7.1mm)
with
the
14
CHAPTER
Table
2.4:
Test
structures
Test Structure 1.n-Pinhole Array Capacitor
Element
Serpentine
Metal
Cross-Bridge
4.Poly
Comb
Poly
Resistor
Resistor
8.Open-Gate
(#m)
measure
the
Step
(6 #m)
18,450 1
Length
(#m)
326,472 18,300 1
Contact
160
Inverter
223
sheet
2,600 144
3: Poly Comb/Serpentine/Cross-Bridge information on the poly layer.
Revision
4: Contact Chain data
Revision
Figure of the
Matrix Matrix points
5: Floating transistors 2.2 shows revisions
the
structures
replaced Contact
in less silicon
area
than
arrays neighbor
latest
of the
above.
Fault
Structures
Chain individual
replaced effects. Chip,
included
width. added
by Contact
The
version
wire
resistor
gate transistor to eliminate
discussed
and
structures.
listed in Table 2.5. The most noteworthy No. 5 is that the number of contacts has No. 7. test
2
resistance
Revision
Subarrays
218,448
Inverters
locally
#
90,558
Length
Transistor Transistors
Devices
SETS
No. 5.
Elements
Step (9 #m) Cross-Bridge
Matrix
CHIP
90,558
Adj.
Adj.
Resistor
Matrix
7.Transistor
TEST
Cross-Bridge
Poly Cross-Bridge Resistor 5.Contact Chain Resistors •6.Inverter
#
Transistor
Resistor
Serpentine
Chip
Transistor
2.p-Pinhole Array Capacitor 3.Metal Comb Resistor Metal
for Fault
2.
by
No. on
to provide
Chain Matrix
and
fault
Contact
provides
more
floating
gate
contacts. isolated
7, which Fault
Chip
includes No.
all 7 are
change between Fault Chip No. 7 and increased from 160 on No. 5 to 920 on
In this discussion, a distinction is made between array-type and matrix-type structures. In array-type structures, a large number of elements are tested
simultaneously to assess whether a fault has occurred. In such structures, the parametric value of the fault can be characterized but the fault cannot be located
2.2.
FAULT
TEST
CHIP
15
DEVICES
Figure MOSIS
2.2: test
3-#m strip
CMOS/Bulk shown
at the
Fault top
Chip of the
No. 7 (7.1 mm chip.
by 7.1mm)
with
the
16
CHAPTER
Table
2.5:
Test
structures
for Fault
Element
#
Test Structure 1. Pinhole Array Capacitor
2.
Chip
TEST
CHIP
No. 7.
Elements
#
Subarrays
n-type
Transistor
77,454
4
p-type
Transistor
77,454
4
218,448
5
18,450
1
2. Metal
Comb/Serpentine/Cross-Bridge
Comb
Resistor
Serpentine
Resistor
Cross-Bridge 3. Poly
Resistor
Resistor
Adj.
Length
Step
(6 #m)
Resistor
1
7. Matrixed
Transistors
8. Open-Gate
Length
(_tm)
326,472
Step (9 #m) Cross-Bridge Matrix
Chain Resistors Inverters
array
category.
Contact
(3.0 #m)
464
Contact
(2.4 #m)
464
Contact Inverter
(3.0 #m)
32 223 2,600
Transistors
of each
for further
analysis.
In matrix-type element
in a matrix.
category.
In the
2.2.4
Pinhole
The
structures,
following
The
Array
Pinhole on-chip
Contact
sections
each
1 -
1
22
-
2
-
Inverters
in the
5
18,300
Transistor
Devices
-
Resistor
Adj.
Serpentine Resistor Cross-Bridge Resistor 4. Contact Chain Resistor
5. Contact 6. Matrixed
(#m)
Cross-Bridge
Comb/Serpentine/Cross-Bridge
Comb
SETS
Array
Capacitor
decoding
Chain
allows
Resistor
structure
from
falls
Matrix Table
into
this
characterization falls
into
this
2.3 is described.
Capacitor
Description The Pinhole Array Capacitor (PAC) described of the art in evaluating MOS device integrity. cap
separated
MOSFETs. diffusion
by deposited These
layers.
MOSFETs The
structure
oxide
from
are
elsewhere [3] represents The PAC consists
an underlying
formed
is arranged
two-dimensional
by orthogonally in four
intersecting
subarrays.
The
the state of a metal array gate number
of and of
2.2.
FAULT
elements ures
in each
2.5
oxide
TEST
and
defects.
The
The
oxide
growth gate
[4,5,6] oxide
are
pinholes the
Map gate
This
surface
residual and
silicon
gate
oxidation masks
nitride
results
the
to be against
the gate
in a thinning
phosphorous
material
1
process,
is believed
which
allows
shorts.
to be between
local
definition,
in Fig-
metal-poly
resistive
shorts
in a CMOS
given and
by simple
resistive
oxide
regions,
polycrystalline
modeled
silicon
2.3).
affected
Location
to characterize
of these
for gate at
(Figure
at the
phosphorous-doped
range
is used nitride
Defect
used
defects
gate
nitride
in the be
oxide the
of residual
of the
can
show
of the
silicon
oxide
is listed PAC
Metal-poly results
origin
formation
17
subarray
2.6.
Experimental and 100 k_. in which
CHIP
to dope
from the
the
silicon
n-
type.
NAKAJIMA
t
KOrOI
N,','R,o,= f\ o×,,:,,=
_NH 3
f
_./_'
--NITRIDE_
( l
Analysis The
first
and
the
flow out The
the
IPBON, and
2.3:
Gate
(
POLYCRYSTALLINE_
IPB
is present;
SIL_
THIN
_
OXIDE_
OXIDE
SILICON
Oxide
defect
origin,
after
Kooi
(1976)
and
Nakajima
(1979).
Technique fault
mechanism
poly the
gate, poly
second
IMP.
mechanism
and
current
OFF
to the
investigated
layers Four
particular
this with
between
metal
Poly
that
measurement,
the transistors
IPD
cap
the and
oxide
between shown either
measurements is the
to Bulk.
channel gate
is shorting
different
IPBOFF.
from
indicates the
is shorting
is applied
To perform
measured.
IPDOFF,
us to identify
A voltage
to various
current
is investigated
metal the
cap
current
is measured.
region.
is applied
is the
that
layer
fault
source/drain
voltage and
3
SILICON
Figure
the
_
The
is absent. defect
current ON suffix These
as shown
gate
in Figure
biased are
from
made:
2.4,
IPDON, to Diffusion
that
a channel
measurements
in Table
and
ON or OFF
Poly
indicates four
the
2.6.
Two
allow types
a
18
CHAPTER
STRUCTURE:n-PAC DEFECT: TYPE # 1 CHANNEL: OHMIC BULK: JUNCTION _l-
STRUCTURE: DEFECT: CHANNEL: BULK:
2.
SETS
vG --_+SV
T IPD
( SILICON
_-
/ -
p
°
IPB _
fault
CHIP
I_PAC TYPE _/2 JUNCTION OHMIC
VG = _+5V
IPD
Figure
TEST
2.4: type
of PAC
Two
IPB
types
of Pinhole
is determined
by the
fault
models
are
type
1 defect
models
the
first
type,
the
pinhole
Array channel
proposed n-PAC
forms
Capacitor
(PAC)
conduction
type.
to explain and
the
the
type
an ohmic
four
measured
2 defect
connection
structures
models to the
where
currents.
the
The
p-PAC.
channel
and
the
In the a diode
connection to the bulk. In the second type, the pinhole forms a diode connection to the channel and an ohmic connection to the bulk. From these models we have prepared
an expected
response
for the
was prepared for both single is one in which two or more measured
current
the
"l";
value
is greater
otherwise,
currents
as shown
than
or equal
it is assigned
to I(CUTOFF)
the
value
set to 1.0 x 10 -s A, but our software 1.0 x 10 -9 to 1.0 X 10-_A to better
can modify fit the data.
certain
by four
four
type measured
other
currents,
combinations
modeled cover the
of signature
a large p-PAC
between
area is more
including
represented one can
of currents
by the defects and
shown
identify are
other
diagnosable
the
observed.
in Figure
affect
a p-PAC
in Table
2.7.
This
table
and multiple faults. A multiple fault (e.g., BD) faults can lead to the same current path. If the
2.4.
adjacent than
the
or an n-PAC
"0".
Initially
it is assigned I(CUTOFF)
is
I(CUTOFF) in the range of Each modeled defect has a
digits
(see
nature
Table
of the
In these When
then
cases,
this occurs
subarrays. n-PAC.
Thus, chip,
if you choose
From
In some
the the
Notice
on a test
2.7).
defect.
defect defects
in Table have the
the cases
is not usually 2.7 that
to choose p-PAC.
2.2.
FAULT
TEST
CHIP
Table
19
2.6:
Pinhole
Array
Capacitor
Defect
The
PAC
Detected histogram
No Defect
Detected
B
Poly-Bulk
Defect
D
Poly-Diffusion
S M
Poly-Diffusion Defect Metal-Poly Defect
P ?
Probing Fault Other Defect
Analysis
are
is generated,
as symbols
PAC
a cluster
defect.
Third,
the
a value
for the
elements
Finally, and
for all categories
values
are
The 3-#m
shown
PAC
oxide are
Analysis
program
PACs.
defects B, BD
and type
2.6. one
and
in Figure
2.5,
in a 1101
sequence. clusters,
The
gate
oxide
defect
2.6 and
in the
are found defect.
is type Defect
the
or more
used
are
a wafer
type
used
map
of the
for each
method
is
defect.
category
for calculating
to analyze
of elements
data
and
p-PACs
oxide
defect.
the
Four
defect three
isolated
defect,
and
D,
B, DB.
data
these
The
Map
cluster shown
subarrays,
from
PAC
analysis)
of the
for its current of one
results
a total the
a total
the for each
have
For example,
have
adjacent
Second,
is calculated
of this
raw that
Location
four-current
alphabet
as to the
E,
number
SB type.
n-PACs
one other
in three
defect,
a B, BD type
The
of the
defects.
categorized
was
show
metal-poly
is clearly
P-P
(both
are
with
categorization.
2.6.
total
These
two
four Figure
The
results
2.5 and
Letters
Examples
2.5 and
Example
in Figures
per
combined.
Data
2.5.
defect
a gate-oxide
of the faults on the wafer; see Figure 2.5. whether the fault is an isolated defect or are
in Figures
CMOS/bulk
is 70,434.
defects
oxide First,
subarrays
shows the location is used to determine
of Array)
steps.
in Figure
generated which This information
(Side
automates
in three
as seen
to represent
Defect
Program
categorized
classes.
Classes
N
Data
faults
defect
"a"
structure are
shown
of 6 isolated
gate
gate
oxide
defect,
exceeds
isolated
gate
metal-poly
defects
highlighted I(CUTOFF) oxide oxide
defect, defects.
defects
are
highlighted
in Figure
2.6.
When
they
are
two
classified
defects
as a cluster
in
2O
CHAPTER
Table
2.7:
Defect
IPDON
IPBON
based
on four
IPDOFF
Pinhole
IPBOFF
TEST
Array
TYPE
CHIP
Capacitor
1
TYPE
2
n-PAC
p-PAC N
0
0
0
N
1
0
0
1
B,D,DB
D
1
0
1
1
S,SB,SD,SBD
S,SD
1
1
0
1
?
B,BD
1 COMBINATIONS
1
? ?
SB,SBD ?
1 OTHER
NOTES:
ON OFF
= Channel = Channel
SETS
tests.
0
1 ALL
2.2.5
identification
2.
present absent
0 = Current
less than
1 = Current
greater
I(CUTOFF) than
or equal
to I(CUTOFF)
Comb/Serpentine/Cross-Bridge
Resistor
Description The
Comb/Serpentine/Cross-Bridge
shorts
and
one
opens.
This
cross-bridge
Figure
resistor.
2.8 shows
a schematic
Comb/Serpentine/Cross-Bridge
ers.
Prior
that
the
touch
to measuring
each
structure The
The
probe
Resistor
test
pads
pad.
The
the
five
combs
comb
wires
have
the
which
a different
crosses
over
steps
made
crosses
over
steps
made
breaks
in the
The wire mation
wire
due
cross-bridge
width
where
structure, down
is needed
test
down
test
when
are
spaced
length
according
adjacent layers.
by layers
of poly
coverage is used the
diffusion,
serpentine
the
Notice probes
to
resistance
100 ohms. between the design
lay-
rule
serpentine limit.
The
The
serpentine
Metal
serpentine
and
is used
the
sheet
for detecting
problems.
to locally
is formed
two
the two-terminal
serpentine.
2.7.
Poly
is performed.
For example,
and
and
2.7 allow
to the
to the
and
Resistor.
for Metal
in Figure
layer
in Figure
Comb/Serpentine
value which is usually used for detecting shorts
to step
to analyze
of the
is passed
single
one serpentine,
is shown
is available
shown
level
bridge
structure
a probe
structure
by lower
resistor the
of the resistor
is less than some predetermined The comb structures are and
layout
to characterize
of five combs,
representation
for the probe
is used
consists
over
measure the
highest
resistance
level
resistance
layer.
measurements.
This
and infor-
2.2.
FAULT
TEST
CHIP
21
M44E WAFER 4 FAULT CURR. IPDON 1.0 × 10- i5 0 2.0 × 10 -15 0 5.0 x 10- 15 0 1.0 2.0 5.0 1.0 2.0 5.0 1.0 2.0 5.0 1.0 2.0 5.0 1.0 2.0 5.0 1.0 2.0 5.0
× × × × X × x × × x x x × x × x x x
10 -14 10 -14 10- i4 10- i3 10 -13 10 -t3 10 -12 10-12 10- i2 10 -ii 10 -_l 10 -li 10- lo 10- lo 10- 1. 10 -9 10 -9 10 -°
I(CUTOFF) 1.0 x I0 -s 2.0 x 10 -s 5.0 x 10 -s 1.0 × 10 -7 2.0 × 10- r 5.0 X 10 -7 1.0 × 10 -c 2.0 × 10 -G 5.0 × 10 -G 1.0 x I0 -s 2.0 x 10 -s 5.0 x 10 -5 1.0 x 10 -4 2.0 × 10 -4 5.0x 10-4 1.0 x 10 -3 2.0 x 10 -3 5.0 x 10 -3 INC/EXC cUTOi_F LOWER
0 1 0 0 8 7 12 8 6 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 3 1 0 0 0 0 0 0 0 0 0
d a
bef c
OF OBSERVATIONS IPDOFF IPBOFF 0 0 0 0 0 0
0 0 2 0 2 3 12 22 1 0 0 0 0 0 0 0 0 0
0 0 1 0 3 4 17 19 1 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 0 0 0
0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
b acef d
a
d e
f
b c
48/0 48/_0 ..... 4_8/0 .... < 1()-g Amps STRESS VOLTAGE BOUND SHOWN FOR HISTOGRAM
C,URRENT Figure
p-PAC NUMBER IPBON 0 0 0
2.5:
SOURCE P-PAC
BOUND test
APPROX
results
for
IMP 0 0 0
0 0 0 0 1 0 0 24 9 6 2 0 0 0 0 0 0 0
0 0 0 0 0 0 1 10 12 7 13 2 2 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
b c aef d
48/0_ ..... 48_/0 = 5.0 V INCREMENT
= 20 mA run
M44E,
wafer
4.
CHAPTER
22
DEFECT
LOCATION
M44E
2.
TEST
CHIP
MAP:
4
WAFER
p-PAC
COL 1144488ACCDD ROW 582585825858 N/PP
2709
............
8127
............
18963
..........
40635
............
2709
............
8127
......
P/PD
N-
a .....
18963
....
b-c---d-
40635
--e---f p-PAC
..... DEFECT
GATE
OXIDE
ANALYSIS DEFECTS
TYPE D
S
CLUSTERS
B,BD
FAULT SITE
SB
e
b
a
c
P-P
OTHER M-P
TOTAL ELEMENTS 70434
f d
Z (×1o ES (×.1o 4)
>
3.6
> 3.6
2.1
6.0
***
2.6
66
***
METAL-POLY
FIELD
OXIDE
CLUSTERS M-M NO.
i
OF
> 3.6
> 3.6
TOTAL ELEMENTS
0
0
70434
> 3.6
> 3.6
13
***
***
1.4
FAULTS E
(xl0
ES
(xl04)
_)
Figure
13 1.4
2.5:
>
3.6 ***
P-PAC
test
results
for run
1.5 4.8
DEFECTS
OTHER
M-P
0
> 3.6
M44E,
wafer
4 (Continued).
SETS
2.2.
FAULT
TEST
CHIP
23 M?4E FAULT
WAFER ....
CURR. 1.0×10-,, • 2.0 ,< 10-1`5
4
n PAC r NUMBER _/PBON
/PDON
5.0 × 10- _5 1.0 × 10-14 2.0 x 10-14 5.0 × i0-14
2,0 × 10-12 5.0 × I0-12 1.0 × 10- lj
2 4 9 9
19 5
9
0 1 0 0
2.0× I0-1° 5.Ox 10-_o 1.0 × 10-o 2.0 × I0-O
0 3 I 0
5,0 >_ 10-9
0
0 1 0 I
I 0
1.0
0
0
2.0 × lO--r 5.0 × 10-7
0 0
0 0
1.0 × 10-o
0
2.0
× 10-6
5.0
x I0-6
1,0 × 10-,5
5.0
0 0 0
0 1 1
1 1
6 19 3
13 15 5
2 8 1
0 0 0
d
2 3
6 20
3 0
0 2 3 0
2 0 0
0 0 0
bd ace
0 0
0
e
0
O
0 0 0 0 0
0 0
0
0
0
0
0
0
0
0
0
1
0 0
1 0
0 0 0 0
0 I 0 0 1
× 10-4
0 0 0 0
1 2 2 7
0
0 0
d
f
0 0 0
0
f
f
0
0
0
0
0 0 0 0
0 0 0
0 0
0 0
I
0
0
0
0
0
0
0
0
2.0 x I0-_ 5.0 x 10-a
0 0
0
0 0
0 0
0 2 1
BOUND
CURRENT
Figure
v SHOWN
SOURCE
2.6:
N-PAC
_xftE, FOR
BOUND
test
I
SS
f
d
1.0 × jO-a
LOWER
VOL-'PA_s---_"'-"-,_ =
........ az/1 5.0 V ...............
HISTOGRAM INCREMENT APPRox = 20mA
results
for
MP
I 0 0 0
I 0 0 0
abe e
2.0 x lO-S 5.0 × lO-S
2.0 x 10-5 5.0 × 10-_ 1.0 x 10-4 2.0 × 10-4
0 0 0 1
I 0 1 0
0 0 6 I0
I
0
4
2.0 × lO-ll 5.0 x 10-J_ 1.0 × I0- lo
IPBOFF
0
0 0 0 0
X 10 -13 × 10- z3 × 10-_3 × 10-12
x I0-r
OBSERVATIONS
IPDOFF 0
1,0 2.0 5.0 1.0
OF
run
M44E,
wafer
4.
24
CHAPTER
DEFECT
LOCATION
M44E
II44488ACCDD 582585825858
2709
........
8127
--M .........
P---
............ -M ......
N---
2709
a .......
P---
8127
b ...........
18963
c .....
40635
e ..........
d .....
n-PAC
f DEFECT
GATE
OXIDE
ANALYSIS
DEFECTS OTHER
l
D,B,DBTYPE
CLUSTERSM-P P-P
S,SB
d
FAULT
CHIP
n-PAC
ROW
40635 P/ND
4
COL
18963
TEST
MAP:
WAFER
N/NP
2.
TOTAL ELEMENTS 70434
a
b
SITE
C e
5)
13
ES ( x lO 4)
140
E
(xl0
3.6
3.4
***
FIELD
TYPE
CLUSTERS
OF
M-M
3
>
14
METAL-POLY
M NO.
>
3.6 ***
OXIDE
1.8
15
4.1
DEFECTS OTHER
M-P
0
5.9
TOTAL ELEMENTS
0
0
70434
FAULTS
_:6 ES
( × 10 4)
Figure
2.6:
6.9
N-PAC
> 3.6 ***
test
> 3.6..... _.6 ***
results
.......
***
for run
_._ 6.9
M44E,
wafer
4 (Continued).
SETS
2.2.
FAULT
Analysis The
TEST
25
Technique
serpentine
serpentine Lserp,
CHIP
and
resistance,
Rserp,
measuring
the
is measured
voltage
by forcing
drop.
The
a current
serpentine
through
effective
the length,
is
R_erp × Wb_idg_,high
Lserp ----
Rs,bridge
where
Wbridge,high is the
pared
with
150%
of the
coverage
the
is due
Wire wires
are
are
M61P
that
necking
being
by suppling
shorted
site
wire
are
results
shown
than
M61P
Las.draw n : fault
Contact
and
the
10.0
comb
nA,
the
as faulty. the
The wires
raw
data
program
and
gathered
generates
calculates
the
a
defect
detected.
No short
Notice
etching.
than
Comb/Serpentine/Cross-Bridge
164700#m.
was
serpentine
to analyze resistor.
opens
2.9.
run.
the
layers.
to over/under
is greater
is flagged
developed
a step-
serpentine
steps.
low lying
due
layers
of the serpentine
and
for Poly
in Figure
for the
a probing
length
shorts
over
from
5 V between
the
been
to have
apparent
than
step.
features
two
is longer
following:
crossing
different
between and
has
wire
The
of the
at the
underlying
current
program
analysis
2.2.6
of the
detected
_eakage
for the
observed
layers
of the effective
densities The
lying
or more
L,e_p is com-
length
is considered
as faulty.
Comb/Serpentine/Cross-Bridge
histogram
larger
serpentine
resistance.
effective
serpentine
of one
to the
considered
the
the
sheet
If the
is flagged
due
sizing
A software from
then site
and
Under/over
If the
length.
thinning
of high
shorts
Rs,bridg_ is the
wire
Undulation
wires.
the
to a combination
3. Width 4.
length
and
1. Serpentine 2.
and
serpentine
as-drawn
problem
length
width
as-drawn
or open
resistor
defects
that
Lserp -_ 169931
The
"P"
shown
in the _m
for the
which
poly
for run
comb
were
is 3.2 percent
serpentine
indicates
encountered.
Chain
and
Contact
Chain
Matrix
Description The Contact chain. Since area
than
Structure.
Chain Structure [7] consists these contacts share the same
individual The
four
contacts. types
Figure of Contact
of eight current
2.10 shows Chain
contacts connected path they consume the
Structures
layout are:
of the
to form a less silicon
Contact
Chain
ORIGINAL OF POOR
26
CHAPTER
2.
TEST
CHIP
SETS
CROSS-BRIDGE
Figure 2.7: The Comb/Serpentine/Cross-Bridge with poly crossovers.
Resistor
in First-Layer
Metal
PAGE
IS
QUALITY
2.2.
FAULT
TEST
27
CHIP
--_1!
I
m
i
I
! '
i
i
SERP. IN
Figure
E-]
E-!
COMB 2
COMB 3
COMB 4
COMB 1
2.8:
mented
E.• Schematic
into
diagram
of the
Comb/Serpentine
Resistor
SERP. OUT
COMB 5
which
is seg-
five subarrays.
1. p+Poly/Metal, 2. n+Poly/Metal, 3. p+Diff/Metal,
and
4. n+Diff/Metal. However,
the
each
chip
to enable
tact
Chain
Matrix
Figures the
2.11
Contact
Chain
Matrix
and Chain
Contact
Chain
a meaningful Structure 2.12
show
Matrix
Structure
was the
Structure contact designed Contact
transistor included
level on
Fault
does
not
probability
provide analysis.
and
included
Chain
Matrix
schematic, Chip
No.
enough
on
Thus, Fault
layout
respectively. 7 consists
data the
Chip
on Con-
No.
schematic
7. and
The
Contact
of four
different
28
CHAPTER
Identity M61P
of failed CHIP
chip - by location in chip 11111111112222222222
TEST
CHIP
SETS
M61P
run.
carrier
123456789A123456789A
NO. COMB
2.
16056 29436 50844 66900 163236
SERP.
183OO
SERPENTINE
LENGTH
........
p
...........
HISTOGRAM
0 166943
0
167690
3
***
168437
3
***
169184
5
*****
169931
2
**
170678
4
****
171425
0
172172
1
*
172919
1
*
+
0
As-Drawn Open
Serpentine
Serpentine
Shorted
=
=
=
[0], High
(#m)
Rserp
(12) Avg/StDev/Inc/Exc/Inv
ANALYSIS
Avg/StDev/Inc/Exc/Inv
e (fl)
Wbridge,hig
164700 Res.
#
- -
Serpentine
Wires
=
169931/1.39
= 812856/3.30
Avg/StDev/Inc/Exc/Inv
h (>m)
(Total
(#m)
#
Elements
Total
#
Shorts
Total
#
Defects
=
Sites
= 20)
× 103/19/0/1
14.5/1.11/20/0/0
Avg/StDev/Inc/Exc/Inv
=
3.03/0.228/20/0/0
........
Figure
2.9:
6529440
Opens
(_m)
366000
0 (#m)
Elements/Defect Std. Deviation
(Step:
9/_m) NA
NA > 2.13
Test
[0]
x 104/19/0/1
Shorts Total
=
[0]
nserp
Rs,bridg
YIELD
Wires
Combs
Length
results
× l06
of
Poly
(_m/Defect) *******
0 > 3.66
× 105
Comb/Serpentine/Cross-Bridge
(Steps/Defect) *******
on
2.2.
FAULT
TEST
CHIP
29
r POLY AND DIFFUS ION METAL
Vl2
VII AFteRt_ENEWEG(19S6_ Figure
2.10:
Contact
types of contacts: are 116 contacts
p+ and n+Poly/metal for each contact type.
consists
of 8 rows
and
current
path
the
same The
trix,
different consumed
to
Contact
replaces
excessively
to save
Chain the four
types
Matrix
necessary
version of the via resistance large
currents
The
silicon
were
by using
structures
saves
overhead Contact chains.
in each
row of the
There Structure
matrix
share
area.
matrix This
Structure.
and p+ and n+Diff/Metal. The Contact Chain Matrix contacts
Structure,
contact
of contacts.
by the
An early 1st metal
58 columns.
Chain
one
which
area
which
circuitry
and
randomly were
would
to generate
ma-
to access
the
otherwise
have
included unsuccessful
2nd metal because
been
pads.
Chain Matrix Structure This structure was
required
accessible
needed
measurable
voltages.
30
CHAPTER
2.
TEST
CHIP
SETS
58 CONTACTS
METAL METAL METAL METAL METAL METAL
V21
TO TO TO TO TO TO
N-DIFF P-DIFF P-DIFF N-POLY N-POLY P-POLY
58 58 58 58 58 58
CONTACTS CONTACTS CONTACTS CONTACTS CONTACTS CONTACTS
V22
• • • • •
V21
V22
12
12 _m
Vll
I_
DIFFUSION
Figure the
V12
four
2.11: types
_
Contact
Vll
POLY Chain
of contacts
l'-'1
Matrix found
with
V12
METAL 464 contacts.
in a single-metal
3-#m
Developed CMOS
to characterize process.
2.2.
FAULT
TEST
CHIP
31
---x.__.4 - COL
...
-I_o
w
- COL cc
I
"'-
_
I
R4-RO
O_
l
]
IROW
...
-FRO
w
ROW
r--1
Figure
2.12:
circuitry
The
test
contact
and
conductance
can
linear
are the
where
of each
for
used
forcing and
the
contact
a current
measuring measurement
I_=CONTACTCELL
0
row
and
denoted
column
addressing
by an X.
characterized
probability
is plotted fit.
The the
by
three
known
value
(64#A/#m
2)
drop over the contact accurate measurements
probability contact. difference
the
an open
of the
the
based
standard on contact
2.13, assumes a normal distribution of contact
scale
and
fitted
line and
the
probability
having
zero
conductance,
of a contact This
mean,
contact,
shown in Figure The cumulative
on the "probability
the
numbers:
of encountering
intersection
of an open to assess
of
the voltage and allows
resistance.
analysis [7]. This technique, of contact conductance.
to represent probability be
calls
interfacial
contacts
probability distribution
taken
Matrix,
measurement
procedure
deviation,
the
the
Chain
the Contact Chain This is a four-terminal
The
square
Contact
C_5-C
Technique
through surface. of the
The
allows
Analysis
COLDECODER
provides
between
a line
is fitted
a characteristic processes,
and/or
using
number vendors.
a Chiaxis
is i.e.,
which The
32
CHAPTER
2.
CUMU NORMAL
TEST
LATIVE (LINEAR
DISTRIBUTION
CHIP
SETS
DISTR IBUTION SCALE)
10o%
{gJ
o G
CUMULATIVE
DISTRIBUTION
(GRAPH
ROTATED)
f
A
L_ >. I-
G 1
90% G/J+ Go
--I
50%
Gp
G
method.
population the
mean
contact
M62Z.
p+Poly/Metal
99%
90%
The
contacts
and
probability probability
of run
of
M62Z
is
Transistors
Description The
floating
behavior the gate The
of the by the
floating
in Figure the
gate
floating
transistor process
gate
2.15. gate
transistor
is expected and
transistor
The
is a transistor
three
transistors
the
charge
models capacitances are the
with
to depend induced for n- and involved gate-to-drain
an isolated on the from
the
poly
initial
gate
charge
measurement
p-channel
transistors
in determining capacitance,
the Cgd,
wire.
The
induced
on
potentials. are
shown
behavior the gate-to-
of
2.2.
FAULT
TEST
CHIP
RK 1 :M62ZCT.
33
103 CREATED:
15:35:11 22-MAY-86 17:16:08 16-APR-86
BY CRUNCH
VERSION
6
RUN M62Z (FAULT CHIP5) P + POLY CONTACT CHAIN STRUCTURE CONTACT CUT WIDTH = 3.0 UM; STRESS CURRENT = 64 i_A/p.m 2 (CP3CTP + POLY 3.0) LAYER = P + POLY SIZE = 3.0 um 800
I []
I
I
I
I
[]
70O
•
%
600
--
z uJ :S
_
_ °
°
° °_/.e
5OO
q
I.U
4OO
300
-
200
-
100
-
I i i
Q,•
J eBqk,
O Q
0 E-3
I
I
I
.01
.1
.3
1 .5
.7
I
I
1
i
i
.9
.99
3N
4N
5N
PROBABILITY
# CONTACTS PROBABILITY
Figure M62Z. naman.
2.14: The
Contact analysis
#PROBE ERRORS= # OPEN CONTACTS INCLUDED/EXCLUDED OF AN OPEN CONTACT ERROR
Probability technique
= = = =
Analysis
was developed
*b,. I 6N
7N
8N
P(GI > G)
0 0 144/0 1.947E-07 9.068E-09
for
p+Poly/Metal
at JPL
contacts
by U. Lieneweg
and
of run D. Han-
34
CHAPTER
2. TEST
CHIP
SETS
S D Cgs
Cgd
-t' I
Ggbo
GC G
cl = Cgd
Cgbo
B
f
C2_
B Cgd
Cgs I
C1 = Cgbo + Cgs
S
-4,
i
C2 = Cgd
Cgbo + Cgs D
n - CHANNEL FLOATING GATE MODEL Figure source.
2.15:
source
capacitance,
depends
on the
Analysis The the
Cgs, area
transistor
and
of the
setup
for testing
is applied
to the
source
the
models
where
gate-to-bulk
poly
over
floating drain
is measured.
length
of 3/_m
source
voltage
channel
gate
the
the
overlap
field
body
is shorted
capacitance,
to the
Cgbo.
Cgbo
oxide.
Technique
test
voltage
Floating
p- CHANNEL FLOATING GATE MODEL
current
were "OFF." to cause the
and
gate
transistors
of the transistor
In run
M56G
the
a gate
overlap
length
of 5 V. The
floating
gate
of about The same
floating current
and
is shown the
floating of 26 #m
p-channel
1.0 × 10 -6 A, and
the
gate transistor voltage to flow in a calibrator
resulting transistors
were
tested
gate
with were
n-channel
is the gate transistor.
2.16.
current
gate
transistors
floating
in Figure
A
through
with
a gate
a drain-to"ON"
with
transistors
voltage required The calibrator
a
2.2.
FAULT
TEST
CHIP
35
+
+ FLOAT
--SV
m
I
m+5 V
FLOAT I _O S
() \7
7 n-CHANNEL
Figure
transistor device
is fully analysis
I-V curves voltage
using
and
the
gate
and
transistor
voltage
transistor
Vgd
VG
shown
= VG,
I-V curves.
used
voltage
and
of the
n-channel from
(JVDS
The
in Figure
the
current.
the
V).
following
gate
Transistor floating
gate
It is estimated
transistors
= -1.5
floating
2.17.
to estimate
channel
= 3.5 V (Vgs in Figure
+
transistors.
is shown are
is calculated
models
gate
transistor
transistor
gate
transistors
for floating
provides
calibrator the
p-channel
floating
setup
drain-to-source
M56G
capacitor-divider
Test
a calibrator
the
for a given
for run
the
2.16:
connected
from
that
p-CHANNEL
is less than The
gate
VTn,
voltage
equation,
of
using
the
2.15
I-
YGi)
× (1-e
-qRc)
1 + C2/CI where C = C1 × C2/(CI
+ C2), C1 = Cgd
transistors (C1 -- Cgbo+Cgs is the process-induced charge the
external
seconds.
voltage
Thus
and C2 = Cgdfor on the gate. Also
source.
for time
The
t >> RC VG
Since
the
gate
stant
RC,
the
negligible.
The
delay
of the
transition initial
time this
CMOS
+
voltage,
is of the
order
1.0 × 10 -l_
- VGi)
,+ c2/cl
devices VGi,
RC,
VGi with
becomes
(I VDSI
between
Cgs for n-channel
p-channel transistors), and R is the resistance in series
constant, equation
= VGi
time gate
and C2 = Cgbo+
the
is much initial represents
larger
state the
and
than
the
the
steady
gate-to-source
time
con-
state voltage
is
36
CHAPTER
CALIBRATOR
TRANSISTOR
TRANSISTOR
,
_VD
I I
'
=._
VG I
FLOAT
- ,oC)
_°_
TEST
LoGJDI
_-_- - -I
UNDER TEST
_
VD
- -
J/i
i
x 25r, , _--/_ ! !
I/I
I
I
VG2
VG3
VDI__
VG1
.....
VG _
VD1
VD2
VG3 VG2 VG1 VG i
Figure
2.17:
CHIP
,o()
vo3-_
LOG ID
2.
,
I
I
VD1
VD2
VD3
Floating-Gate
device
analysis.
VD3
VD ---_
SETS
2.2.
at
FAULT
TEST
a drain-to-source
behavior
of the
The when
initial VGi
equation
CHIP
37
voltage floating
gate
of zero
gate
voltage
RC
+ C2),
C1
= Cgs2
+ Cgbo2,
C2
= Cgsl
+ Cgbol,
ignored.
(RC
is in the
VG
order
= VGi
of 1.0 × 10 -13 seconds),
we have
(VDD-VCi)
+
1 + C2/C1 Since of
we can
VDD/2 The
the 4.0
for the analysis
gate
C1 = C2 and
second of the
faulted faulted
transistors:
n-channel
of about
The
and
the
implies
that
for this
"ON" The
with work
tions
have
have
been
not
the
transistor type
on the yet
developed
voltage
floating been and
fully are
is "OFF" about
the of about
gate
floating
of faulted
is at
configuration voltage
we expect
a gate
voltage
structure. structures
p-channel
gate
gate
1.3x
Poly-Poly b) Serpentine Metal Wire Poly
c) p-Pinhole
Array
Metal-Poly Gate d)
Ox.
Gate
Ox.
Poly Metal Poly
3932064
hngth(1
#m)
0/18
5876496
length{
1 pro)
0/18
332100
steps(6pm)
>
3.2) 6.8×105
Defects
1.2x105
Linewidth Sheet
b) Contact
_
9/18[
VARIABILITY
Avg.
Std.
Value
Dev.
ANALYSIS Prob.
of
Open
Points Incl/Excl
Resistor:
Linewidth(#m)
Sheet
0/18
2. PARAMETER
(Dimensions)
a) Cross-Bridge Metal
0/18
l0 G
(Opens): 3.3x105
TABLE Parameter
10 _
>
Shorts
Metal-Poly
Element
Total Elements
1.9×
Defects
n-Pinhole
Bad/Total
> Resistor
Wire
Sites
0.o8 0.13
18/0 18/o
30.
1.
18/0
14.1
0.59
18/0
(4.5#m)
(#m)(3.0#m) Res.
Res.
2.94
(rnfl/[:]) (n/El)
Array
Resistor
(Contact
size:
3.0 #m)
p+Poly/Metal
(I])
1.95×107
n+Poly/MetM
(fl)
5.42x107
144/0 144/0
p+Diff/Metal
(fl)
1.53x10
c
144/0
n+Diff/Metal
(fl)
1.15x10
s
144/0
46
CHAPTER
for
this
#m;
run
the
were
The
observed
third that
summary results
twelve
this
could
of defect
this
Further, the
the
the
2.2.11
Fault
It is of major
#m.
linewidth
the
circuit and
can
on layout
process
the
ith-type For
in the
problems
No. 5.
The
report
defects
and
it four
previously,
of circuits
fabricated
defect
Since
higher
The
than
The
coverage
densities
prob-
in previous
nominal
problems
is 4.5/zm
were
the
of faults Ei
circuit,
geometry
circuits,
and
the
priority
observed
the
represents
the
number
shows
Ni
represents
and
Di
= Ni/Ei
circell
circuits
to
with no adjacent shorts, no matter to poly
shorts
design,
the
estimated
defect,
Chip
of basic
of these
for proper
2.23
Fault
for a specified
responses
of poly
is needed
Figure
in the
of faults
For example, a circuit any poly to poiy layer
circuits.
ith-type
generated
likelihood
the
Therefore,
specified
contacts.
process
poly how
for this
simulation, of fault
pri-
Elements/Defect
the
from
number
of the
fault
priority
is the
ith-type for
the
defect. the
scaled
defects
coverage
Process
for different
2.23
for the
example
priority listing, from the MOSIS were
step
Chip
oxide
undersized.
step
to prioritize
Prioritization
Chip
elements
is 4.5
As explained
performance
are again
the
geometry.
the same
In Figure
Fault
width
undersizing.
be used
of integrated
oritization.
SETS
summary
Diffusion/Metal
No metal
that
control.
is zero. testing
gate
is significantly
Prioritization
reports not
contact
linewidths 2.81
significance
are
to defective
the process defects are different. to poly layers will not experience bad
the
defects.
timing
metal
on Fault
From
p-type
oxide
wire
CHIP
wire.
M63E 2.10.
have
gate
no
metal
for run
sites
nominal
However,
in Table
n-type
degrade
metal
of metal
elements
shown
relates
was
as a result
cuit based
produced
are
of an open
measured
summary
#m.
undersized
was
have
observation
of occurrence
runs. and
to the
The
TEST
run.
Another ability
linewidth. 2.67
of twenty-eight sites
type
was
due
out of twenty-eight during
metal
linewidth
summary
is seen
undersized
measured
problems
M63E
is the
2.
using
have
circuit
specified
in Table
2.11,
we have
shown in Table 2.12, based on the results run No. M62Z discussed in Table 2.9. The Di
= 104Ni/Ei.
the
highest
priority
for the
example
circuit.
As seen and
are
in Table expected
2.12
prepared
a fault
of the Fault Chips results in Table 2.12 the
to be
n-type the
major
gate
oxide
cause
of
2.2.
FAULT
Table
2.10:
Prepared
CHIP
FAULT
CHIP
by:
Report Note:
TEST
No.
ANALYSIS
H. Sayah(hrs),
3. Run
Fault
47
Chip
Reviewed
No. M63E. was
Type
> 2.0x
Poly
Poly
Resistor
Ox.
Array
>
Ox.
G 5,9x
1.8×
Defects
106
Poly Metal
1.3x105
Poly
2. PARAMETER
(#m)(4.5#m)
Linewidth
b) Inverter
6116544
length(_m)
2/28
9141216
length(_m)
6/28
516600
steps(6Dm)
0/28
512400
steps(9Aum
0/28
2537024
capacitor
2537024
transistor
2537024
capacitor
2537024
transistor
-4/28
]
1/28 I
VARIABILITY
Avg.
Std.
Value .....
Dev: ........
ANALYSIS Prob.
of
Points
O pe_ ....
Incl_/Ex_l
Resistor:
Linewidth
Sheet
0/28
7.7×I03112/28
(Dimensions}
Sheet
l
10'
4.6 x 105
................. Metal
Element
Cap.:
Shorts
a) Cross-Bridge
¢
105
1.1×10
TABLE Parameter
2.9>(10
5.1x105
Array
Metal-Poly
Total Elements
Cap.:
Defects
d) n-Pinhole
Gate
De v.
l0 G
> 5.1x
Metal-PolyShorts Gate
Sites Bad/Total
(Opens): 7.7 x 104
Wire
c) p-Pinhole
7-30-86
of 14 wafers.
ANALYSIS
Std.
5.3 x 106
b) Serpentine Metal Wire
C. Pifia(cap)
(Shorts}:
Metal-Metal Poly-
CMOS/BULK
No. 5 Date:
on each
1. DEFECT
Element_s/De.fect Resistor
3-_m
M. nuehler(mgb),
Chip
twice
E-value
.......... a) Comb
by:
Fault
fabricated TABLE
Defect
FOR
0.12
28/0
0.18
28/0
28.7
1.04
28/0
12.3
0.77
28/0
_
(#m)(3.0#m) Res.
Res.
2.72
(mf]/[]) (fl/D)
Matrix
(Wn/in
= 4.5/3.0,
Wp/ip
= 6.0/3.0):
2.35 - 19.0
0.03 1.04
-
5692/329
-
5692/329
{mV)
0.11
0.28
-
5692/329
(V)
4.99
0.01
-
5692/329
Vinv G air
(V_
VIow Vhigh
c) Contact
Resistor
Array
(Contact
size:
3.0Urn): I
p+Poly/Metal
(fl)
3.38
0.87
2.7
x 10-1°
n+Poly/Metal
(12)
2.14
0.64
2.1
x 10-7j
224/0
4.2 4.7
x 10 -4) x 10 -5
224/0 224/0
p+Diff/Metal
(l-l)
6.21
2.07
n+Diff/Metal
(_
4.48
1.19
d)
Open-Gate
Initial
Gate
n-Transistors Voltage
(V)
(W/L
= 6 _zm/3 0.16
I
224/0
#m):
0.05 ..........
4/0 ....
)
48
CHAPTER
FAULT
CHIP
GATE-LEVEL
EiIELEMENTS__
2.2.12
The
fault
models tial
Fault
Timing
information
gathered
for proper
simulators
process.
from such
structures
we have
test
defects.
Figure
2.24
circuits
we have
to-drain studied. and
and
the
all of the [10] for the
for n- and
defects
complete
p-channel
Jet
fault
models
results on
using
short
defects
of the
Gate
used
to develop
of the
only the
for n- and
p-channel
has
simulation
been The are
defects using
performance
n-channel prepared circuit shown
Array
oxide
calculated
gate-to-channel
same
fault
is essen-
Pinhole
for gate
ith
Oxide
a
of logical
In this experiment
Laboratory. fault
to
were
the
priority
development
models
defects
ignored;
was results
experiment.
are
the
model
the
p-channel
of these
Propulsion transistor
Chip
Fault
the proposed
simulation possible
Fault
introduced
a simulation
gate-to-source
DESIGN
Due
[9]. From
The
effects
conducted
A more
including
Technology used
to study
the
shows
of n- and p-channel transistors. bulk resistance of 1000 Ft. In order
Di represents
as SPICE.
of circuits
Capacitor
SETS
]
Degradation
simulation
gate
oxide
prioritization
Circuit Pinholes
for circuit
CHIP
Ni (_ ELEMENTS) E.[ELEMENTS_ '_ DEFECT
2.23:
TEST
Ni (_ ELEMENTS)
/
Di (DEFECT)=
Figure defect.
2.
the
gate-
defects fault by
are
model Fail-Safe
configurations in Figures
2.25
2.2.
FAULT
Table
and
2.11:
2.26.
mission
circuit
transistors
2.
i0,000
(#m)
3.
I0,000
(lzm)
4.
I0,000
Poly
5.
10,000
Metal
6.
10,000
p+ Poly/Metal
contacts
7.
10,000
n + Poly/Metal
contacts
8.
10,000
p+Diff/Metal
contacts
9.
I0,000
n+ Diff/Metal
contacts
is embedded
between
faulty
transistor
to simulate
(either for
and
2.27
resistance
cause
timing
length
two
steps
minimum
The
output
is required
resistance.
The
circuit
than
of the
circuit
of the
faulty
its output to the
simulator
pinhole
and
these
used
The
transistors
values
trans-
its output
of SPICE.
n-channel
size
to pull
to pull
version
As seen
greater
performance from
Figure
degradation
resistance
values
does
not
From
pinhole the
model
resistance
values
drastic
the
short
from
lead
that
Array
the
0.8
to circuit
different
circuits with
on the have pinhole
4.5 kfl
model are
short
than
observed
As
shown the
short
significant
for this
to
experiment,
to such
depends
in
of the
Although
responses
not
p-channel
performance
sufficiently
defects
the
circuit does
we have
by 1 ns. used
short
smaller
100kfI. the
not
circuits different
and
results
pinhole
the
model
values
10 and degrades
p-channel
until
resistance test
the
of pinhole
fault
about
between
of 10 to 100 kfl
degradation
of transistors
than short
of 10kll
values
n-channel
Capacitor
are
resistance range
smaller
versus
performance,
the
smaller pinhole
Pinhole
by 4.5 ns and in the
for
2.27,
resistances
pinhole
performance
be noted
performance
switch
2.27,
in timing
for pinhole
n-channel
The
length
diffusion
it takes
as smaller
in Figure
2.27,
it must
time
elements.
steps
situations.
4 to 1000kf/for
As seen
the
cause
the
value.
0.7 kfl.
Figure
adjacent
and
a commercial
transistors
adjacent
transistor
The
to switch. model
about that
shows
resistance
fault
Poly
of circuit
failures.
Figure
switch
over
of pinhole
from
to Poly diffusion
faulty
is PRECISE,
to 1000 kfI for p-channel performance
Poly
circuit
the
value
to Metal
over
or ground).
each vary
Metal
practical
VDD
experiment
ceases
number
I0,000
resistances
short
a selected
i.
is noted
for this
with Elements
is precharged rail
49
No. Elements
gates
to the
short
CHIP
Example
The
transistor rail
TEST
defects.
to a great
5O
CHAPTER
Table
2.12:
Priority
M62Z
shown
listing
in Table
of likely
defects
for
shorts
Poly-Poly Metal
geometry
the
A major models
shorts defects
110
n-type
Gate
Oxide
defects
833
p+ Poly/Metal
contacts
20
n+ Poly/Metal
contacts
54
p+Diff/Metal
contacts
n+Diff/Metal
contacts
current
drive
of the
experiment
accomplishment
on the
Fault
Chip
Testing
vacuum
Chips
on the to chip loaded
pump stage
with of the Fault
prober,
to hold prober.
automated Chips
Slotted-Chuck
The
of the circuit
in Figure
and
MIN
the
faulty
transistor.
composed
The
of minimum
has
development
range
of the
Chip,
and
is used
Fault
wafer
2.28.
To aid
prober in chip
and
it is possible
testing.
and
of fault
fault
models
to simulate
Figure
for testing.
the
was chips
to move 2.29
The
parametric
testing
Slotted-Chuck
Slotted-Chuck Thus
is the valid
of interest.
a special
the
ready
gold-plated, brass plate with mm wide slots to accommodate The
< -
gate
period
by our automated
a wafer wafer
report
structures
shown
is used
for extended with
PAC
are tested
system,
Chips
driving
as SPICE.
defects
Fault
the
such
of these
acquisition
1
circuitry
of this
simulators
from
Fault
MAX
p-transistors.
the
The
< -
153
is a transmission
is derived
2.2.13
Priority
40
Oxide
for circuit
effects
Run
< 304
Gate
n- and
and
< 301
opens
p-type
in this
circuit
SETS
< 52
opens
wire
Metal-Poly
on
CHIP
< 77
shorts
wire
Poly
used
example
Estimated
Metal-Metal
driver
the
TEST
2.9.
Defect
extent
2.
shows
of unpackaged developed.
in a fixed
the prober the
Slotted-Chuck
data
from
two
major
design
revisions
chip
Slotted-Chuck is a circular,
a five-inch diameter, a 75 mil thickness and 48-7.1 mm :_ 7.1 mm unpackaged chips.
undergone
A
location
during
3-7.4 its de-
2.2.
FAULT
TEST
CHIP
51
G
B
O--
B
:
G
O
bulk -- 10=V_0_
NMOS
FAULT
MODEL
(NFAULT)
*FAULT MODELS OF THE PINHOLE
velopment Chuck moved.
Figure
2.24:
period.
The
ARE DERIVED FROM ARRAY CAPACITOR
Fault
first
models
revision
to alleviate a problem with The second was to reduce
to ensure
proper
After
the
vacuum
chips
prober,
we manually
location
information
the
PMOS
are
was
strap
must
determine
be worn
2.2.14
Future
The
Chip
Fault
debugged Contact The
and Chain transistor
devices.
the
weight
of the
Slotted-
the Slotted-Chuck sliding when the stage was the diameter of the vacuum holes to 10 mils
on
the the
computer
test procedures to locate and Note that to avoid electrostatic
wrist
RESULTS
p-channel
to reduce
{PFAULT)
achieved.
loaded
in the
MODEL
THE EXPERIMENTAL TEST STRUCTURE.
for n- and
was
FAULT
during
Slotted-Chuck location
of the
memory.
This
and
placed
chips
and
on store
information
and
unloading
of the
wafer
the
is then
test the structures on the chips. discharge and oxide breakdown, loading
the
chip
used
by
a grounded
chips.
Work
is in the
process
are fully functional Matrix Structures. matrix
structure
of development. except
for the
is designed
AII test new but
structures
transistor
not
yet
matrix
implemented
have
been
and
the
in sil-
52
CHAPTER
2.
TEST
CHIP
SETS
5V
D (- T
OUT PRECHARGE
Figure 2.25: Circuit n-channel transistors.
B
$
OUT
i I i
I I
I I
,/'
I
I
I
I
I
I
i
I
,_
I
I I I
/IDELAy_I / 14"_LL_ I I I
I_
_,.
IX I I
I ' t_
i I
! •
/_v
I
I
I IDLE
I
' V1
D
IOPF
I V2
G
I
',_
i_v
configuration
I
,
I
,,\
I I
N FAULT
and
ENABLE
timing
I RESET
table
I
used
for
simulating
faulty
2.2.
FAULT
TEST
53
CHIP
5V
p EAULT
)
D
.OUT
_v __---Z'r---li v2
I
L.F}
_
w ;, Vl
OUT
Figure p-channel
2.26:
Circuit
transistors.
I
I
, /,
I
I
I
,,
I
I
i
I
I-_ 2v
I/
i
I
, ,
I
I !/
!
I I PRECHARGE
10PF
I
:
' ;
I _._,._2v I DELAY" IDLE
I
i I
PFAULTENABLE
configuration
and
I
timing
Y I
RESET
table
I
used
for
simulating
faulty
CHAPTER
10 6 "
_'
'
I
'
1
,
I
'
I
'
I
2.
'
TEST
I
'
I
CHIP
SETS
'
10 5
-
I
cc
0 z
10 4
_J
o
ta_ INDICATOR
"--_'_ )
jf j .,I--
Figure signals
3.11: Timing sampler and an on-chip timing
delay measurement sampler.
which
utilizes
two-step
input
3.2. TIMING
the
SAMPLER
START The
and
STOP
timing
on
who
the
When
previou_
case,
An
feedback are
the
operator
electronics
and
point,
used
improved
method drift,
sampler
timer
(timing
sampler
control into
that
is read
corrects
value
3.11
waveform
is connected
the
measurement
the
are
cycle.
resolution
t_, values
of tin for
of t,,.
In
applied
in
present
cycle.
implemented
with
generator.
for unknown
cable
another
the
an
If t_, < td
adjustment
and
of Figure
timing
cycle.
starts
in the
ti,
illustrates
(within
output)
the
to adjust
3.11
to obtain
be used
console the
tin and
tm converges
can
unknown
element
the
needed
Figure a timing
increases
cycles,
in determining and
ta.
initiates
algorithm
value
information and
and
operator many
incorporated
calibration
timing
this search
the ti,
delay
the
over
At
td.
cycles
Generally,
provides between
input
then
A binary
the
previous
zero
cycle to
of ta.
the
adjusted
timer)
value
output
difference
presets
properly
of the this
the
77
pads.
sampler
so as to reduce operator
ARRAY
input
delay
delays,
etc.)
is shown
to the
input
and
errors
in Figure
output
of the
(due
to
3.12.
A
ta-delay
FEEDBACK
i I E--I
TIMING
,C CH,p/WAFE_ "-]
STOPI
-
t Figure element. that
3.12:
The
input
is subtracted
element
tao,t.
Differential timing from
This
the
differential
ta = tao,,t - tdin.
An application
pad
pad
Figure
driver 3.13.
and The
delay
receiver
delay
measurement
sampler delay
is used obtained
technique of this delays
is measured
technique and
to
the
timing
measure
from
yields
when
with
a baseline
the
output
an accurate to the inter-chip
the feedback
sampler.
timing
measure
measurement delay select
delay
tdi n
sampler
of the
delay
of on-chip
is illustrated
switch
is in each
in of
78
CHAPTER
_o
D
I_ J
3.
TEST
__-_
START [----
t RECEIVERJ
GENERATOR L Figure
3.13:
Measuring
FEEDBACK inter-chip
STRUCTURES
delay.
3.2.
TIMING
the
four
is the
positions. delay
positions and
SAMPLER
The
of the
2 and
between
1 output
3 measurements
pad
delay
as
sampler
one input C-element
occurs before a transition is a circuit that behaves
be
constructed
when
from
2 or 3 of its
output
as shown
digital
OR
C-element
when
C-element
or negative
measurement
The
setup
using
phase
C-element
places
will trip,
input
of resetting
the delay
and
to node
then
transition
delay
the
out
01.
the
output by
the
towards high), B both
static.
the
a
of a 2-input 3.14.
measurement
of positive
are
shown
phase
arming
in Figure
and
a measure
state.
In this
state
when
B. The
setup
the
A input.
to traversing of Figure the
output
state,
consists
For
positive node
For
delay
00
negative
to traversing
is sampled
the
a transition
through
input
3.15. phase.
phase
3.14.
corresponds
includes
C-element
like
for the
to change
phase
phase
through
period
(tin)
to see if it changed
when When
to the
MOSFETs
when
leakage
action
p-channel
paths
of the
capacitance
connected
n-channel
VDD
for the C-element is illustrated from a 3-input majority gate,
memory
C. This
inverter
towards
low).
measure
of Figure
The
and
of positive
diagram
the setup
The
capacitance
ground
transition
hysteresis. is low
measurement
input
then
is the
in the
is equivalent
CMOS implementation circuit is not constructed
of an
and
where
and
to the
that
behavior
an initialized
on
3 inputs
device
output
sampler
into
this
of the
is high
tin > td).
is not
capacitance
The
digital
the output
output the
The
of a setup
to a transition
10 on
period
A practical 3.16. This
vided
prior
causing
on
output
displays
its
diagram
timing
C-element
measurement,
(indicating
ure
the
whose
one
when
diagrams
3
if a transition
is a bistable
be used
consists
measurement,
11 to node
and
cycle
C-element
transition
can
Timing
thereby
A occurs
transition
a C-element
timing
state
its output
gate
is high.
sampler
delays.
since
positions
input. A 2-input Muller The Muller C-element can
connecting
AND
between
Sampler
(a circuit
circuit
trigger
by the
timing
delays
The
by
between
receiver.
changes
gate
This
its output
transition
transition
high)
as a 2-input
gate
output
2 measurements
difference
and
2 input
on the second in this manner.
3.14.
is characterized
The
state
are
of a Schmitt
behaves
2-input
node
inputs
delay
delay,
chip
majority
1 and
The
a Timing
whose
a 3-input
in Figure
equivalent
C-element
on
is a circuit
position
inter-chip
of the
C-Element
A timing
the driver.
is the
it is the
Muller
79
difference
chip
4 measurements
3.2.3
ARRAY
are
C-element
primarily output nl
and
neglected,
The
n2 are
MOSFETs
Pl
the
function
consists
node.
and
output
in Figtherefore
of the
output
on
is pro-
(A and P2 are voltage
input
is driven on
B both (A and remains
CHAPTER
8O
OUT
3. TEST
STRUCTURES
OUT
=
IMPLEMENTAT ION USING A 3 INPUT MAJORITYGATE
LOGIC SYMBOL
/-- NODES LABELED __
/
OOA_---.L---_,_O! / _k_O J/'l
011 Ol NC_
WITH INPUT (AB) _
"X _
II
)
BRANCHES LABELED WITH NEWOUTPUT
NC -- NO CHANGE
I TRANSITION DIAGRAM Figure
3.14:
Two-input
Muller
C-Element
as a timing
sampler.
3.2.
TIMING
SAMPLER
ARRAY
STARTo._,,-
STOP
tin_Vol
STATICCHARACTERISTICS OFSTATICIZER
5 _"
Vi2 _:,_
Vo2 _
DYNAMICCHARACTERISTICS OFSTATICIZER ...........
_........
Vst = Vinv = 2.12 VOLTS
4
0
3 it
•-. 2 _-; _i
2
>
..............
: Vst
1 !
o
i
2
3
4
5
0
20
40
Vil= V02 (VOLTS) Figure
3.17:
staticizer
consists
mission
gate).
switching
of an
When
the
threshold
element a long
Restoring
coupled to change
state
(metastable) is approximately
nodes. until
point
pair
the
staticizer
week
output
circuit
mutual one
can
exclusion
is off balanced transistor
with
feedback this
node
remain
exactly
be connected from
threshold
channel
output
the
the
feedback
nondigital
to Vu), to the does
its switching (11701 -
trans-
above/below
through
can still
circuit
a staticizer.
(long
V_l to a voltage
if Vii is initialized
staticizer
by at least 1 volt).
with
C-Element
will drive
exclusion The
of the
initializes
staticizer
(indefinitely
mutual
output
level
C-element The
of time
transistor
staticizer
logic
inverter
V,,t, the
to VDD/ground. period
the
60 80 I00 120 140 TIME (NSEC)
for
so a cross 1/-ol and not
Vo2
begin
threshold
Vow] > Vth which
CHAPTER
84 This
additional
a source
follower,
this
analog
dither
is used
approach
tested
array
circuitry to drive
is used,
as it can with
A parallel and
staticizer
digital
3.18).
C-element
timing
TEST
STRUCTURES
if an analog output
sampler
buffer,
voltage
off chip.
measurement
loop
such
as
When will
not
feedback.
of C-element
(Figure
is unnecessary
the
the
3.
timing
Although
samplers
a series
has
connected
been
designed,
array
fabricated,
is preferred
because
---_E_Y CHAINL28J_____
128 ----_- I MULTIPLEXER
OUT
-.._ DELAY CHAIN3 J )--- _(!!_,__
H,,
When following
rising
delays
to the
whereas the second and to the fact that (Hp
edge
feature
the
be attributed
node
to falling
3.
than
inverter
the
failing
input
for
edge
Cp
a given
delay.
pair,
as a load
sees two inverter inputs as transistors are slower than
differences
denominator
is that
of each
which
This drives
(fanout
= 1),
a load (fanout = 2), n-channel transistors
in mobilities).
the tau model is applied to the loaded inverter rising and falling edge delays are obtained: 1
Awa
pair
of Figure
-
Awb
t_f = Hj, L2[1 + -r + rW-L ] + H'L2[f(1
A_a. + r + _{
tdr = H,_L2[1
the
3.20
inverter
STRUCTURES
3.22,
the
]
+ r) + WL'
1 + r)
+ Hpi2[f(1
Awb ]
+
where - Ap._C'p + A._,_C L + A,,_C_ Cwb Awb
--
-
C*o_
t
Cp
L = Ln = Lp = Lo -
ApbC_
+
C"
C._ Cg_'
AmbCtm
A L,
+
AdbCld
, Cd
Cd Coz•
W = Wn = Wo -
AW
and Wp = rW,, The
interstage
wire
capacitance tance
Ap, A,_,
and
(Lo/Wo)
using
primed normalized sionless. written has
been
the
where Aa are
by the
metal
areas.
capacitance Both
is divided
C_, C_,
AL/AW oxide
of the
C_,
C_,
capacitance equations
units
and
as linear
equations
in l/W,
used
to fit the
as-measured
to the
electrical area
inverter
where data
above
unit
delays
rising
and
capaciarea
and
lengths/widths (L/W).
equations
C_,, = eo,/To_ pair
polysilicon
diffusion per
as-drawn
(W = Wo - AW). for
the
lengths/widths
C_ in the
per unit for the
and
the
of capacitance
are made
the true
components:
(A,,_C,_),
C_ have
Corrections
w./L. ......
into three
capacitance and
to obtain values,
Wp/Lp
c-.- c}:Lwo: ",
capacitance
(ApC_,),
(A_C_),
Cp _ C_,,LWp
'
have
and
been
are dimen-
t4f and A fitting falling
The
t_, can
be
procedure
output
edge
3.2.
TIMING
inverter
SAMPLER
pair
delays
Lo, Wo, r, f, values
(tdp and
Ap_, A,_,
for H,,
Marquardt
Hp,
ta,
Au,,
AL,
algorithm
!
AW,
=
rising
t.5_m
ratio
=
i
5O
in doing
Hn
=
0.0157
Cp
=
0.063
0 Vdd
fanout ,HD.= Cm
C_.
this
i
edge =
and Adb to the
!
l
Zarnbda
in Figure
Up, C,_, and
used
i x
as plotted
Apb, A,_b,
was
S0
89
ARRAY
The fit.
falling
=
5V
=
2
model
equations
finite
the
parameters to obtain
difference 3.23
i
Levenberg-
shows
the
results
i
edge L=11.72 _/^
0.0284
=
and
Figure
I
=
3.20)
//
0.253
Cd
=
0.233
/
Je
.c 4O DELTAL
=
0'281
__
0J o L 30 n c.
"220 > c
10 L=2.72
0 .06
I
I
I
I
I
I
0.14
0.22
0.30
0.38
0.46
0.54
I/N-CH
Figure
3.23:
L are
in units
of fitting
the
is plotted from the
Timing
the
and
raw data
against
1/W.
C_,
C'
The
where
equations. lines
using
has
data
Width
0.62
[1/#m]
H is in units
of ns/#m
2, W
and
is dimensionless.
fits the data however,
Effective
fitted
to these
equations
plot. The tau model
parameter
sampler
of #m,
model
Transistor
drawn
the
very an
In this
figure,
through
the
extracted
the data
parameters
well considering unrealistically
inverter points
shown
its simplicity. high
value.
For
pair
data
are
derived
on the
top
The
extracted
the
particular
of
!
layout
of the
timing
sampler,
C_
should
be less
than
C_ and
Cp.
The
values
extracted for the three parameters C_, C_, and C_ are not accurate in a physical sense because the changes in inverter pair delay due to the differences in metal, polysilicon, very
small.
and This
diffusion presents
capacitance a problem
from
one
in the
inverter separation
chain
to the
of these
next
parameters.
are
90
CHAPTER
Another
cause
capacitance
was
3.2.5
problem
not
is that
accounted
the
periphery
for in the
timing
peatable
sampler
is a compact
measurements
ring oscillator
external wafer
approach
inputs
coaxial
STRUCTURES
component
of the
aspect
The
delay
used
to characterize
of the data
circuit
3.3
proper
timing
from
gate
designs
over
the
high
wafer
and
with
direct,
the
tau delay
of some
special
outputs.
Only
two
card. it can
to accomplish Another
posi-
be multiplexed.
sampler
array
geometries
can
be
employed
in
model.
Structures
Introduction
The design rules, which are related to the spacing not adequately tested by the common parametric split-cross-bridge
resistor,
deficiency,
of very
a set
contact
3.3.2
Structure 3.24
shows
resistors,
simple
CRRES fabrication run. based on diode breakdown
between different test structures
transistors,
structures
was
etc.
developed
These structures, which use voltage, are termed collision
layers, are such as the
To overcome and
differences
for
the
only two pads test structures.
and
are
Geometry the
between
between shown
source-drain
this
tested
geometry
of the
collision
structures,
with
a cross
shown of each. The distance d was varied from structure to structure. case, d represents the "as drawn" dimension. It should be noted that
region'
of to
is easy
timing
re-
amenable
this
of device
and
limitations
is also
probe
which
compact
a range
circuit
speed
on the
ease
a single
delays
using
no
terminations is the
fast,
measurement
are
to the
allows
It overcomes at the expense
delay
there
sampler
obtained
that
delays.
measurement
to be applied
and
structure
sampler
because
Proximity
3.3.1
vary
diffusion
model.
circuit
to delay timing
need
cables
tive
typical
The
measurements
speed
using
test
of on-chip
hardware. level
high
Figure
TEST
Conclusions
The the
of this
3.
devices in the junctions
fabrication
processes,
manufactured cross
by different
sections
of a MOS
the
refers
transistor.
to
actual
physical
section
In every because of
dimension
fabrication
houses.
The
a thin-oxide
region,
such
d could 'Active as
the
3.3.
PROXIMITY
.....
STRUCTURES
91
°°,°
P-WELL
PAD
PAD
TO
TO
PAD _
TO
I ACTIVE
[]
METAL
i._i
P-WELL
El
ACTIVE
•
CUTS
:':
p+ DIFFUSION
ACTIVE
ACTIVE
,,.
Figure and
3.24:
Collision
diffusion-to-diffusion
Test
Structures breakdown
for measuring voltage.
p-well-to-diffusion
(active)
92
Table
3.2:
Diode
breakdown
voltages - Diode
- Spacing-
p-Well
lambda 5
diodes
3.3.4 These turer area
p-Well
Voltage
to
p+AA
n+AA 48-50
Test
Structures.
(Volts) to
-
p+AA
n+AA 33-34
to
6.0
8-15
49
33-34
34
2
3.0
0
35
32-34
33
1.5
0
31-49
0
0
-1.5
0
27-0
0
0
p+AA
--
p+
doped
active
area
n+AA
--
n+
doped
active
area
Experimental
sulting
Collision
STRUCTURES
4
Notes:
of these
of various
Breakdown
TEST
p+AA 48-50
1
A set
3.
/zm 7.5
-1
3.3.3
to
CHAPTER
Results
structures measured
p+AA 33-34
was fabricated by applying
and
the
a reverse
breakdown
bias
voltage
to the junctions
of the (Table
re3.2).
Conclusions structures
offer
a very
can comply
with
the
and
well spacings.
rules
that
can
could
establish
be met
simple
agreed
It also by wafer
a set of rules
method
upon provides vendors.
for this
of verifying
that
set of geometrical a means Based
particular
design
of determining on
the
a wafer
above
manufacturer;
manufac-
rules
for active
a set
of design
test
results,
see Table
3.3.
one
3.3.
Table
PROXIMITY
3.3:
Design
STRUCTURES
rules
93
_
for manufacturer
as indicated
by
Collision
tures. Design
Rule
Name
Design
Rule
p-Well
to p+Active
Area
8.0/_m
p-Well
to n+Active
Area
7.0#m
p+Active
Area
to n+Active
Area
3.0/zm
p-t-Active
Area
to p+Active
Area
3.0/zm
Value
Test
Struc-
ORIGINAL
PAGE
IS
OF POOR
QUALITY
CHAPTER
94
3.4
The
Split-Cross-Bridge
3.
TEST
STRUCTURES
Resistor
IEEE
1572
IRANSA('II()NN
{JN ELI_CIRt)N
DEVIfZI_S.
VOL
ED 33, N[)
IO. O(I()BER
IV8b
The Split-Cross-Bridge Resistor for Measuring the Sheet Resistance, Linewidth, and Line Spacing of Conducting MARTIN
Ab_IrocI--A spacing
new
bt'tween
measurement measure
lest
ing
laser.
ture
_a_
Th¢_e
I.ising
an
value
measured _ alum.
pileh
ing
_alne_. on the
sured
and
are
results
line
lir_
pre_nled
sheet
confirm
is used
_paring
sheet
resistance,
electrical
mea-
lest
Iine-
_tructnre
techniques
a
measuring
described
here rules
be
quickly
used and
to
of on
an
parameters
cross-bridge resistor.
linewidth
elec-
based
the
designed
techniques
can
of
extension is
which
split-cross-bridge
measurement
an
re-
Alternative
and
spacing
121.
The
evaluate
are test
based Fig
structure
I
Spilt crl_ss line spacing
integrated-circuit
accurately.
°r
the
spacing is
in
specially
measuring
and
technique
the for
visual
line
approach
I I I measurements
from
termed
j to
and
The
measurement
layout
abe
approach
linewidth,
determined
on
the
resistance,
I[)N
an
lines.
resistor
sis,or,
_ature
between sheet
designing
INTROI)U('I
describes
conducting
cross-bridge
are
for
designed line spac-
_elf-cbecking
difference
to validate
Rule_
and and
in detail.
PAPER
trically
_lructure's
i small
values.
I. HIS
the is,
the Most
of Ihe
linewidlh,
Thai
thin
layers.
Ihe me=sured
pilch
the_e
Ihe optical
I/¢reent
between
line
struc-
2
resistance,
pitch.
designed
and
difference
HERSHEY
to
metal
within
W.
layers.
and
greater
and
were
Ihi_
u_,ed,
micromeler
pc_13,_ilicon valne_
CHARLES
cnnduct-
metal
rlectrically,
lecrhnique_
_.ND
line
used
of the
and
IEEE,
electrical be
prt_ess,
sili_nn
the
the
an
also
pitch
and
one-quarter
pitch
Io validale
Ue_l
based
_idlh,
A _mall
i_ u_ed
using can
fabrication
ftDr the line
by
rand line
For
typically
measurements
electrically
MEMBER,
ft_r evaluating
layer structure
i,plieall)
compared.
_ere
ele_lrieal
lint
_ame
pcdycry_lalllne
measured
were
mei_urelneJil_
developed
the
linewidth,
in difru_.ed _ere
BUEHLER.
compact
inlegraled-circuit
fabricaled
measured
_a_
on This
re_i,,tance,
_lru_ture_
designed
_trncture
conductnrs technique.
the _heet
G.
Layers
The
technique
bridge S. and
re_islor designed I_1 evaluale Ihe sheel resistance R, _la conducling
by
polycrystalline form
of
critical
silicon, these
test
To
illustrate
are the
Was polysilicon
is
resistor, the
the
lower
Manus,:rlpt The authnrs of Techn,dog3,. IEEE Log
in
Table
I.
evaluate The
in
spacing
structure is
a
upper is
a
split-bridge
December Ig. 1985. revised the }el Propulsion t a_ralol_y.
1
CRITICal.
G_O_ETrlC_L
DIIdENSIONS
ANI) V_'II _AGE TAP
ERI_ORS (E_)
the Fig.
I,
between resistor
The
RESISTOR
their
consider
line
SPLIT-CIIo_,S-BRI[XII_
The
1 and
split-cross-bridge
middle
Pasadena. CA Number 8610062
Fig.
shown
the
metal,
layers.
principle,
structures.
structure
re°e,red are with
shown
in
in
silicon
resistor
to
three
structures
diffused
listed
lines of
test
measurement
designed
combination
and
and
split-cross-bridge
which
cross
14
structures
dimensions
polysilicon
two
fabricating
½'.
was TABLE
demonstrated
linewidlh layer
structure bridge
is
a
is
a
resistor,
resistor.
The
May I. 1986 California Instilule
91109
0018-9383/86/1000-1572501.00
% - _0
_,
% " a'_
_"
bridge
resistor
Wh
=
2W
has +
ducting
channels,
fective
width
©
S.
single
IV,
IEEE
conducting
channel
split-bridge
each is
1986
a The
=
resistor
with
a
2W.
The
width line
of
of has
W
spacing
so
width,
two that S
conthe
is
ef-
deter-
ORIG/NAL
P,_E;
i3
OF. POOR QUALllV
3.4.
THE
SPLIT-CROSS-BRIDGE
95
RESISTOR
1573
BUEHt_ERAND HERSHEY SPI.IT.CROSS BRIDGE RESISTOR
mined
by
(W,
=
2W
q S)
subtracting
2W)
II. the
are
ships.
by
from [3[,
is designed
the
potential
/, passed The
=
out
rectangular
the
into/t
voltage
taps
be
In the analysis,
using
the
and
this
simplified
is - r _1 -",llt,_
van
S =
the -I I --
Yh is V,
-
The
=
2W
between
specified of the
the on
is determined
width
1b1
the
from
split-bridge
R,L,I,/V,
Fig ] Cross sectional diagrams of two diffused layers formed (a) b:, a uniform oxidation, diffusion, oxidation process and (b) by a local-oxidation, diff'asion, oxidation pt_ess where crmcal dimensions are tndlcaltd Intermediate surfaces a_e shov, n by dashed lines
(3) measured
where
the potential
/, passed voltage that can
Ii and
into taps
difference
is L_.
Note
no significant be
The
taken
S = where For
Wh -
and It, =
the
design
expression
the sheet
resistor
that
The
magnification
as their
general
V, is V4 -
Of I_.
out
IV', =
distance
a current
between
above
equations
occur
so that
line
size
the
require Lb and
L,
-
is
L,I,
features
during
eral
from
(4)
I and
Lt, =
L, =
R,LI(V,
-
[inewidth
ingI,
=
is calculated
landL,
=
by
and
line
P, =
W + S =
Thus, uate sheet
the four
R, LI(2V,
-
split-cross-bridge critical
resistance,
S,
is
A
physical
linewidths
line
MEASUREMENT model
and
spacings
the
visually
was
)inewidth
and
wafer.
spacing
of a layer
on a fabricated in the location
as
determined
made
on
mea-
wafer. of a feature
from
visual
measure-
photomasks
and
fabricated
the
difference
in
edge as determined cal measurements
can
(7)
be
used
to
layer,
and
line
and
relation
that
these
2 illustrates
the
location
of
from visual on fabricated
silicon
(poly)
layer
where
served
on
wafer
(W,
(Wp)
on
the
features
poly
layer.
point
in
layer.
the the
the width or
photomask.
at the The the
parameters
the fabrication
i.e., pitch.
compares
or wafers
among
3. Fig.
eval-
INTERPRETATION
developed
of a feature
a fabricated
a feature
and electriwafers.
(W/2)
spacing,
of photomasks
spacing
on
wafers. is
arbitrarily Ill.
linewidth
sured electrically is the difference
is determined
of a conducting
linewidth,
the
parameters:
assum-
V_)/(2Vbl/O.
resistor
parameters
deposited
requires
ob-
The =
of
model
and
(6)
Wh -
features
The
lat-
is the
ments
features
of
of
etching,
W_,, S,_
edge
P, between
or lateral
fabrication.
to a
shrinking
ob-
L
pitch
coating
and
The due
and spacing of a feature on a photomask.
X the
linearly
bloating
making
eight
techniques.
is the linewidth served visually
(5) (3)
as the
the
served
modifying
electrical or contract
Wp. St,
L. then
W = R, LI/(2V,). Finally from
and
of the following
V The
such
wafer
during
the cross
Vb)ttVbV_)
or
expand
photomask
diffusion,
W,, S =
visual
may
of factors,
use
Vb)I(V_V ,)
R, is determined
either
number
(l). 1, =
by
of a feature
layers spacing
e,(Lb/hV,
resistance
V5 for
values. for
-It7
V_ for a current
distance R,
tt
(2)
is the distance
(I). from
from
R_LhlJVh
resistance
W, =
t])
is determined
of 1_. The
which
the cross resistor and resistor is determined
s_ -'t, $1 -rl _1 "r,lt _
a current
expression
+
out
sheet
2>
resistor
difference
The
ta)er
ig-
of l F
2W
and
is Lh,
photomask.
can
V, is VL -- V 2 for
resistor
potential
Ih passed
-
Fig 2. Cross-sectional diagrams of a p.)lycr_slalltn¢ (poly) qlicon and a photomask where critical dtmenMons are indicated.
for geometrical
is needed,
tV.-/I,)tT/In
of the bridge
w h = where
resistor
lltcm
relation-
section,
properly, layer
difference
into I T and width
idealized
measurements,
14] equation R,
where
in a later
cross
(W h =
idealized
are uncorrected
R, of the
the
tLU$
resistor
resistor
electric_al
following
as discussed
resistance
Pauw
the
split-bridge
bridge
TECHNIQUE
three
relationships
calculated der
requires
if the structure sheet
of the
of the
MEASUREMENT
which,
nored
width
width
illustrated
These
errors, the
the
technique
which
the
from
base
length
of
The
visual oxide,
width the
ofa
layer
than
width which
2
W,,
describing
ob-
the width is shown
surrounds
IV, is shown
trapezoid
in Figs.
polycrystalline
of the poly
W,,) is smaller
of the
electrical
is shown
at
the
the
mid-
the
poly
96
CHAPTER
1574
IEEE
TABLE CfyMPARI'_ON
OI
tRANSACTIONS
ON
3.
ELECTRON
DEVICES.
aND
Fig
4 due
The to
crn,r
shot1
in
: _vaF
eq
Keeping
the
2)
As
oxidation,
illustrated
planar
lateral
diffusion
and
the
reversal
of the
W_, and W,
-
W+ (line
2 (line
pitch).
smaller
than
larger
than line
spacing).
For
spacing. pitch,
formed
+
the
V and
that S,.
have
is the lines,
in photomask
be used
S were
correctly
value
between
and
or
IV, is
apply
significant
in Table
it can
distance
is.
are
kind
be
IV, +
of edge. the is not
and
processes
because
both
to verify
provided
that
be
the
by
edges
ruled
design
are
out.
then
values
for
test
in pitch)
occurs,
then
L,
the distance
the voltage
a change used taps
for must
L_, and be
and
were
equipment.
and
measured-visually.
+
W and
parametric
the
the photomask
not
W,
cro_s error
cqualion
resistor
that
If these
[5,
are
follows
rules
in Section
are
II can
accurate was
are
fol-
be used
within laid
one
per-
out
squares
at
that
in Fig.
two
angles.
calculated
accurately
expression
a detailed
analysis
of this
is shown
is slightly
[see
by
in Fig. than
less
4
the
from
The
true
the
This
structure
rule
idealized
rule
141;
#1
be at resis-
follows
the result
R, as calculated
sheet
80-
equal-width
Design
(I)).
it
N is
I, N =
separated
from
right
so
151where
array
As illustrated 80-#m
is constructed
of
from R,,
resistance,
as
by R_ =
where
E]
curve
in
is the Fig.
R.(I
geometrical
4,
the
#1 requires
-
E_)
error.
error
for
18)
By
A
>=
extralx)lating 2Wis
to the split-cross-bridge that
A >
tion of the structure.
or
are af-
features
Greek
get_melrtcal Pau_
the
seen
to
be
negligible.
linear
shrinking)
given
intersect
be
As applied
by be
resistance
given
two
on
(or
R_ to
sheet
the analysis
not
implemented
cannot
tance
example.
affected
resistor
IV,
of
der
requires that the length A of each arm of the cross least twice the arm width W in order for the sheet
in
between
edges
the
the
van
the
rules.
integer.
pads
that
from
line fea-
S, are
For
left
(bloating
can
that
distances
features fashion
seen
tr_m
ehrninales
a 2 by N probe
positive
cross
to
II deserves
means that the measure of the
That
between
this
correctly
magnification
table
they
If magnification
measured
layer,
are
St,. This is a direct
same
identical
S, can
sign
+
photomask
fabrication in an
magnified.
IV,/
of the layer
comments
listed
X because the
changes fected
Similar
the
distance
parallel by wafer
The rectangles
a diffused
resistance W
from
resistor
with
the probe
quantities
(I)
From
on
by
features
an arbitrary
quantities:
IV, is larger
2
split-cross-bridge
#m spaces.
in the table.
sheet
>
design
results
is the sign
W_,
'k \
split-cross-bridge
to obtain
be probed
derived
discrepancies
$o = Wp electrically
1g1¢6
CONSIDERATIONS
the
equations
4, and
and
W b -- (W,/2),
discussion.
OCTOBER
|1
Ihe
DESIGN
of the
structures
(linewidth),
for
2X.
Such
+ S,. = W,, + pitch measured
affected
+
could
processes.
line
special
W,
2V
I0
cent.
measured
three
on the nature
example,
IV,, by
manufacturing The
be seen
poly
structures
The
with
W,12
As can
formed.
tures
X terms. along
IV, or W e depending
being the
V and
W, are shown,
and
tTr
re_i_lance
geometrical
then
The
metal
for diffused
four
directly
a fraction
among the eight paramNote that the difference
for
design
lowed,
IV, includes but
The
as well.
equations
equations
Nf)
11) t
from
process.
width
diffusion
relationships in Table II.
upper
the lower
of the
by
process
oxidation
the electrical
region
The mathematical eters are illustrated between
3,
portion
layer
oxidation
diffusion,
in Fig.
the
of a diffused
diffusion,
a local-oxidation,
not only of the
formation
A
,heel
IV.
or by
ED]3,
I w/u2L
al
measuring
arms
+n calculatin_
I'1 a uniform
STRUCTURES
SP_(INGS
II
either
QUALITY
]l
[ANIwlDTHS
the
OF POOR
VOL
11 _ Isl II
3 illustrates
PAGE
TEST
II
Fig.
ORIGINAL
If
the de-
Wb) rule structures
in a CMOS
The
a suitable sistor
A/W_,
and
constructed two
places
design
ratio
following
rules
the
to
A > =
lateral
to
be considered.
design
rule
bridge
por-
than
A
diffusion may
(such have
as a p-welt
errors. to both
the bridge
resistor.
Bridge
resistors
oftbe
> =
to calculate
applies
a conducting the length
and
the design of diffused is a factor. Ira structure
minimize
split-bridge
cross
2W_, (rather
the designer
discussion
from along
the
to include diffusion
large
process),
resistor,
2W;, for
was chosen wh¢re lateral
has an excessively
The
=
channel
that
channel. They
include
reare
is tapped
There
in
are three
the distance
iS
ORIGINAL
PAGE
OF POOR
3.4.
THE
SPLIT-CROSS-BRIDGE
BUEHLER
AND
HERSH[_Y
SPLIT-CROSS
iS
QUALITY
RESISTOR
BRII_IE
97
RESISTOR
1575
_v t
_i
,
7,//
O_
|
!
•
,R/ll
11 6
Re_or
model
o!
uhc
br}dge
duced
Design
rule
the current 0
O1
17
_A 5.
The
tO
error
m
measunng
pc_orballon_,
in
Ihc
lh¢
line_idth
channel
Imm
current
a
flay,
at
briog¢
the
sti_cturc
v_dtage
due
lap_,.
tap
rately
from
sion
and width
the location width..
of the tap
Design taps
of the taps,
rule
#2
distance
L between
the
channel
width
This resistor
(W
is much
larger
dicates taps
is
that
its
D of the
large
(W
that
so
that
from
the
= R,L/R).
of the
is calculated
the
results
161 where His
of a bridge
[6.
of the
eq.
between
the
resistor
The
tap for
error
In(I
D/W
voltage
and
(D/2W}
(D/(2W)):)I.
=
(10a)
is
an
as calculated tion
(see
The of the rical
from (lOb)),
distance
From
L
( 10b)
the
this
voltage
taps
and
D is
expression -
W,/(I
error
E,3
taken
as the L_ =
error
this
(ti)
less
than
errors for
split-bridge
layer, one
The
half
but of
allowed for
for
1 percent.
this
resistor
the true reduce
equation
much
longer
that
equation.
The
parameter
"'g." current
(12)
(W/gD)I
(13)
that
than
equa-
width
For
the
voltage
where resistor
The worst
errors case.
W,. taps
design by
structures taps
L_ =
I,
E2, is the
are worse the
inwas
error
for is
rule
for
from
a discontinuity Fig.
7.
sity
J(x)
(W
The
in
=
width
a detailed
analytical the r-axis
is
the
requires
means
that
the
larger
than
re-
which
should
taps. of a voltage a change
W to be
to the
applied rule
allows in the
of current channel
161 for
tap in the
calculated
As
of the
expression
shunt
channel
analysis
width
to
from
shown
ap-
indicates
rectangular
1, this H,
good
edge
width
is
confor-
rule
0.18}. the
the
R,L/R). Fig.
This
g
that
H h and
in the
along
2D.
=
channel
=
serves design
I 1. I times
tap
from result
is
uncorrected
distances
follows
HaWs
the
is a very
tap
> =
where
This
The
channel
the
shown
the
from
derived
0. t8.
to terminating
the
expression
tablish
G G/D
requires the
from
was (13)
=
(G*/D
due
twice
cross-bridge
a value
_f E_ versus
I (DJ2W)
case
of the
length
#4
width
gD.
{14) the
channel.
model
rule
tan
and
g
for
errors
accurately sistor
160 tun
in Table and
the
=
finding
a plot derived
Equation for
main
tap
quired
to
fraction
the
requirement
channel
by
G*
(D/(2W))")I.
width
(14)
design
be located
+
its
a small
Design
evaluated
expression
theory.
from
the
where
is applicable
to
only
is G*
= t2/r)[(D/W)
In (I
mapping
current
W,
the geomet-
the
E 2 are listed
the bridge resistor.
even
of
that
of the voltage
to
amount. width
width
error
than width
chosen
the
indicates
rectangular the
were
minimum
This
larger and
study,
140 ,urn.
for the metal
idealized
is slightly
E:b is the
the
width.
to an acceptable
in
where
the
resistors
cluded and
channel
between
bridge
ma3or
(48}1
(L/W)Ez
This
minimize true
model
Each
in diverting leads to
fit between
analytical
proximation
(R JR)
between
tap.
W = W_ is the
expres-
resistor
the
D
accu-
E_]
+
was
a good
16, Eq.
E._ =
(9)
"g"
provides
tan-I
width
L is the distance
where
6
resistor
R,[(L/W)
from
a resistor
Fig.
is to determine
tap length
parameter
E z is
+
channel
of the
in
the effect of the tap The resistor model
model
g that
that
width
m
width
resistor
an equivalent
E_ = (D/W)/II
(48) I in-
-- E_)
(2W/rL)[(D/W)
W where
model
the
be calculated from
rectangular
R =
real
the
follows
as shown
the
ctror_
G of a tap twice
rectangular
rule
t'_lrma_c"
where
The
of conformal
the length result
R,(L/W)(I
geometrical
uncorrected
length
W to
is assigned
from of the
equation
-
This
of the resistor
objective
width
the bridge
bridge
by
E2 =
The
for
the
be at least
uncorrected
= R,L/R).
io
lap'_
that
channel
u_ed
bridge
channel
the
which indicates from the channel
voltage and
enough
accurately analysis
upon
the resistance
the
channel
allowed
expression
width.
R = where
and
requires
the
_trt/clurc
by
5.
by Hall
than
is given
be
a detailed
based
described
taps
resistor
in Fig.
analysis
mapping
width
in the
for
developed
of the taps,
width
be calculated
from
shown
This
the
can
follows
the
minimum
rectangular
rule
length
to a change
that
at the
the
uncorrected
relative
requires
be designed
the
#3
carrying
of the
area between
1,
t21 Fig
Fig,
"
1/11 _ 1 |1
resplit-
one
to es-
figure.
This
flow
as shown the
current
past in den-
CHAPTER
98
lEEk.
157h
tRANSA(
tH)NS
()N
lions 27
_0-
_
_
,w[
'
','
between
('Q'
values
is required
be
denxH),
_hange_
_ldth
ol
culaling
the
ahmg
v_idlh _rtHn
hn,:v,
NiItOlll
Keeping
channel
the
Ihc
ldth
lap_
voltage
the
of
edge
a
conducting
a distance
that
nlinlltllIC_
th_tt_nl_llLIl[},
latyc[ ix Iv,
Ihi_
Ihal Ihe
ice in
error
cal
the
the
the width axis is
ol
ratio
oped
the
larger
width
of the
channel.
_- =
[in (a/h)
a
_/-I +t
The
,fln
smaller
channel
distance
along
to
the x-
(c/d)l/a-
(16a)
The
+
,_1-_-let
of
14 different
arc
the
poly
a_,/t
(lbe)
given
equations
eqs
t40)
results
densit.',
settles
channel
uut
and
the
is conservative
is.
the
(17) from
the
HaWs
equations
16,
2 tanh
_ (:.)
Iransfi_nna|ion
:_l.
four
The
14" shown
Fig.
7 indicate that
is less
the discontinuity. large
channels.
wilh
re_,pecl
in
Fig.
that than
This
that
large
7 is one-half
current
twice
is tree
Notice to the
the
width
of the
the
EXPERIMEN'IAL
tance III,
and 131,
the
electrical
171. These
to be measured the channel rors
and
tion
of
by
Also.
the
resistor
resistance rents I: and
voltages the
sheet
should
forced
voltages
measurement
measured requires
due that
to
ttA
for
dioxide
of
the
apparent
this
oxide
varied
were
and
between
eliminareversal
requires
V_ and
to be lotted
point V,.
The
in both
is from
off
properties
by
a muhiposition was
was
test
were
the
image
structures focus
removed increasing
The
amount
controlled of each The
of
and
thus
structure
were
following
proce-
errors
while
of the could
linewidth
(2000× chamber
field
Instead.
of focus,
change
the
x)
voltage
never the
by since
using
the moving
selected
magnificaan
NBS
electronic
NBS the to
stanfocus
standard
and
sample
into
electronically
magnification
pressur-
was
as
used
magnifica-
discrete
by (such
a
standard
high
Magnification
calibrated
one
5000
affect
Each
in
session
the was
could
enhancement focused
each
and
began,
only.
used.
taken
of an NBS
the
SEM.
were of
as this
therefore
compensation) and out
lines.
chip
session
switch
curother
and
of the
dard.
direc-
was thus
beginning
values the
re-evacuated
four
I_ and
taken
Once
turned
each
the
magnification
No
linewidths
magnification
of At
was
study.
value
silicon
removed
photomicrographs.
tion tion
minimize
layer.
In the process,
lines
a SEM.
the 200
the poly
oxide
lines
m
metal
and
layer
The
for
layers,
the
field
to chip.
were
500-,aA
patterns.
these
this
structure
chemically
metal
strictly
session.
never
was
not
photomicrographs
this
for
sysFor
electrically,
grown
using
measure-
prober.
oxide.
was
used
these
ized
between
chip
run.
measured
acquisition
each
5 mA
of
chip
each
electrical
n ÷ diffusion
of the diffusion width
gate
first
data
gate
on
the test from
were
structures
thermally optical
from
layer
chosen
resistor
oxide
poly
wafer
to expose
photographed
was
of
chip
removed
[81 at both
er-
average
test the
errors
the
passivation
the edges
to eliminate
as determined
protective
field
p'
through
and
the
photomicrograph
voltage
The
diffusion,
split-cross-bridge
in
current
p*
on
fabricated
and
de-
n _ diffusion oxide),
The
on
a 3-
were
(thin
an automatic
measuring
each
along
measurement
directions
currents
bridge
the
After
layer
structures
oxide
arranged using
oxide
controlled
field
the con-
gate
and
optically,
polysilicon
on
with
layer,
poly
of
devel-
comparison
metal
forced
were
of structures
randomly
using
firr the
continuous
elsewhere
then
linewidth
resistors
on
these
1 mA
directions
relays.
from
resis-
instrumentation
the
resistance result One
in both
the
at switch
aSSUlnes
detailed
in both
is intended
offsets
measurements.
to be
require
flowing
procedure
errors
accurate. cross
current
voltage
Ihermal such
are
procedures
for This
intrt_luced
linewidth
sheet
on
a computer
polysilicon
All the
were
currents
RISUI.TS
fbr evaluating
oxide,
the test
taking
procedures
a signifi-
fabricated
manufacturers
study,
dures V,
field
chips
were
then
Measurement
test
with
from
resistor.
on
different
and
some
rule
layer
made
the
That
are can
associated this
sizes
n*
poly
ments
for both
design
layer,
n"
electrically
of the
channel,
are
optical
were
layers:
linewidths
from
in
in a distance
from
#4
bridge
derived
shown
"_,idth
small
exp(-2ul.
(41} I using
+ z)/(l
The
the
v, ere
and
Inl(l
-
equations
by t =
These
the above
layer Two
for
structures
of seven
diffusion
tl6d)
link
effects
errors
Two
oxide),
, : ,/i _/:, + r_q-_5 it that
various
effects
procedures
used
process.
p+
and
t and
bulk
(thick
(16c)
parameters
the
forced
measurements
split-cross-bridge
These
layer,
tem where
chip. each
¢, = ,;1 + t - I,_ + f>; + r
P, from
to avoid
the
The
magnification
for
oxide.
/,/i
and
These
of these
below.
structures
signed
(16b)
+):7i
be-
resistance
the currents
Additional
measuring
given
test
,am CMOS
p+ =
for
are
to minimize
sisted
of the
S,
be adjusted
if any
procedures
layers
on a test whercfis
W,
Iqg6
measured
of eight
as self-heating.
in [7].
(X'IOBER
factor.
SEM.
tb)
tnmL
I(I.
voltages
R.
must
to determine
NL)
In addition,
such
at length
The
ahmplly
structures
ED3_.
A minimum
to measure
PAGE
QUALITY
STRUCTURES
VI and
1_ and
131. [7].
effects
used
cant
('un'enl
I,
VOI.
resistor,
the
discussed
"_-_'4'
7
points
V2 and
interference Q r ""
TEST
DEVICES.
tween
through
FJ_
Eli(IRON
split-cross-bridge
I( P4
3.
ORIGINAL OF POOR
changing an
unknown
IS
ORIGINAL
PAGE
iS
OF POOR QUALITY 3.4.
THE
SPLIT-CROSS-BRIDGE
BUEHLER
ANn
HFRSHE'f
SPI.ll
('RIISS
99
RESISTOR
BRIIX;_
1577
RESISIOR
p
value.
For
this
of electronic For
the
were
analysis
purpose
low
of obtaining
clear
at a tilt angle
The
tilt axis
was
a SEM
with
magnification pictures,
resistor
one
of
the
graph
structure, two
i
to the elec-
data
sured
Some
oxide
all
error
unreliable
and
points
with
Therefore,
data
Vu,ual
versus
electrical
plolted
along
is given
above
_*_th
linewtdth
hnear
the
line-
were
TABLE V_*,I
al
P tl',,
LI_
MI(
_II)TH
R(IMF
Rtt
[I
R',)
graphs vernier
using a vernier caliper pro'_ided readings in
width
of each
near
the
top
segment
and
micrograph. from
line
of the
bottom
This
each
the
and
resulted
in the
in
in three
or
six
The The
the were
was
calculated
certainties The
based were
were
the
used
vert
the
each
for
a11 ¢1.
and
Vit
The does
Subthreshold dashed not
characteristics line
change
indicates with
for how
radiation.
the
a p-MOSFET characteristics
at shift
radiation if Vot
levels changes
5.1.
MOSFET
SUBTHRESHOLD
PARAMETER
_--_-F_/2$ RAD LEVEL
_I I
RAD LEVEL
OZl._VTf0(e2
f _1--2
_ f-_'_Vit_"_
VTf0(_I)
_I_F2-,_
=I=
_I 2_f_,J )
121
EXTRACTION
=I I =
-Vot-_
vit-----I -Vot
|
LOG(IBinv)
LOG(IB)
LOG(I Bmg) GATE VOLTAGE, VG
Figure
5.4:
¢2 > ¢1. and
Vit
Subthreshold
The does
dashed not
characteristics line
change
indicates with
for an how
radiation.
the
n-MOSFET
characteristics
at radiation shift
if Vot
levels changes
122
CHAPTER
5.
DEVICE
MODELS
AND
SIMULATION
DRAIN D' ID
IB IA
,Clo
GATE G'=G
VD
BODY
UD
B'=B
VG_...__ UG
S' SOURCE Figure is R.
5.5: The
The
model
of an n-MOSFET
subthreshold
leakage
where
current
passes
the
drain
through
and
the
source
resistance
drain-source
diodes.
Figure 5.4. These schematic semi-log plots of body current versus illustrate how the subthreshold current varies between the onset
gate voltage of inversion
(IBinv
is located
the
where
middle
is at VG
mid
gap
= VT,
oxide
VG traps
and
to higher of positive in Figure
ID,
and
the
S'.
Thus
ID
VD
and
UD
enters = IC
where
voltages traps
the
For the
the
with and
shown drain
The
intrinsic the
exits
the
the
IB
slope.
interface
gate
and
while
at
a smaller
IB,
the
voltages in Figure
tap, the and
intrinsic
Fermi
Von.
and
saturation
5.22,
Thus
region
VG
or a new This
[28] and
IB
only
but
current must
developed.
the
the
IB
drawn
be
slope
of the
formulations
For by the
terminated
of current
a new formula for IB subthreshold-saturation
[29] suggest
VT,
MOSFET
slightly
[27], IB between
in its
inside
the
is terminated the
current-voltage
for
subthreshold curve.
Other
which allows for continuity in the region boundary. Antognetti et.
that
are equivalent
to the
following:
( vD)) - exp ,- Vt,
= F x IB0(1
IB,
(5.25)
1 + F exp (---(vc,-vr)) _izi where
F is a factor
function
is very
VD
> Vt
VG
> VT,
and IB
that
is either
attractive. for
VG
a fitting
For VG = VT,
= F × IBO.
IB
parameter
< VT, = (F
It is seen
IB
is identical
× IBO/(1 that
[28] or estimated + F)).
for VG
> VT
[29].
to Equation For VD that
5.22.
> Vt IB
and
This For for
= F × IBO
128
CHAPTER
when
VG
arises
when
with
the
current not
exceeds
by a few Vt
attempting
most
and
being
in the
saturation
robust
enough.
considered
DEVICE
formulated
F.
one
at room
Numerous
in which
region. Thus
the
MODELS
or 50 mV
to evaluate
successful
found
equation
VT
5.
F was
subthreshold
A difficulty were
determined
the
to let
attempted
from
extraction
chosen
current
SIMULATION
temperature.
approaches
However, we have
AND
an offset
procedure
was
F = 1 in the
for all values
of VG
above
[30] as:
VD
IB
5.1.3
Parameter
The
expression
linearized
IBO(1
......... l+exp(
for
the
the
extracted
current
it in logarithmic
In order and
parameters,
to extract
-2.5V.
From
Vit,
Equations
5.16
M{1 where
M0
-
In the
above analysis
Fm
has
of a MOSFET.
of Vot
threshold
Vit
comes
from
M,
are
VG-
shown
at two values
5.24
the
M-factor
Vt
VT
(5.27)
inside
the
of VB,
brackets.
that
is expressed
is VB
= 0
as:
(5.25)
)} = [MO] + 2v/2¢f
= (M0-
1)¢f
(5.29)
the
same
meaning
The
"m"
denotes
In practice,
follows Vot
where
is easily
so that
expression
extraction
5.22
lrm] _ VB
VB
subthreshold region M factor. to those extracted for F. The
and
and
Vit
region
1 + [_1
Vt
2(26f-
= 1 + Vit/¢f
in Equation
form:
is measured
1
given
= [lnlB0]
IBO
IB
(5.26)
Algorithms
subthreshold
by expressing
(-V_)) M×Vt
Extraction
IB In ( 1 - exp (- VD)) vi where
- exp
from = 2¢f
Equation
5.29
the
as F derived that
values
Equation
Fm extracted
5.2; that
+ Vit
-
and
VTo
from
the
is derived
active
from
for Fm are
the close
is, for an n-MOSFET:
VTo
(5.30)
comes
from
the
active
region
voltage.
For p-MOSFETs,
Vot
is derived Vot
from
= VTo
Equation
- 2¢f
- Vit
5.3; that
is (5.31)
5.1.
MOSFET
SUBTHRESHOLD
where
again
Vit
region
threshold
Finally,
comes
from
PARAMETER
the
subthreshold
F0 has
notes
that
values
extraction
of F0 follows
the
the
uncertainties which the
little
physical
Tables
base
the fitting
active
of Equation
5.23:
(5.32)
as the
active
expression.
is because
bipolar
the
value
F.
"0"
de-
that
F0
derived
Thus
F0 depends
of the
The
it is found
F0 was
transistor.
In addition
F0 should
region
In practice,
This
of the
on
Thus
of fitting 5.3.
W columns. the
The
by ap-
F0 reflects
on
threshold
be interpreted
5.1.
in Table
region used
These
in Table major
the
the
extraction
voltage
extracted
as a fitting
factor
with
By
comparing
fits.
5.3.
as discussed of interface VitCo/q.
The
that
earlier
FO =
states
can
Table
5.1, the
is shown
were
The
for placed
continuity in Figures
the in the
of the 5.7
agree
given
in
in the
determined
differs
MOSFET
the
JFETFIT 5.8 where
and
formula
IBO
and
=
_
The
above
(1/cm
but
density
as:
Nit
=
2) = 2.16 × 10 _3 ×
W(gm)/L(ttm) drain
F0, are listed
F.
given
the
individual
eo = 3.9 x 8.86 × 10 -14 F/cm,
is: Nit
MOSFET of the
the
F = 0.831
from
equation
that
In addition,
Fro, with
listed
it is seen
from
significantly
with
5.2,
in
parameters
fit parameters well.
Vit, closely
are listed
individual
degradation
= 50 mn,
conversion
basis
5.1 and
agrees
from Xo
the global
parameters, v/V
derivatives and
listed parameter
are
voltages
extremely
a tolerable
= 0.850
where
with the
in Tables
and/_)
be calculated
= 8.2 × 109 (1/cm2).
Vit(V)/Xo(nm). The parameters
values
11.13 _
For Co = eo/Xo
JFETFIT
on an individual from
subthreshold Fm
the
are
MOSFETs
threshold
to be compared
indicate
three
Notice
the
MOSFET
determined
VT
CC,
using for the
process
the
(e.g.,
obtained
of MOSFETs
used.
are were
coefficients,
in Table
were
parameters
parameters
to the global
were
sizes
W dimensions
to fit each
5.2 which
5.3.
correlation
L and
different
In this extraction
saturation
listed
of four
results
the
parameters
Table
a set
These
[30] where
L and
ine
IBO
F values.
depends
region.
5.1 to
extractor
Nit
the
significance.
results
the
from
Results
The
from
of the
from
meaning
the
approximation.
in turn
active
5.1.4
VTo
[ltFOJ2v/2_b f-VB
from
width
in this
from
and
_Vt 2
physical from
significantly
proximating of IBO
same
F0 is derived
differ
region
129
voltage.
the
IBO
where
EXTRACTION
model current
1.067_tA,
= and
9/3, used
curves. VT
=
listed
in
to examThe
0.700V,
result and
130
CHAPTER
Table
5.1:
MOSFETs. XT 1 2 3 4 5 6 7 8
L 3 9 9 3 3 9 9 3
Individual In
W 9 9 6 6 9 9 6 6
this
VB 0.0 0.0 0.0 0.0 -2.5 -2.5 -2.5 -2.5
5.
MOSFET case,
2¢f
_ × x x x × x x x
10 -4 10 -s 10 -5 10 -4 10 -4 10 -5 10 -5 10 -4
2.46 5.38 3.35 1.44 2.46 5.38 3.35 1.44
DEVICE
MODELS
parameters -- 0.6V, VT 0.701 0.706 0.699 0.700 1,445 1.518 1.520 1.461
VTo 6 0.38 0.49 0.48 0.40 0.10 0.26 0.26 0.15
XT
L
W
VB
v
2 3 4 5 6 7 8
9 9 3 3 9 9 3
9 6 6 9 9 6 6
0.0 0.0 0.0 -2.5 -2.5 -2.5 -2.5
-0.042 -0.037 -0.017 -0.012 -0.054 -0,048 -0.022
based
on
= 0.075
V,
e 0.335 0.014 0.012 0.288 0.391 0.053 0.051 0.336
A 0.038 0.011 0.011 0.035 0.042 0.011 0.011 0.038
IB0 1.457 8.004 4.664 4.593 9.069 7.730x 3.064
X 10 -7
x x x x
10 -s 10 -7 10 -7 10 -s 10 -s
×
10 -7
AND
SIMULATION
individually and _ 1.58 0.49 0.44 1.39 1.62 0.62 0.60 1.51
fitting
four
O = 0.041. r 0.070 0.050 0.047 0.065 0,082 0.046 0.042 0.074
M
Temp
1.796 1.857 1.797 1.447 1.539 1.512 1.473
300 300 300 300 300 300 300
R 78 78 125 125 78 78 125 125
CC 0.9994 0.9998 0.9998 0.9995 0.9993 0.9997 0.9997 0.9994
5.1.
MOSFET
SUBTHRESHOLD
PARAMETER
EXTRACTION
Table 5.2: Individual MOSFET parameters derived from rameters given in Table 5.3. In this case, 2¢f -- 0.6 V and _
VT
6
c
the global FET VTo = 0.075 V.
L
W
VB
R
CC
1
3
9
0.0
2.39
× 10 -4
0.702
0.37
0.338
0.039
1.52
0.067
50
0.9994
2
9
9
0.0
5.39
x 10 -s
0.704
0.48
0.032
0.012
0.54
0.049
50
0.9995
3
9
6
0.0
3.35
x 10 -5
0.700
0.51
0.032
0.010
0.54
0.049
81
0.9980
4
3
6
0.0
1.48
x 10 -4
0.698
0.40
0.338
0.038
1.52
0.067
81
0.9993
5
3
9
-2.5
2.39
x 10 -4
1.449
0.11
0.338
0.039
1.52
0.067
50
0.9990
6
9
9
-2.5
5.39
x 10 -5
1.514
0.22
0.032
0.012
0.54
0.049
50
0.9966
7
9
6
-2.5
3.35
x 10 -5
1.523
0.26
0.032
0.010
0.54
0.049
81
0.9990
8
3
6
-2.5
1.48
x 10 -4
1.457
0.15
0.338
0.038
1.52
0.067
81
0.9980
IB0
_
M
r
pa-
XT
u
A
131
XT
L
W
VB
1
3
9
0.0
-0.0!4
8.011
x-i_
1.766
Temp 300
2
9
9
0.0
-0.042
1.810
x 10 -7
1.766
300
3
9
6
0.0
-0.037
1.124 x 10 -7
1.766
300
4
3
6
0.0
-0.017
4.974 x 10 -7
1.766
300
5
3
9
-2.5
-0.012
3.524
x
10 -_
1.487
300
6
9
9
-2.5
-0.054
7.961
x 10 -s
1.487
300
7
9
6
-2.5
-0.048
4.943
x 10 -s
1.487
300
8
3
6
-2.5
-0.022
2.188
x 10 -T
1.487
300
132
Table are
CHAPTER
5.3:
Global
calculated; Transistor
all
MOSFET other
5.
DEVICE
parameters.
parameters
Parameter
are
MODELS
The
AND
parameters
which
SIMULATION
are
indented
measured. Value
Standard Deviation
+ % ±
BETA:
THRESHOLD:
DELTA:
TAU:
ETA: EPSILON: LAMBDA:
M:
IB0:
AW(#m) AL(pm) VTf0(V) Vot(V) VTo(V)
= = = : =
1.086 1.249 0.711 0.604 0.077
r(vV)
=
o.8194-o.o18
KLG(V x pm) KLGB(pm) KWG(V x #m)
= = =
0.005 0.057 -0.051
KWGB(V D0(v/V) KLD(pm) KWD(#m)
= = = =
0.065 0.355 0.248 0.422
o(1/v)
:
0.043 4- 0.003
KLT(pm/V) RW(n ×/zm) H0(1/V) KiH(pm/V) E0(1/V) KLE(pm/V) L0(1/V) KLL(um/V) KWL(_m/V) MO(uuitless) Vit(V)
= = = = = -= = = = = =
rm(CV) ro(_/V)
x _m)
= File : [SANG.TRY2]C30N61
± 4444-
0.211 0.071 0.028 0.027 0.024
4- 0.012 4- 0.007 + 0.068 4444-
0.039 0.022 0.039 0.138
0.042 4- 0.007 401.965 4- 62.943 0.251 4- 0.062 2.227 4- 0.150 0.057 4- 0.022 0.690 4- 0.054 0.006 4- 0.003 0.062 4- 0.003 0.020 4- 0.016 1.267 4- 0.037 0.080 4- 0.011 0.772 4- 0.075 7.788
4- 0.424
(19.38%) (5.71%) (3.89%) (4.39%) (31.35%)
(2.16%) (260.24%) (11.77%) (-134.17%) (59.42%) (6.09%) (15.54%) (32.75%)
(6.25%) (15.34%) (15.66%) (24.68%) (6.72%) (39.38%) (7.83%) (47.28%) (4.52%) (80.63%) (2.94%) (13.94%) (9.68%) (5.44%)
5.1.
MOSFET
SUBTHRESHOLD
PARAMETER
3211 , , ,
/t
2568
O
133
EXTRACTION
1926
1284 c_:_:__642
IB
0
I
SUBTHRESHOLD 29 _"
I
23
_ -_
I I
]
I
I
u
_
_
SATURATION
i
I
t
:
dID
-
,,
_u_.-_
_
_0 0.65
I 0.69
0.73
I 0.81
0.77
0.85
UG (V) Figure shows VGS
5.7: that =
VT
MOSFET the
slope
=
0.700V.
drain
characteristics
is continuous
at
the
for
VDS
subthreshold-saturation
=
5V.
This boundary
graph at
CHAPTER
134
5.
DEVICE
MODELS
AND
SIMULATION
2209r 1767
/ X
A
CHIP
6.1 where
the
different
V2
6.2.
AREAS
,
OF
INVESTIGATION
and Test Strips wafer coverage
for different required.
A second
was
which
issue
ce_.¢eyed
parameters. surface
3.
from
the
Chips.
The
issue
of determining them,
detail
was
many
Test
which also
approached applied
two
passes
over
data:
the
the
from
the
from
the
to plot
wafers same
In
second this
resulting using
no
exclusions
were
made
on each
results
were
results
would
this
method
when
summary validity
results of the
problems final
certain
issue
of the
data
first
circuits are
of functional
elsewhere
for
concerned
functional
structure
was
(Chapter
the
applied
to be ac-
pathologically the
criteria
for the
these
from
each
were
used
Test
to create
In effect, from
involved The
to the
second win-
Chip
data.
wafer
indethe
the
and
to know
become
reason
on
others,
for
if
manifest
a comparison
severe
lot
decisions
curious
would
for
exclusion
to the
We were
data
samplings
data
methods.
how
involved
procedure
applied
This is due
and
and
of outliers)
clues
the
of the
seeking
the
data
management
structure
data
and
of the
test
technique. correlations on the
transistor circuits
two
technique
data
depart
in isolation
inadequate.
from
to
what
the
corresponding
can
combined. and
which
techniques:
Strip
exclusions.
wafer
be realistic,
different
histograms,
pass
was
further
subsequently
latter
wafer
made
fitted
to be considered
global
of
between
outliers,
(for this
enough no
surface
combined
distributions
data
the
pass
elimination
were
summary the
Test
these
technique
exclusions The
to the
The second wafers.
exclusion
case,
pendently.
sults
and and
pass were determined. dows to the individual The
two
if so, for
made
statistical
histograms
From
(identification
the
degree
to fit a surface
and was
using
be similar
population
and
the
sufficient
mapping),
were
first
global
must
population).
exclusions
4. The
points
was
all wafers
were
Strips
technique the
to determine
comparison
first
curate,
sites
(wafer
The from
(b)
nine
helped
a quantitative
Test
(a)
the
"sufficient"
nine
to identify
parameters
whether
Therefore,
fitted
143
production
thresholds, such
7) in this
between
as a RAM report.
test chips.
KP,
etc.,
or the
Examples compared
timing
sampler
with
the
described
re-
144
CHAPTER
6.3
Test
As
used
in this
structures; wafer.
Test
Test
Strips
of test
this
run,
the
have
much
every Strip
and
structures
Test
Chips
a few
Test
Chips
run
can
the
consumes
thus
Test
parameter
5 percent Chips
parameter
extraction.
3.
Circuit
parameter
extraction.
4.
Layout
rule
5.
Yield size
the
smaller
three
of the
Test
size
from ing
the KP
6.4 Once made,
for
limiting
However,
the
the
num-
Test
Strip
a production
5 percent from
chip.
of the
area
allows
from
of the
area
In
of the
wafer.
the following
all categories
selected
structures
categories:
to be from
are
included
routines
on the
Test run,
transistors
included
on this
are
in Table
6.1.
versus
VG
size, slope,/3,
where
respectively. AW.
Chips
sizes
extraction
each
maximum
JPL
of parameter
p-channel
the decisions Test
structures
Strip
of various
shown of the
L and The
Geometry
the
allows
Test
requirements
= /3L/W
dimensions, for AL and
available
included;
only
the
first
to be included. the
n- and KP
Chip
of the
transistors
culated
Chips,
total
selected
a production
of the
checking.
categories
for both
on
to test
analysis.
To satisfy ulators,
dedicated
extraction.
2. Device
The
Test
contains
of the
were
STUDY
wafer.
strip.
approximately
about
for the
than that
CASE
8 percent
on the
on each
wafer
fully
be included
about
dimensions
on
chips
can
sites"
be placed
CHIP
Design
are
consumed "prime
smaller
site
Strip
nine
nine
that
Test
1. Process
The
occupied
chip
Test
on this
and
on
production Test
only
structures
is replicated
the
Chips
positions,
ber
and
report,
therefore, The
chip
Chip
6. A TEST
KP
and
were
Chip
Assembler
identified
the
values
of the
Test
in Table
and
used the
sim-
Dimensions
along
with
the
values
were
derived
for
VD
= 50 mV
length
6.1 are
cal-
not
and
us-
width
corrected
Generation
Chip and was
Chips.
channel
Program
(TCA)
as CM5111,
curve
as-drawn shown
Test
on the contents
Test
ID
W are
These
for circuit
the Test
Strip
to generate
the
Test
Strips
had
been
geometry.
as ST5102.
The
6.4.
GEOMETRY
Table VTI-2, at VBS
6.1:
AND
Transistor
3-#m
TEST
PROGRAM
Geometries
CMOS/Bulk
= 0) for each
for both
p-well, Device.
The
2.0 n-Channel
15.0
Transistors 12.0
data
n- and
p-channel
L, showing shown
As-Drawn 3.0 6.0
in #A/V
wafers
from 2 (mean
1, 4, 5, and
Length 9.0
(#m) 12.0
15.0
56.7
49.0
46.5
45.2
44.7
-t-2.7
+1.5
=t=1.4
=t::l.1
=t:0.8
+3.3 9.0
(#m)
103.
54.6
44.5
=}=12.
+3.5
+0.9
49.9
44.4
6.0
±3.4 4.5 3.0
p-Channel Transistors
transistors
KP
is from
145
55.7
As-Drawn Width
W vs.
GENERATION
±I.I
81.7
47.6
43.8
41.6
40.6
±9.2
±3.3
±1.3
±1.3
±1.3
77.2
44.6
38.4
=t=8.7
+2.6
+1.9
15.0 12.0
-.809
-.827
-.831
-.837
-.836
±.027
=1=.018
±.017
=t=.022
+.024
- .807
As-Drawn
:1:.023
Width
-.811
- .846
- .844
(#m)
± .025
±.023
±.017
- .829
- .858
±.021
±.019
4.5 3.0
-.688
-.836
-.860
- .866
- .872
±.029
±.020
±.019
±.019
±.016
-.717
-.854
- .888
=t:.026
-{-.021
±.017
Run + a 10.
146
CHAPTER
two projects
were
laid out independently.
level specifications
of the required
all detailed
geometry
Intermediate
Form
(in the
case
CRRES
Chip
files
of structure,
which
were
routed
test
program
state
probing
to test
the
VTI-2
built
around
given.
test
following
the
the
prober
wafer This
study
leftmost The moved was
processed
The
result
reference one
particular
there drawn the
into
the
Test
Chip
Test each appears
probing
computer
project,
the
These
files
prepared
ten
a The
minutes.
to test
the
Two
Test
Strips
of small
ASCII
CRUNCH has
an
with nine
identifier
structure one
times
on each
was
replaced
by
a
software
will be
generated
for
and
the
earlier 10.
time,
it
position
of
1 had
the
steps. Wafer
missing. a binary,
sequential
formatting. Data
Once
Test
wafer,
the
VAX,
all data into
Compiler.
then
from its
all
name
such
file
chips
test
for
which
example,
wafer
the
CRUNCH is had
compiler,
would
of its filename. one
file
binary
called
by the
file for each as part
the
For
"349"
was
the
to organize
is complete, in a format
called "349"
file which
On
Preprocessor, this
contains
CRUNCH
characters
been test
test
by the
incorporated the
at the
programs
electrical
dimensions),
then the
by
has of the
test
files written
file, which
(of given Chip,
Test
files.
which,
1, 4, 5, and
was
the
data
of Data
system
the
for final
called
to this
a transistor
descrip-
instrumentation.
system
programmed
13 x 13 grid)
wafer
structure,
generated,
this
numbered
archival,
Each
assigned
been
the
11/780
is a series
files.
uniquely
(of the
labeled,
in the
about
one
details
Thus,
wafers,
by a program
raw data into is discarded.
for the
produced
structure.
test
takes
to execute
above.
four
from
TCA
automatically
the
test
Since
automatically
two columns output
JPL's
designed
outlined
used
to a VAX
using
computer. was
were
geometry
Disposition
no machine-dependent
system
steps
the
generated:
and
probed
LSI-11
system,
The
were
and
for fabrication
ST5102). structures
11/780
generated
file in Caltech
foundry
into the
which
prober
on a VAX
TCA
gross-
Chips.
were
an
microVAX-II
by the
STUDY
file containing the
of each
Generator,
Probing
wafers
of the
parameters
programs
Test
Strip
in CIF,
locations
Program
program
Test
files
CASE
an output
to the
or else merged
essential
to be executed
Wafer
The
been
Test
of a test
6.5
exact
the
input
was
directly
of the
CHIP
placement,
result
sent
geometry
the
and
wafer
one
case
a text
and
The was
CM5111),
(in the
to the
compilation separate
Chip
to producing
tion
and
Test
project
type
structures
which
A TEST
Using
automatically. (CIF)
of the
In addition
6.
CRUNCH
have Since file
6.6.
TEST
would the
STRIP
contain
exact
nine
file with
the
is fully Each
ber
and
labeling
of the
output
filename
whether
is labeled
are known.
for a wafer
the
"description
data,
and
in such Thus,
a way
one
that
CRUNCH
map.
labels
the
147
data file"
in each output
the construction
CRUNCH
of the
of the
TCA.
CRUNCH
it was
incorporates
taken
from
algorithmic
information
the
Test
to identify
Strip
file construction
or Test
and
the
Chip.
wafer
This
automated
num-
filename
access
to
files.
is essential to automating the analysis of the (formatted but as-measured) in the CRUNCH files, by the main analysis tool, a program called STMJPL was
program
derived
Strip
STMJPL
structures
the
generates
the
Test
Strips.
mined
by studying
the
global
sidered
"outliers."
indicating from
others.
tribution normally layer
6.3),
individual mode
6.7
From
The
case,
the
that
showing
a skewed
A map 6.4)
1. Sheet
series
and
parameters
to the
which
data
this
data
points normally
wafer
was
significantly
are
shown:
run
the
the
data, data
Resistance
was but
referred from
resistance
second
time
maps
in "avenue"
the
This
a tabulation to in this
Split-Cross-Bridge
Strip statistics
is not
an
the
Resistors:
dis-
example of of the metal generated
is shown,
printed result
is listed
is the
(Table
once
in
6.5).
Initial
ST5102
of information
section
different
first
were
mode
deterbe con-
distributed,
Probing:
Test and
maps
to n+poly
Structure
prepared.
rather
Wafer
and
were
would
was
distribution.
of contact
of wafer
summary The
applied
no one
from
Results
the
important
to decide
histogram
Qualitative
maps.
analysis
Results
resistance for metal to n+poly (Table 6.2), data, and the second is the sheet resistance
(Table
entire
of the
exclusions
Test
on
statistical
Preliminary
maps
histograms
histograms
wafers.
a preliminary analysis
wafer
Parametric
the
of Standards
Map
approximation
Two
of contact distributed
(Table
"full"
In this
to a first
the
Bureau
Wafer
program
on
National
[31].
Test
The
from
STATII
6.6
wafer
points
wafer,
furthermore, from
RESULTS
automatic.
allowed
which
for
nine
on the
to fit a surface
it obtains
CRUNCH
structure This data
data
PRELIMINARY
of the
site,
preprocessor,
informution
Therefore, files,
data
Each
of each
enough
test
MAP
points.
coordinates
file contains The
WAFER
with
each
plot,
of a full statistical obtained
in Table
6.6.
from
the
148
CHAPTER
Table to
6.2:
Histogram
n+poly
Stdev
on --
the
0.4312;
Maximum
--
of Test %
3.23
the
Strips
of
--
20.69;
Stdev
A
TEST
distribution
of
contact
Run
Wafer
VTI2,
Median
--
CHIP
CASE
resistance #1.
Mean
2.1512;
Minimum
30
4O
STUDY
for
metal
--
2.1112;
=
0.7312;
12.
INTERVAL
NO.
MIDPOINT
OBS.
NUMBER
OF
0
(OHMS)
INCLUDED
normal
6.
= 418;
EXCLUDED
LOWER
BOUND
-- 0.73;
POINTS
BELOW
BIN
UPPER
OBSERVATIONS
10
20
= 0 BOUND
1 = 0; POINTS
-- 3.23;
ABOVE
BIN
BIN
COUNT
34 = 0; BIN
= 34 WIDTH
= 0.0738
6.7.
PARAMETRIC
TEST
Table
6.3:
Histogram
metal
layer
from
VTI2,
Wafer
Median
of the
the
#l.
INTERVAL
PROBING
skewed
Mean
NO.
OF
on
the
= 10-sial/D; ; Maximum
resistance Test
Strips
% Stdev
of the of Run =
3.15;
= 0.0357fl/_.
OBSERVATIONS
OBS.
(RSHEET) 0.0306
3
0 ***
0.0307
9
******
0.0309
18
******
0.0310
34
******
0.0312
41
******
0.0314
39
******
0.0315
47
******
0.0317
43
******
0.0318
31
******
23
******
0.0321
17
*****************
0.0323
8
********
0.0324
7
*******
0.0326
11
0.0328
2
**
9
*********
0.0331
9
*********
0.0332
9
*********
0.0334
4
****
0.0335
9
*********
0.0337
3
***
0.0339
6
******
0.0340
3
***
0.0342
5
*****
0.0343
4
****
0.0345
4
****
0.0346
1
*
0.0348
0
0.0320
0.0329
>
+
0.0349
4
0.0351
0
10
20
30
4O
***********
****
0.0353
2
0.0354
0
0.0356
1
*
0.0357
2
**
LOWER POINTS
Stdev
= 0.0305fl/[]
NUMBER
of sheet
Resistor
= 0.033[1/D;
; Minimum
149
distribution
Split-Cross-Bridge
= 0.0316Vt/[]
MIDPOINT
STRIP
**
BOUND = 0.0305; UPPER BOUND = 0.0358; BIN COUNT = 34 BELOW BIN 1 = 0; POINTS ABOVE BIN 34 = 0; BIN WIDTH = 1.56 x 10-4
CHAPTER
6.
of
Resistance
150
Table
6.4:
Mean
=
"Full"
Wafer
2.40_,
Minimum
=
Stdev
1.69
12,
VT-i260866:c,6i (VTI2)(
Map =
0.31811,
Maximum
cMos
Contact
=
VTi2:
%
3.24
A
Stdev
=
22:56:18.00-
)
1171i
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.>31
CASE
INVERTER
VOLTAGE
VINV (V)-2. 19+0.013 (0.6%) .i
CHIP
maps
for the
.59,
5
CC (IGAINI vs Wnpoly) : 0.82 CC (IGAINI vs VTOsum)- 0.54 VTOsum = VTOn + IVTOpl
inverter
parameters
VINV
(left)
and
Chapter
7
CRRES
Project
171
172
CHAPTER
7.1
7.
CRRES
PROJECT
Introduction
The
JPL
the
CRRES
Chip
Microelectronics
Effects test
Package
Satellite
circuits
(CRRES).
for
evaluating
space
single
the
The
radiation
chip
delivered the
was
NASA/JPL
7.2
JPL
CRRES
testing:
upset
rates,
degradation
ground
test
chip
a Timing and
a CMOS
program
consists
of three
Random
Access circuit
transistor and
1986.
in
Radiation operational Memory
for
for
evaluating
Matrix
for eval-
parameters. parts
Parts
CRRES
inclusion
and
cell Transistor
foundry
of the
for
Release
Sampler
a-32
in March
segment
designed
Combined
of SPICE-like
at
CRRES
circuit
a Static
degradation,
fabricated
to the
test
of the
The
timing
custom
(MEP)
radiation
event
radiation-induced uating
is a full
for the
were
MEP
also
were
supplied
to
program.
Purpose
The
purpose
of the
JPL
1. To demonstrate 2. To validate based 3.
To
provide
VLSI 4.
on the
the the
ground
microcircuit
the
space
radiation
Runs The JPL radiation
Event
matrix
for parameter
for
single-event-upset
radiation-induced
(SEU)
and
CRRES
total
radiation
detection,
degradation.
ICs. response
chip
parameters
circuit
design
ionizing
dose
Chip
and
of
with
guidelines. (TID)
radi-
Foundry
Period
in Figure 7.1 is a 3-#m CMOS/Bulk three unique experimental structures:
extraction,
approach,
custom
foundry.
of CRRES
Reporting
(SEU) timing
Upset
of
During
of the
worst-case
in a spacecraft.
technology
silicon
response
to provide
circuits
for procuring
understanding
and
VLSI
assurance
chips,
at a radiation-soft
tests
CRRES chip shown test chip containing
tor
product
radiation
Description
custom
of test
a transistor-level fabricated
is:
of using
of a family
5. To evaluate Single ation effects.
7.3
chip
viability
JPL
use
circuits
To correlate
CRRES
a static
random
and The
a timing
JPL
CRRES
access
p-well space a transis-
memory
(SRAM)
sampler
for
chip
is included
measuring in the
7.3.
CRRES
CHIP
T$
T$
O1
D0
24
23
ORIGINAL
PAGE
IS
OF. POOR
QUALITY
DESCRIPTION
SPARE
SPARE
SilARE
22
21
20
SPARE 19
173
SPARE
SPARE
18
17
TS
T$
E
i
16
15
INV SPARE 14
SPARE 13
XT
N-GATE
WELL
12
11
INV
INV
WELL
V$$
10
9
T TS
D2
25
64-STAGE TS
D3
26
TS
04
27
TS
D5
Z8
TIMING
SAMPLER
TEST STRIP
INV
P-GATE
iNV
VDO
INVERTER
INV
SUB
5 INV
OUT
__
GND
29
4XTVG
RAM
DQI5
30
3 SPARE
RAM
DOI4
31
2 XT
RAM
DQ13
32
1 VDD
RAM
DO12
33
RAM
_:_11
RAM
0010
RAM
DC9
36
RAM
DQ8
37
4 x 8MOSFET MATRIX
34
35
VP$
_ 84
XT
VD
63
XT
ID
82
XT
C2
61
XT
Cl
_XTCO i
RAM
DQ7
36
59XT
RAM
D(_
30
UXTR1
RAM
DG5
40
57
41
42
43
44
RAM
RAM
RAM
RAM
DO4
DO3
DO2
DOt
Figure
7.1:
The
46 RAM DO0
JPL
41_
47
46
49
50
RAM
RAM
RAM
RAM
$
W
E
EP
CRRES
RAM A5
Chip
51 RAM A4
52 RAM A3
which
53 RAM A2
54 RAM A1
55
56
RAM
XT
A0
EN
is 6.9 mm
× 6.8 mm.
R0
SPARE
DESIGNED
DEC.
'B5
CHAPTER
174
Microelectronics
Package
scheduled
launched
in the
for ground
test:
to be
several
circuits
metric
test
ring
strips
oscillator This
JPL
section
Pin-outs
Section
7.10.
"Product the
Static The
SRAM
upset
due
rate
The
cell.
These
powered
by has
7.5):
matrix
a separate 8 columns
sizes
(Figure
(one total
poly and one leakage when The
timing
is tested
7.6).
Two
sampler
the
pulse
passes
are simplified.
also
in Chapter
The chip was isons lists
of radiation the
foundry
of Foundry The
yield
prone. leakage
was
The
about
dominant
current
The by the
hardness runs
(on
field
of 64 loaded
for
a given
sampler
of
transistors
for measuring
inverter
pairs.
It
The
number
of
time.
number.
circuit
(Figof one
oxide
blank
is
The
transistors
transistors
remains
as a binary
timing MOS
that
in the the
20 percent failure order
Implementation
(Foundry
of different
used
the
chain
is presented
submissions
1 indicated
is a chain
the
test
Thus,
and
test
in-space results
are
3.
fabricated
by two foundry
7.7)
along
low-
under
measurement.
oxide
n-channel
and one location are off.
(Figure
a pulse
gate
tapped,
device
(pA)
in
read/write
results.
n- or p-channel
contain
64 six-
is for minimum to be the least
Kelvin The
sub-threshold
locations
into
The
SEU
32-element,
normal
for
of changes
7.4.
affecting
with either
in the
85-76).
investigation
parameters.
contain
in
report
is organized
in Section
is a
be found
described
No.
pe-
or an asymmetrical
allow
changes
of the
report
can
operation; all timing data This design is expected
allowing
metal gate), all transistors
measurements described
cells described
the
are
a
results.
Electronics"
(SRAM)
7.4)
of 4 locations
function
LSI/VLSI
para-
versions)
function
chip
Memory
of SPICE-like
locations
by sending that
(Figure
the
a symmetrical
timing
supply,
29 of these
four
and
are
and
contains
JPL
early
during
Publication
different and
for extraction
and
presently
also
sampler
design
(JPL
either
7.3) allows full static for given operations.
transistor circuit
stages
Access
to radiation-induced
leakage
ure
1984
utilizes
to geometry
(Figure times
susceptible
Random
SRAM
design
(on
obtained
for Custom
7.2),
chip
timing
for testing
PROJECT
inverter,
and
of the
of results
chip
1982-September
transistor
matrix
CRRES
October
words.
circuitry execution
JPL
(Figure
CRRES
to confirm
requirements
Technology
1 kbit
16-bit
data
CRRES
six-terminal
description
Assurance
period The
The
The
assurance,
a description
timing
satellite
1990's.
a stand-alone
a brief
and
and
CRRES
early
timing
provides chip
of the
process/fabrication
for obtaining
CRRES
riod.
for
(MEP)
7.
1 and
processes
development
lk SRAM at the
mode
wafer
of the
of hundreds
and of this
chips
Service
Foundry
remaining
and
compar-
manufacturers. chip.
were only level
of ISI (MOSIS)
2) to enable
Table
Electrical
nominally
the
chips
lk SRAM
of microamperes).
7.1
analysis acceptable.
were chips The
latch-up was
4k
high
SRAM
7.3.
CRRES
CHIP
DESCRIPTION
175
POWER AND CONTROL BOARDS
TOTAL
DOSE
INNER
= 2
MIDDLE OUTER
= 8 =340
J.
kRAD(Si)/YEAR
EXPERIMENT BOARDS
10-MIL
ALUMINUM
SHIELD
MICROELECTRONICS PACKAGE
CRRES
Figure Package the
7.2:
The
(MEP),
locations
CRRES the
of the
Satellite
expected 12 JPL
showing doses
CRRES
for chips
the the
location
various
denoted
of the
Microelectronics
experimental
by A1-A4,
B1-B4,
boards, and
and
C1-C4.
CHAPTER
176
Table
7.1:
Summary
of
CRRES/MOSIS
PROJECT
MOSIS
NAME(S)
RUN NUMBER
RAM1,RAMIB,RAM1F CRESCHP18_B,CRESCHPI8_A CRESCHP17_B CRESCHP17_A CRESCHP16M PADTEST2 PADTEST3 PADTEST1
Projects --
DATES
7.
as
CRRES
PROJECT
of March,
--
ADDITIONAL
SUBMIT
PKGS OUT
RUN(S)
M65P M61P M5BG M5BG M5BE M5BE M5BE M5BE
5-20 1-8 11-22 11-22 11-5 10-28 10-28 10-28
7-23 2-21 2-7 2-7 1-29 1-29 1-29 1-29
CRRES4Kg,CRESCHP16 CRRES4K8,CRESCHP15 CR4K7TS,CR4KTR,CR4KTM CRRES4K7 CRRES4K6
M5BE M59A -M56G M55C
10-17 9-26 8-17 5-30 4-24
1-29 1-28 * 7-23 7-16
ARRAYN1,ARRAYP1
M53X
3-12
t
CRRES4K5 PADTEST CRESCHP14 CRRES4K4 PADTEST CRRES4K3 CRRES4K2 2KRAM
M53X M53X M53X M52S M4CL M4CL M4AD M49A
2-15 2-18 2-6 2-6-85 11-19 11-19 10-17 9-13
? 4-8 2-5 2-5 1-30-85 12-21
CRESCHP12,CHIP8284 CRESCHPI1
M48V M46M
6-2 6-19
11-30 9-13
CRESCHP10,CRRESCHP8 CRRESCHP7
M45H M44E
5-23 3-30
10-10 6-19
CRRESCHP6 CRRESCHP5 CRRESCHP3 CRRESCHIP2
----M42X M41V
2-29 2-28 2-1 1-16-84
$ f 4-11-84
CRRESCHIP
M3AJ
10-19-83
t
1987.
M57Q M54A M54A,M57Q M58U,M63E M54A M54A M54A
MS1P-F M4BG-F-M51R-F M4AD M49A M47T-F-M48V M46M-M47T-F M45H
M39D,M39H,M3BM, M3CO,M41V
Notes: CRRESCHPn = Ik SRAM Version CRRES Chip CRRESCHPnM = Ik SRAM Version CRRES Chip, MOSIS/MIT I/O Pads CRRES4Kn = 4k SRAM Version CRRES Chip ARRAYP1, ARRAYNI = I>-or n-Channel Kelvin Tapped Transistors RAM1, RAMIB, RAMIF = Normal, Asymmetrical, or Faulted SRAM *DELETE-CIF; tWAFERS FAILED; SRUN CANCELLED
7.3.
CRRES
CHIP
DESCRIPTION
ADDRESS DECODER
177
tVDD
......
.
__ __-__ __-__ _-L_.L_L._
ROW1
_ _ _ _;_ _o. I I__ _HOW.,O._t,N_O_, _fl I'_^'_-_-"_^'I MEMORY CELL
SENSEAMPLIFIER ENABLE
r
Vss _
t
'DATA LATCH
co tRO I_
PRE-CHARGE PREC
gE TRANSISTORS R/W
TRANSMISS ION GATES
L4--___
R/W _-_-----
TRI-STATE ENABLE
I
('T'- HI Z STATEI
I ITRI-STATE I/0 J
I
Figure
chips
had
zero
7.3:
percent
JPL
yield;
CRRES
the
chip
SRAM
dominant
failure
logic
diagram.
was very
high
leakage
current
(milliamperes). The pulldown
4k
SRAM transistors
problem was traced were not connected
misplaced p-well ground in adjoining SRAM cells The The the
lk SRAM
problems JPL
also
voiding
is not
The to assure
this rules
connection and was too small. was
chip
submitted were
(Figures
the
p-well
and
for destructive
traced 7.9 and
p+diffusion
physical
to encroachment 7.10).
Such
separation
analysis
of the
the to a
at JPL.
p-well
encroachment
beyond
caused
the
problems described above. The foundry's design rules were examined to be more conservative than JPL's on this critical dimension. This
analysis problems,
on
design
functional and found
chip
to two design errors (Figure 7.8): to ground in the SRAM cell due
indicated
but lk chip
thought could was
a functional
substantial to have cause selected circuit
voiding
in the
contributed
long-term
reliability
for design in the
field
to any
(Figure yield
7.11).
This
or functional
problems.
modifications
remaining
oxide
observed
single
and foundry
fabrication run.
in order
At this
same
CHAPTER
178
[] E_
[]
[]
[]
[]
7.
CRRES
PROJECT
[] []
i
•
1 °..
[]
I
I
[] Figure
7.4:
The
JPL
CRRES
Chip
MOSFET
Matrix.
7.3.
CRRES
CHIP
DESCRIPTION
179
BINARY
INPUT
II
II
II I
Figure
time,
7.5:
the
drop-in aged
Locations
ring test
The
Chips by MOSIS electrical step 2.2) gram
was
received
were
passed
from
of the same
design
compared
was caused
was
identified on each Chips
listing in Table
from
of 1986
the
two
with
a new
1986:
pack-
chips
of the
asymmetric
bad
I/O
the MOSIS
run
from
Foundry in the
from
2 were
pass
also fabricated in zero percent
2. The first
JPL
than
(DQ1-4).
resulted
problem
better
cell did not
lines
with
packaged
zero
metal
Fault
percent
fabrication
Chips
(Section
runs. 1 and
for integration
7.2 along
and
this was considerably
of results
Foundry
of all deliveries
incorporated
50 percent
at Foundry
yield
by comparison of the
run
1. The
coverage
matrix.
circuit
This
fabricated
to 50 percent by a step
sampler
of February
tests;
However,
MOSFET
end
to consistently
as those
run M61P).
timing
About
Foundry
in the
at the
cells.
all screening
]
sizes
the
delivered.
due
(MOSIS
from
SRAM
CRRES
in March
is shown
chip.
resulting
fabricated
complete
on the
yield
yield,
CRRES
removed
for the
yield
and
was
wafers
SELECT
transistor
placed
asymmetrical
cell parts
qualification
MOSIS
four
and
20 percent
various
2 submission
and
symmetrical the
was
Foundry
symmetric
of the
oscillator strip
parts
COLUMN
II
into
of JPL the
2 runs the
CRRES
expected
were
MEP
sent and
Chips total
dose
to the to serve
to the before
CRRES
pro-
as spares.
CRRES failure
A
program for these
CHAPTER
180
7.
CRRES
PROJECT
9.0 --_
9.0
m
_--
]
IEZ]l
±
5/'//J ii// wwww
9.0
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T
////.
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T
(9/3) 19/91
O I-1
t
r7 (6/3) (6/9) D
= DIFFUSION
Figure
Table
7.2:
Process
_
7.6: Geometry
JPL
CRRES
Fail-Dose
of cells
Chip
in MOSFET
deliveries
Breadboard
= POLYSILICON
to the
Flight
GATE
Matrix.
CRRES
program.
Flight
SEU
TID
(Spare)
JPL
AFWL
krad(Si) (De-Lidded) A (VTI2)
15
4(b)
l(b)
B (VTI2)
15
4(b)
l(b)
4(b) .....
!(_b)
C (VTI!) (a)
= 12-18-85;
_15 ......... (b)
= 3-11-86;
9(a) .....
(c) = 3-15-86
6(c) 4(¢)
10
7.3.
CRRES
CHIP
DESCRIPTION
181
BINARY OUTPUT
DECODER
000
I
I
I LATCH E
,, _1,
A v
1,, v
L
000
Clb
T
E
/
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T
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T
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_1_ I .... I I_ _1 .... I_ _ : RESET'-F'ARM-IDE DATALAY I- DATA- I_ESE-ITI_ARM - I_ELAy--I-Tipr Figure
7.7:
JPL
VALID
CRRES
Chip
Tipf Timing
Sampler
Circuit.
VALID
182
CHAPTER
7.
CRRES
PROJECT
..........lilll i......... °°o°°°o
i ii:i _:_
,=°.oo_
,
! I,l[llkl li I
i
:::
r:_
I
_
1%
"
!
:
:
D
P-WELL
TO
P
LESS THAN
I'--I_.,_ox/r LJDIF
parts.
These
Before
the
L--J
Figure
7.8:
parts
parts
acterized space.
with
the
The
placement
and
1987
and
There
are
several
7.4
the
rate
accuracy
:
in the
SRAM
BETWEEN
at
board.
for the diagram
JPL
in the
was
performed
made
on the
on JPL
results
7.2 along
Chips as seen
char-
of test
in Figure the
indicated
cells.
fully
7.3 shows
generated,
of measurements
were
for analysis
interface
interface,
designed
they
is shown
CRRES
this
cell.
symmetrically
Table
Chip
PULLDOWN
GROUND
SRAM
shipped,
MEP
JPL
CRRES
AND
-
METAL
with
for each
about
__-J
4 kbit
were
in the
circuit
concerns
CONTACT
_P_
archived
expected
NO
......
chips
MEP/JPL
--.L
i
satellite
data
rate
a complete
the
1 kbit
of the
dose of the
errors
m
TRANSISTORS
_LY
for the
and
dose
uary
affect
the
location
An analysis
may
Design
used
expected
RULE
_
intended
electrically
from
DIFFUSION
DESIGN
7 P-WmLL
F
I 11
!
chip/board MEP. in Jan-
in Figure the
figure,
CRRES
7.12. which
Chips.
SRAM
The
SRAM
tri-state is the
test
I/O
pads),
six-transistor
Functional SRAM
circuit
patterns
testing
(Figure
7.3) is accessed
using
4 control
static
cell typically
of the
of all ones,
SRAM all zeros,
lines
and used
through
64 16-bit
6 address
lines.
for radiation
is conducted walking
using ones,
and
hard a DAS walking
words The
(through
memory
cell
applications. 9100. zeros
Standard are
used
ORIGINAL OF POOR
7.4.
PAGE IS QUALITY
SRAM
183
UNSTAINED
P-WELL EDGE
"__
(AS DESIGNED)
STAINED
P÷ DIFFUSION P-WELL _ AS DES EDGE _ AS FABRICATED
Figure
7.9:
matrix
decoder
Encroachment circuitry.
of the
p-well
into
the
p+diffusion
in the
transistor
184
CHAPTER
7.
CRRES
ORIGINAL
PAGE
OF POOR
QUALITY
PROJECT
UNSTAINED
P-WELL EDGE (AS DESIGNED)
I
STAINED
,I,.'(io00xSEM SUPERIMPOSED) _ '
P-WELL I AS DESIGNED EDGE [ AS FABRICJ
Figure cell. more
7.10: Note lateral
Expansion
in the
of the
superimposed
diffusion
in this
p-well
around
cross-section process
than
design on the
depth.
boundaries lower
picture
in the that
SRAM there
is
IS
ORIGINAL
PAGE
IS
OF POOR
QUALITY
SRAM
7.4.
185
_f/NITRIDE
INTERLEVEL OXI DE METAL "--"
THERMALOXI DE FIELD OXI DE
SILICON VOIDS IN INTERLEVEL OXIDE
METALTHINNING AT STEP
fjNITRIDE INTERLEVEL OXIDE --,------METAL "---
THERMALOXI DE FIELD OXI DE
8000X SEM MICROGRAPH (CROSS SECTION) Figure tributed expected
7.11:
Voiding
to any that
in the
particular this
could
interlevel failures
lead
oxide. which
to long-term
This
were
seen
reliability
was on
not
shown
this
problems.
run,
to have however,
conit is
ORIGINAL OF POOR
CHAPTER
186
7.
CRRES
PAGE IS QUALITY
PROJECT
ID
vO n
: lOOK TSI TSE
2_
EN
VG
ENID
VOID
vo
vG
6 rs
DATA
OUT
xT
XT
_I
TSBE2 TSBEI
RAM
RAM WEEP
SENSE SV
BUS
SO OUT SENSE
5S 10v
BUS
_
NO
DUT NO.
oo
WEEP
2
DUT
NO
2
qALL_
)I_S WSAI
8E
.
BOARD
ENAOLE.
TlS
-
TRISTATE
(I}
IN
DISABLE
STATE
OUTPUT
(2)
IN
DISABLE
STATE
AOOR
AND
_31
IN
DISABLE
STATE
WEEP
LINES
(4)
THESE
TWO
RESISTORS
LOW
MUST
..
RAM
DATA
BE
DESELECTED
t JNE$
HELD
LOW
REMOVED
Figure 7.12: Circuit diagram The notes indicate concerns, the
$
I
JPL
CRRES
Chips
and
F LOAT •
UNLESS
INSURES OR
XT
CHIP
CIRCUIT
THESE
RESlSTORS
ARE
_NSTALLED
DEESLECTEO, WILL
NOT
WORK
of one pair of JPL as of January, 1987, the
MEP.
CRRES Chips on the MEP. about the interface between
VD SOURCE FEEOBACK
7.4.
SRAM
Table
7.3:
187
Chip
placement
and
Process
and
the
test
Ground JPL's
using
2A, 2B
devices
This
writing
each
cell, counting
used total
for the of how
nominal
performed
the
is performed
are
using
measured.
pattern
and
the
number
of times
then
Tests were chips from the were cell
CRRES was
with
developed
each
of these
SEU
rate
modeling,
proceedings
of the
both
to find
types
a method
of cells along 1986
balanced
with
Nuclear
The zeros
Dosimetry rate and stored,
SEU will
test be
in the written
MEP into
analysis
and
Space
during
periods
of this
December 7.5. will
the
1986)
be similar SRAM
and
to the the
7.14. was
Effects and
then
the ground
number
of by
writing
test
fixture
of specific
unbalanced The
data
for
Work
done
on
published Conference
text
a
on CRRES in these tests
The
statistics.
data,
angle
zeros) and keeps with the measured
cyclotron Included
and
Radiation
and
The
cells.
SEU 7.13
a
destruc-
A record
unbalanced
in Figures
the
will be provided by the cross section. In addition, except
and
(SEU),
is exercised
and
occurred.
calculated.
for increasing
is shown
Transactions on Nuclear Science, included in this report as Section all
reading
has
also performed at the UC Berkeley 88-inch foundry runs that are included in the MEP. chips
test
rays
n- or p-well
energy
of all ones (or this data, along
ion fluence, the upset rate and cross section are cell upset locations was not kept in this test.
Upset
of
is con-
cosmic
a potentially
under
continuously an upset
CRRES chip writes a pattern many cells have upset. From
Event
beam
device
Nichols
testing
in all CMOS
a known The
Such
Single
found
Don
of primary
latch-up,
device
a test
MEP.
of 2MHz.
and
514). effects
and
rate
Smith
(Section
effects
p-n-p-n
ion fluence
of the
Rate
operating
by Ted
Section These
boards
8
of a flip-flop
parasitic
test
the
[34].
for the
(krad(Si)/year) 340
> 1) to simulate
in state
of the
with
was
(Z
rate
Dose
SRAM's
Reliability
ions
change
technologies.
at the
Parts
triggering
initially
B, C
heavy
non-destructive
incidence
1A, 1B
testing
dose
Placement
A
radiation
on semiconductor tive
Board
is performed
Electronic
ducted
expected
of this test.
of upsets
in the (IEEE paper
is
All ones
or
counted.
MEP, which allows for calculation of upset the upset location within the SRAM will be
of high
upset
rates
(i.e.
solar
flares).
188
m
m
E :::L 0 q)
CHAPTER
6001
I JPL CRRES
I
500
0
ZERO
/_
ONE
1 CHIP
1 VTI2
i
7.
I
1
1
I
170 MeV
Br 60 °
o ° z_
241 MeVKr0
170 MeV
400
Br 0 ° p-MOSFET
DRAIN
300 CI 60 °
200 n-MOSFET
DRAINS
0 100
82 MeV
CI 0 °
0 0
0.1
LINEAR
Figure
7.13:
0.2
0.3
CHARGE
Symmetrical
cell,
I !
82 MeV ffJ 0
PROJECT
TOTAL
i 0 I,0
CRRES
I
I
0.4
0.5
TRANSFER,
lk SRAM
I 0.6
0.7
ion upset
response.
L =
heavy
0.8
7.4.
189
SRAM
1500 JPL
CRRES
CHIP
VTI2 170 MeV
Br 60 °
TOTAL m
Ixl p-MOSFET DRAIN
E --1 ¢D 0
1000
t_
170 MeV
i
241 Me V Kr 0 °
0 I--w m m ffl 0
Br 0 °
500 82 MeV CI 60 °
u,I ffl
82 MeV
LINEAR Figure
7.14:
n-MOSFET
CI 0 °
CHARGE
Asymmetrical
cell,
TRANSFER, lk SRAM
DRAINS
°° (°°t
L= _ heavy
sec 0
ion upset
_-_
response.
ORIGINAL
PAGE
IS
OF POOR QUAi-ITY
190
CHAPTER
Paper
Presented
Space
Radiation
IFFF
on
Pran_,hlion,
AA
Nuclear
_ol
S_lcnvc.
ANAIYTICAL
_ETIIOD
NS
FOR
at
the
}3,
No
SRAN
G,
Martin
and
heavy-ion-induced (SRA.H)
deslgn
of
goal uric
reuse
the
area
environment
will
indicate
be
of
into and
a
The test
than
Radiation
cell
L --4
increasing cell,
for
the Fig.
was
1.
Six-transistor
Combined
access
memory
ceils the
with JPL
at
(SEU)
test
I
as
a
the
static
Specially rates
upset
chip
of
cell.
(SRAH) et,hanced
characterizing
rate
the
a
part
of
to
memory
be
is
b
in
Package
Release SRAHs
and are
because makes
the
detection
increase (Fig. both
l) the
upset
was
designed
pull
up
rate
is
low
Mpa
and
2).
times.
The
With
but
modifi,'ation
to
pull
down
In
=
5
V
a
cell
shown
set
in
Fig.
]
raised
is
upsets.
Fig,
3
This
of ceil
the
maximum
].6
to
over
requires
al.
approach
that initial
the
approach
of
current
pulse
one
approach, current
author_ }
is
must
determinin
R
a
node.
at
be
cell
17.2
SRAM
cells
used
current
concerned
with
no
The
a
on
to
expression
differences
the
in
cell
follows
our
the for
upset SPICE
large
the
for
"syrametrical"
CMOS
analysis.
simulate
well
Jaeger
expression of
state-space
between lie
that
analytical charge
reasonably
analysis
learned
an
critical
pulse
analytical
four
recently
derived
based
j
current
Jaeger
approach
of
treatr_nt
critical
They and
their
current-pulse pulses. and voltages
-]
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.
: :.......
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dimensions
2.
Asyrm_trical are
experimental given
in
in
Table
memory 2
except
cell
pulse.
have
also the
approach
4, i
usual a
the
calculating
steps.
WORD
the
an
The
_
Fig,
to The
suggest
from
derived
curves.
'*node
in
node
the
be
seen
while
which
IB0
a
analy£i_2
As
can and
injecting
of
et. for
Mnb
[rom
with
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To
regions
design,
increase the
VDD for
Va
the
by
nature
ceil drain
increase
aI]
from
state-space
this
dil[i(ult.
this
to
processing
flight
rate,
six-transistor
the
estimated
space
oversize
kbitSR&H-year
additional
rates the
with
at
voltage
of
upset
(CRRES).
[or upset
upset
tare,
(Fig.
upsets/l
choice
a
trajectories
slope
Combined
Satellite
of very of
the
transistors upset
a
the
Of
Effect_
memory have
notation.
the
(HEP)
Radiation the
they
calculated and
voltage
critical
the
included
were
trajectories.
held
critical
contrast Hicroelectronics
rates approach
resulting
state-space
designed are
a
random
upset
release"
of node
directed
is
cell
(CRRES). The
effort
memory
Release
and
This
static
designed
Introduction
single-event-upset
!
experi-
rate
upsets/
the
Sateli:te
the
kblt-year)
(l.b
for
....
the
the
the
upset
SRA2_
intended Effeccs
for
the
asymmetrical
chip
01109
space
upsets/l
(17,2
balanced
khit-year).
Technology
space
by
rate
upset
larger
minimLLm-geometry i
the
times
a
in a
CELLS
to
in
for
MEMORY
access to
achieved
ts
model
AS_,_IETRICAL
the
where order
transistors
cell
4.7
in
upsets
analytical
asy_etrical
mental
random
cells
observed
selected
the
predict
applied
rate
asyrm'netry
of
from
static was
upset
of
The
drain
Results
to
asy_etrical the
nu_lber
of
method
with
increase
envirorunent. the
The
mem >
23.0
363
I
-_
..,I"3 _
300 -1 25o 2.00
i t,:'o° I o.6o
J'/
121
O0 0.O0
1.OO
200
3.00
400
000
5.00
1 O0
200
3 O0
4 O0
5.00
VG(V)
VG(V) VD= 5.00 450 400
VG 5.00 4.75 4.50 4.25 4.O0 3.75
531
443
3.50 3.00 250 2.00
354
3.50 3.25 300 275 2.50 2.25 200 1,75 1.50 1.25 1.00 0.75 0.50 0.25 0.05
A
1,50 I O0 060
_.266
020 005
177
89
0 000
I 00
200
300
400
000
5 00
1 O0
2.00
3 O0
400
500
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372
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r I
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=
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1 O0
200
3.00
4.00
I
I
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z
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r
.,_,.._..._..__
I O0
MG(VI 300
400
5.00
3.25 3.00
.._ 292 -
2.50 2,75 2.25
150 1 O0
I 2.00
t 3.00
t 4.0o
2.00 1.75 1.50 1 25 1.00
135
--
I 0.00 1.00
n-Channel (bottom)
0.50 0.75 0.25
97
0
5o0
0.00
100
2.0o
3.00
4.0o 5.0o
0.05
VD(VI
MOSFET after
VG 5.00 4.75 4.50
389
060
7.0
tion curves
o.2oo os
4.25 4.00 3.75 3.50
6.0
7.16:
200
1oo 1"50 o.eo
467
VGIV)
Figure
1
4.00
250 200
80
f_
584
0,20 0.05
T
r
VD = 5.00 450
5.0 _
"_
4 oo s 5o
122
3.50 3.00
_ ¢
_
0.00
_
= _._
200
350 4.00
5.00
MG(V) l
5.00
450 4.00 35o 300
.
2.50
//////,'/._=_=_
0,00 30
'
0.20 o.6o 1oo 15o
j-//////_ "/////_3"00 /////////_
= I-124
.___
5
/JA ///I ////I ////j
pre-irradiation
10 krad(Si)
curves
at 2.5 rad(Si)/sec).
(top)
and
post-irradia-
7. 7.
TIMING
IOOuA
SAMPLER
I
I
199
I
I
I
I
I
|
|
I
I
10. uA _DOSE
RATE = 2.5 Rad Si)/s
i.0uA
, CHIP 1 100hA
tO. nA
i.0nA
,
0. InA
i
PRERAD
l
,
I
i
l
_
1.0
7.17:
CRRES
I
,
I0 DOSE C0-60,
Figure
i
Chip
leakage
I00
kRAD (Si) versus
total
I
dose.
200
CHAPTER
Table
BETA:
THRESHOLD:
7.5:
Comparison
of n-MOSFET ROW
ROW
PARAMETER
#2
#3
VB
= O,-2.5
TRANSISTOR
ROW %
#4
%
2)
50.84
48.81
4
50.46
1
1.290
0.797
38
1.353
-5
DELTA
L(_m)
1.018
0.931
9
1.091
-7
VT0(V)
0.715
0.679
5
0.719
-1
PSI(V)
0.069
0.027
61
0.066
4
0.834
0.842
-1
0.842
-1
0.053
0.077
-45
0.051
4
0.060
0.06
0
0.074
-23
°s) × #m)
-.054
0.24
544
-.062
-15
KWGB(Izm)
0.104
0.084
-71
0.121
-16
D0(V
x #m)
0.299
0.331
-11
0.315
-5
KLD(I_m)
°'s)
0.694
0.723
-4
0.636
8
KWD(#m)
0.272
0.112
59
0.138
49
THETA(1/V)
0.039
0.049
-26
0.044
-13
KLT(#m/V)
0.074
0.058
22
0.065
12
RW(_
LAMBDA:
Results.
W(#m)
KWG(V
EPSILON:
Test
PROJECT
DELTA
KLGB(#m)
ETA:
CRRES
KP(uA/V
KLG(V
TAU:
Matrix
TRANSISTOR
GAMMA(V
DELTA:
7.
725.41
596.28
18
646.6
11
H0(1/V)
x _um)
0.047
0.049
4
0.049
4
KLH(t_m/V)
0.309
0.254
18
0.419
-36
E0(1/V)
0.056
0.056
0
0.057
2
KLE(I_m/V)
0.586
0.592
-1
0.566
3
L0(1/V)
0.005
0.002
60
0.004
20
KLL(_m/V)
0.100
0.108
-8
0.099
1
KWL(#m/V)
0.021
0.001
52
0.017
19
V; PHI
= 0.6 V
GEOMETRIES:
W(#m)/L(lzm)
= 9/3,
9/9,
6/9,
6/3
7. 7.
TIMING
Table
SAMPLER
7.6:
- BE]-TA:
THRESHOLD:
201
n-MOSFET
Matrix
TRANSISTOR PARAMETER
Ok
lk
gb{UA/V:_i
50.84
49.54
3
1.290
1.049
W(#m)
DELTA
L(#m)
VT0(V) PSI(V) GAMMA(V
°5) × #m)
KLGB(#m) KWG(V DELTA:
TAU:
EPSILON: LAMBDA:
x #m)
=
0,-2.5
TRANSISTOR
V;
(Si)) %
10k
53.40
-5
49.23
3
19
1.437
-11
1.002
22
%
DOSE 5k
(krad
Results.
%
1.018
1.054
-4
0.998
2
0.996
0.715
0.681
5
0.612
14
0.421
41
2
0.069
0.033
52
-.031
145
-.287
516
0.834
0.837
-4
0.83
5
0.914
-10
0.053
0.049
8
0.060
0.074
0.071
-34
-.028
-23
0.067
-12
0.126
153
300
-.301
457
0.114
-10
-10
0.426
-43
-110
-.054
-.045
-17
-.216
0.104
0.133
-28
0.1
D0(V
0.299
0.3
0
0.33
KLD(#m)
0.694
0.635
9
0.744
-7
0.926
-33
KWD(pm)
0.272
0.388
0.248
9
0.245
10
THETA(1/V)
0.039
0.035
0.04
-3
KLT(#m/V)
0.074
0.081
-10
0.062
16
0.07
5
725.41
813.2
-12
579.25
20
707.2
H0(1/V)
0.047
0.105
-123
KLH(#m/V)
0.309
0.528
-71
E0(1/V)
0.056
0.051
9
KLE(#m/V)
0.586
0.596
L0(1/V)
0.005
KLL{#m/V)
°s)
x #m)
KWL(#m/V) VB
Test
KWGB(#m}
RW(i2 ETA:
Radiation
TOTAL
DELTA
KLG(V
Cobalt-60
PHI
=
0.6
GEOMETRIES:
-43 10
4
0.045
-15
-126
0.341
-10
0.194
37
0.057
-2
0.058
-4
-2
0.593
-1
0.603
-3
0.003
40
0.005
0
0.005
0
0.100
0.098
2
0.103
-3
0.103
-3
0.021
0.001
52
0.019
10
0.012
43
9/9,
6/9,
V W(#m)/L(l_m)
= 9/3,
6/3
0.206
3
0.106
-338
202
CHAPTER
Table
7.7:
BETA:
THRESHOLD:
DELTA:
TAU:
ETA: EPSILON: LAMBDA:
p-MOSFET
Matrix
Cobalt-60
TRANSISTOR PARAMETER
Ok
KP-(u-A/V_i DELTA W{#m) DELTA L(#m) VT0{V) PSI(V) GAMMA(V °5) KLG(V x pro} KLGB(#m) KWG(V × pro) KWGB(#m) D0(V °'5} KLD(pm) KWD(#m) THETA(I/V) KLT(#m/V) RW(fl x #m) HO(I/V} KLH(#m/V) E0(1/V) KLE(pm/V) L0{1/V) KLL(pm/V) KWL{pm/V}
18.03 0.527 1.112 0.776 0.425 0.453 0.081 0.117 0.159 0.104 0.25 0.428 0.425 0.099 0.073 2038 0.47 0.845 0.043 0.313 0.018 0.174 0.039
Radiation
TOTAL lk 18.61 1.075 1.026 0.809 0.462 0.448 0.087 0.108 0.163 0.094 0.204 0.482 0.116 0.106 0.047 1270 0.198 0.625 0.043 0.283 0.014 0.187 0.037
7.
%
DOSE 2k
-3 -104 8 -4 -9 1 -7 8 -3 10 18 -13 73 -7 36 38 58 26 0 10 22 -7 5
CRRES
Test (krad
18.41 0.898 1.082 0.835 0.502 0.431 0.067 0.108 0.189 0.122 0.230 0.414 0.009 0.113 0.049 1323 0.258 0.741 0.036 0.268 0.013 0.184 0.028
Results.
(Si)) % 5k
-2 -71 3 -8 -18 5 17 8 -19 -17 8 3 98 -14 33 35 45 12 16 14 28 -6 28
VB = O,2.5 V; PHI = 0.6 V TRANSISTORGEOMETRIES:W(#m)/L(pm) = 9/3, 9/9, 6/9, 6/3
PROJECT
17.23 0.835 1.209 0.893 0.541 0.455 0.052 0.098 0.358 0.073 0.201 0.215 -.191 0.I03 0.053 1551 0.1 1.326 0.034 0.273 0.016 0.174 0.032
% 4 -58 -9 -15 -27 -0.4 36 16 -125 30 20 50 145 -4 27 24 79 -57 21 13 11 0 18
7. 7.
TIMING
1.8
SAMPLER
--
[]
1 6 _--
_"
:VBS=0,
._
mV/kRAD
SLOPE=-30.9
_
(Si),
mV/kRAD
DOSE RATE=
_
VTI2,
1.2 _-_---
CHIP#l,
VTo-0.674V (Si],
2.5
VTo_=1.47V
RAD(Si)/S W = 6#tm,
_]_.,_-CHANNEL
,.o--_0.8
SLOPE_-30.0
O :VBS=-2.5,
1 4 (_ •
203
-L=3k(rr,
MOSFET
: -_
--
-=
0.6(_
o.4 o __,,, 1,,,,1,,,,i,,,,i,,,, -0.2
i,,,,i,_f,l,l_,l,l,,ll,,,_
--
-0.4
-
[]
:VBS--0 SLOPE=-34.7
-__--
O:VBS:2.5
mV/kRAD(Si),
SLOPE=-34.5
VTo=-0.762V
mV/kRAD(Si),
-
VT o :-1.11V
--
-o._-0.8 [ _ Z
DOSE '-'__.._.._
VTI2,
-1_0(__
_,._-_--_ __
_
_
RATE : 2.5 RAD(Si)Is CHIP#l,,
L=3/_m
W:6_,lm,
P-CHANNEL
---
MOSFET
-_
-1.6 -1.8
_
-2.o
__
,,, I,,,,I,JJ 0
3
, I,,_,1,,,,
6
9
I,,,,1
12
15
DOSE Co-60 Figure
7.18: Threshold
MOSFETs.
The
gate
voltage voltage
versus was
,,,,1_,,, 18
21
h-_,, I,,,,24
27
(KRAD)
dose for n- (top)
5 V during
:
irradiation.
and p-channel
(bottom)
30
204
CHAPTER
7.7.1
Test
The
CRRES
ers
Hardware
chip timing
grouped
sampler
to one input
of a dynamic
timing
sampler
input
pad
the
(TSE).
timing
sampler
of applying pins), the
then
number
to the delay
The
chain
the
timing
sampler
input
6-bit the
error
The
wafer
employ and
(delay
between
output
word.
by
has
then
is less
to N. Figure
TSI
rate
each
(START)
by
The
N and
7.19
which
to tap
that
adjusts when
the
on TSI
output through
technology
the
measurement
VLSI this
chain
delay
tripped.
quantization
inverter-pair
the
100
a stop
between
is measured
is greater relationships.
on
is repeated
start
timing
error
transition
from
output
lab
inverter-pair
sequence
the output
and
output. This inverter-pair
on the
when
in the
converter,
JPL
by
TSE
reflects
pairs
This
and
and
of inverter
followed
to
consists
word
64 taps
D0-D5.
is increased
decreased
illustrates
TSI
output
edges
eliminates of the
N on the
circuit
delay
in the
and
the
stop
previous
than
or
equal
When
the
h I
I TSE
OUT
(STOP)
)
N
I
I
I
I
I RESET
I ARM II
DATA
DELAY#1
VALID ] (OUT
2 . 62
3
10
**********
13
*************
13
*************
2.73
4 +
2
3.08 3.19
i 0
3.31
I
3.42
0
Figure
7.22:
Positive
*
1
STDEV 0.360
*********
9
2.96
3.54
ns
+
2
2.39
2.53
20
+ .........
0 -
2.27
MEAN
(ram)
0
2.04
2.85
! 2.5
OBSERVATIONS
i0
+ .........
2.50
PAIR ARRAY
t 2.0
OBS.
(ns)
2.16
60
PAIR NUMBER
1.0 DISTANCE
I_
% ns
edge
*
STDEV 14.1
MEDIAN 2.50
inverter-pair
MINIMUM ns
1.30
delta
MAXIMUM ns
data
3.60
ns
from
one
chip.
7. 7.
TIMING
Table
7.8:
SAMPLER
Summarized
209
data
from
the
timing
samplers
on four
Wafer #1 (9 sites tested) % STDEV MEDIAN MINIMUM 4.16 2.71 2.57 0 0.9999 0.9995 3.97 2.58 2.42 0 0.9999 0.9998 3.97 2.68 2.54
wafers.
TDP PR2 TDN NR2 TDPAVG
'EAN 2.72 0.9998 2.57 0.9999 2.69
STDEV 0.113 0 0.102 0 0.107
TDPSIG TDNAVG TDNSIG
0.27 2.56 0.20
0.03 0.104 0.03
TDP PR2 TDN NR2 TDPAVG TDPSIG TDNAVG TDNSIG
MEAN 2.61 0.9999 2.46 0.9999 2.58 0.26 2.44 0.20
STDEV 0.158 0 0.134 0.0006 0.159 0.03 0.135 0.04
Wafer #4 _ STDEV 6.05 0 5.43 0.062 6.16 13.3 5.54 20.0
(41 sites tested) MEDIAN MINIMUM 2.61 2.29 0.9999 0.9997 2.46 2.18 0.9999 0.9995 2.59 2.26 0.26 0.15 2.45 2.14 0.20 0.13
MAXIMUM 2.94 0.9999 2.73 0.9999 2.92 0.32 2.71 0.28
TDP PR2 TDN NR2 TDPAVG TDPSIG
MEAN 2.65 0.9999 2.48 0.9999 2.62 0.28
STDEV 0.179 0 0.27 0.0005 0.173 0.05
Wafer #5 % STDEV 6.76 0 11.04 0.047 6.59 17.1
(70 sites tested) MEDIAN MINIMUM 2.65 2.31 0.9999 0.9997 2.51 0.56 0.9999 0.9993 2.62 2.29 0.27 0.22
MAXIMUM 3.64 0.9999 3.22 0.9999 3.54 0.61
TDNAVG TDNSIG
2.49 0.19
0.141 0.05
5.68 27.6
2.50 0.19
3.15 0.56
TDP PR2 TDN NR2 TDPAVG TDPSIG TDNAVG TDNSIG
MEAN 2.80 0.9999 2.66 0.9999 2.76 0.27 2.65 0.18
STDEV 0.131 0 0.126 0 0.127 0.04 0.119 0.02
Wafer #10 (9 sites tested) % STDEV MEDIAN MINIMUM 4.70 2.81 2.56 0 0.9999 0.9998 4.75 2.67 2.43 0 0.9999 0.9998 4.59 2.76 2.53 14.8 0.26 0.22 4.51 2.64 2.43 10.8 0.19 0.15
11.0 4.05 " 15.3
0.28 2.56 0.19
0.22 2.41 0.15
2.21 0.10
MAXIMUM 2.86 0.9999 2.69 0.9999 2.83 0.31 2.68 0.25
MAXIMUM 3.02 0.9999 2.87 0.9999 2.98 0.34 2.85 0.21
CHAPTER
210 viation tions
computed
from
is specified
PR2/NR2
are
the
correlation
small,
data.
with
inverter-pair
a standard
delays
in Figures
are
displayed
the
actual
locations
that
were
the
fastest
circuits
would
be
If a microprocessor, gate delays, of the wafer processors the
is due
first
in the the
to the
the
channel to length
be expressed
cannot
41 boxed These
wafer
side
delay
per
clock
#4
numbers
maps
left
are
show
on
that
the
wafer.
cycle
ratio
This
difference
was
80
r (r = 5/3
on CRRES
of intrinsic
n-channel
delays and
chip). and
a fanout
of 2.
transistor
in
transistor
If these
fanouts
were
would
be equal.
The
transition
p=channel
and
of the p-channel This
to the of each
p-channel
negative
delays n-channel
to n-channel
inverter-pair
p-channel
than
inverters.
inverter
drives
the
as the
ratio
is due
the n-channel
of 2).
positive as well the
9 MHz. larger
in the first
inverter
(fanout
and
the
edge,
transition
between
only
difference
of 1) while
output
run
transistors
second
(fanout
imbalance
could
is 5 to 6 percent
in which
the
negative
difference
wafer
is a positive
the
loading
in terms
obtained to be inverter
afford
counter.
delay
transistor
can
delays
Tn
[2].
from accurate delays
the
Since
pairs
(inverter-pair
to within
standard
the delay
the satellite
data
all have minus
CRRES
and robust. on a satellite
to include
the inverter results
on
Conclusions
data
approach measure
pair
and
mobility
vp respectively
The
the over
0.2 ns.
lower
p-channel
design
of 1 and
drives
positive
of the
and
the output
inverter
of the transitions
transitions.
n-
sampler's
inverter
of the delay
7.7.3
the
fits for
variation
transitions
wafer.
computational
negative
a fanout
drives
then
is a function width
from
line
delay
The
on this
portion
of the
timing
to the
second
transistor
negative
respectively.
for positive
for
times
inverter
magnitude
and
delay
input
same,
7.24
to the
average
transi-
respectively.
of less than
and
obtained
right
delay
drives
So, if the
the
deviation
measured
longest
upper
response
inverter-pair the
the
inverter-pair
This
and
input
was fabricated on this run, processors from the lower left portion could run at a maximum clock frequency of around 11.5 MHz but
inverter-pair
different
7.23
whose
from
The
that
for positive
PROJECT
TDPSIG/TDNSIG,
corresponding
Notice
CRRES
for positive/negative
and
coefficients
transition
is very
The
data
by TDPAVG/TDNAVG
positive/negative a wafer
the inverter-pair
7.
type
obtained
the same delay
one
least
chip
timing
sampler
demonstrates
This structure provides that has power and weight lab
test
from
one
delay
= 100 ns/# significant
equipment timing
(±0.4ns), stages bit.
the
such
sampler
as a frequency array
procedure
tripped)
this
an easy way to limitations and
should
shows
that
performed
on
give accurate
ORIGINAL
PAGE
OF POOR
7. 7.
TIMING
12
v
ii
v
I0
v
9
v
8
v
7
v
6
v
5
V
4
v
SAMPLER
211
-:
3
2
v
v
1
>
9 9 4
+
3 3
2.88
1
Wafer
to
4
2.82
0.159
ns
ns
1 -
STDEV ns
than
4
2.75
2.57
less
OBSERVATIONS
+ ......... 2
2.25
0:2.25
% ns
map
STDEV
MEDIAN
6.15
of the
2.58
average
MINIMUM ns
inverter-pair
2.25
MAXIMUM ns
delay
2.92
for
ns
positive
IS
QUALITY
edges
ORIGINA[ OF POOR
CHAPTER
212
>
< ii i0
12
NUMBER
OF
0
2.16
2
**
3
***
3
***
2.33
2
**
2.39
5
*****
2.22 2.27
-
2.45
>
11
2.50
Figure
7.24:
(Wafer
4).
******
4
****
2.62
2
**
2.68
3
***
+
STDEV 0.135
Wafer
13
ns
ns
to
2
19
ns
i:
ns
to
2
25
ns
2:2.25
ns
to
2
30
ns
3:2.30
ns
to
2
36
ns
4:2.36
ns
to
2
42
ns
5:2.42
ns
to
2
48
ns
6:2.48
ns
to
2
53
ns
7:2.53
ns
to
2
59
ns
8:2.59
ns
to
2
65
ns
9:2.65
ns
to
2
71
ns
+:
_s
or
greater
2.19
2.71
map
% ns
20
+ .........
+
***********
6
2.56
ns
than
OBSERVATIONS
i0
+ .........
MEAN
less
OBS.
(ns)
2.44
2
0:2.13
STDEV 5.54
of the
MEDIAN 2.45
average
MINIMUM ns
inverter-pair
2.13
MAXIMUM ns
delay
2.71
ns
for negative
edges
PAGE' iS QUALITY
7.8.
CONCLUSIONS
7.8
Conclusions
The
major
for
inclusion
parts
goal
In this was
of the
on
have
design
the
J_elivered
report
period,
violations
incorporated
SEU
tests
of the
The
modification
minimum
design
parameters and
transistor
mode
7.9 The
functions
a TID chip
This
CRRES is being
in order
SRAM
consist
cell,
matrix
work
on MOSFET
leakage
currents.
report
circuitry
mandated
electrical
does high
depletion
from
were
a factor performed
to cause
cell
confirm
except
that are
for
transistor
a highly
transistors. interfere
dose
upset,
geometries.
period
matrix
not
Results
by foundry-specified
tests
individual
circuitry
chip done
Cobalt-60
in any
causes
suc-
the
way
with
n-channel
en-
mode.
will be split
into
since
SRAMs
This
for upgrading will greatly
and
60 testing
work
simplify
test
are on
an SEU
needed
SEUs.
be desired.
Chip
in a satellite
For the
The
and
TID
CRRES Chip
will
sampler.
to study
is essential
two chips,
data
would
timing
measurements
functional of the
many
statistical
10 Mbits and
is planned matrix
capabilities Cobalt
in the
a sufficiently
we calculate
devices Plans
not changed
to get sufficient
of a MOSFET
Experimental
the
design
is almost
tests
required
in an addressed
to become
rate
these
ways:
cell
Work
of the
Chip.
experiment
upset
energy
to testing
decoder
the Since
SEU.
between
transistors
until
Future
that
important
SRAM
of seeing
to AFGL Additional,
program.
in two
ratio
from
alternative
CRRES
minimum
ancillary Results
from
devices
probability
the
has
of the
1986.
asymmetrical
cell.
parts
in March
part
the
cr0ss-section
in the
measurements
hancement
above
was to provide
was changed
and
balanced
design
the
design
cell indicate
spacings.
indicate
test
overall
of the
matrix
preferable
results
the
to the
extracted
ground
SRAM
substantially
correspond
a slight
test
that
project
accomplished
eliminated
asymmetrical
transistor
cessful
the
chip
was
to the
were
than
levels
results
CRRES This
to increase
greater
at energy
JPL
MEP.
been
rule
of three the
213
the
radiation
to establish to evaluate capabilities
and
expedite
MOSFET
matrix
effects the
potential
of the
specific design
are underway. heavy and
ion timing
testing sampler.
field-oxide
cause
of chip
changes.
Improved of the
test SRAM
214
CHAPTER
7.10
CRRES
This
section
user
of the 1.
Chip
contains JPL
CRRES
pin-outs
CRRES Chip
PIN
Test and
7.
CRRES
Configuration
connection
diagrams
PROJECT
Pin to serve
as
Outs
a guide
chip.
Leakage
Measurement
Pin
STATE
Configuration
FUNCTION
PIN
FUNCTION
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
VDD XT VPS SRAM A7 XT VG INV OUT INV SUB INV VDD INV p-GATE INV VSS INV WELL XT WELL INV n-GATE SPARE SPARE TS I TS E SPARE SPARE SPARE
VDD VDD GND GND NC VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM
DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 S W E EP A5 A4
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
20 21 22 23 24 25 26 27 28 29
SPARE SPARE SPARE TS DO TS D1 TS D2 TS D3 TS D4 TS D5 GND
GND GND GND NC NC NC NC NC NC GND
52 53 54 55 56 57 58 59 60 61
SRAM SRAM SRAM SRAM XT EN SRAM XT R1 XT R0 XT CO XT C1
A3 A2 A1 A0
GND GND GND GND GND GND GND GND GND GND
62 63 64
XT C2 XT ID XT VD
30 SRAM DQ15 GND 31 SRAM DQ14 GND 32 SRAM DQ13 GND NC = NO CONNECTION TS = TIMING SAMPLER XT = TRANSISTOR MATRIX SRAM = STATIC RANDOM ACCESS INV = INVERTER
PIN
MEMORY
A6
GND NC NC
STATE
to
a
7.10.
2.
CRRES
CRRES ures
CHIP
Chip
TEST
Pin
7.1,
7.3,
PIN
FUNCTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
CONFIGURATION
and
Configuration
for
PIN
VDD XT VPS SPARE XT VG INV OUT INV SUB INV VDD INV p-GATE INV VSS INV WELL XTWELL INV n-GATE SPARE SPARE TS I TS E SPARE SPARE SPARE SPARE SPARE SPARE TS DO TS D1 TS D2 TS D3 TS D4 TS D5 GND
S, SRAM
SRAM
OUTS
215
Operation.
See
also
7.25. STATE
VDD VDD GND GND NC VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NO NO NC NC GND
30 SRAM DQI5 (0,1) 31 SRAMDQ14 (0,1) 32 SRAM DQ13 (0,1) NC = NO CONNECTION TS = TIMING SAMPLER XT = TRANSISTOR MATRIX SRAM = STATIC RANDOM ACCESS INV = INVERTER *SRAM
PIN
W, SRAM
E, AND
PIN
FUNCTION
33 34 35 36 37 38 39 40 41 42 43 44 45 *46 *47 *48 *49 50 51 52 53 54 55 56 57 58 59 60 61
SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAMS SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM SRAM XT EN SPARE XT R1 XT R0 XT CO XTC1
62 63 64
XT C2 XT ID XT VD
DQ12 DQII DQI0 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 W E EP A5 A4 A3 A2 A1 A0
PIN
STATE
(0,I) (0,I) (0,I) (0,1) (0,I) (0,I) (0,I) (0,I) (0,I) (0,1) (0,1) (0,1) (0,1) *(0,1) *(0,1) *(0,1) *(0,1) (0,1) (0,1) (0,1) (0,1) (0,1) (0,1) GND GND GND GND GND GND GND NC NC
MEMORY SRAM
EP, SEE TIMING
DIAGRAM
Fig-
ORIGINAL PAGE IS OF POOR QUALITY
216
BLOCK
CHAPTER
7.
CRRES
PROJECT
DIAGRAM:
AO A1
55 ._
0-,,-_ e,---
,_
S2
_"--
A5 AS
50 57
_"-_
A7
3
44
DQ1
OTHER
31
DQ14
STANDBY
IO_30
PINS
IN
CONDITION
DO15
_'-'-_
! 1 VDD
LLJ,1 2tl
48474849
GND
S
W
E
EP
TIMING DIAGRAM: READ
CYCLE
WRITE
CYCLE
/
S
w_--_
w x_L/ I.,,-• --,,_,_-----".-_,,._-.
EP
_._
__
,:-,,.l
d_' ON
P-XT
ON
N-XT
OFF
TG
\
ore
/
ON
/
P-XT
OFF
_
N-XT
OFF
_
OFF
OFF TG
B
OFF
OFF
f
ON
_
A_
OFF
OFF
B
;_Z
OFF
A xZi_'
II _
10@ ns
e >
100
b
400nl
f ,,_
400m
II ;_
400
>
© ;>
400
a_
d
