Programmable on-chip and off-chip network architecture on demand for flexible optical intraDatacenters Bijan Rahimzadeh Rofoee,1,* Georgios Zervas,1 Yan Yan,1 Norberto Amaya,1 Yixuan Qin,2 and Dimitra Simeonidou1 1
High Performance Networks group, University of Bristol, BS8 1TH, UK 2 School of CSEE, University of Essex, CO4 3SQ, UK *
[email protected]
Abstract: The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over. © 2013 Optical Society of America OCIS codes: (060.4254) Networks combinatorial network design; (060.0060) Fiber optics and optical communications.
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1. Introduction Intra-datacenter [1,2] network interconnection provide high data rate lines preferably using optical fibres among the servers to enable bandwidth aggressive applications with tight QoS requirements of parallel and distributed computing in massive scales. The requirement of highly connected servers is approached by deploying hierarchies of L2/L3 switches in
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(C) 2013 OSA
Received 1 Oct 2012; revised 6 Nov 2012; accepted 7 Nov 2012; published 27 Feb 2013
11 March 2013 / Vol. 21, No. 5 / OPTICS EXPRESS 5475
different levels within and between datacenter racks and clusters [1] with not much concern about resource/spectral efficiency [2]. This is whilst optical networking, specifically sub wavelength networking, supporting efficient optical networking for wide range of bitrates, is an candidate solution for complementing the highly electrical switching architecture of intra data center networks today [3]. In the meantime, the semiconductor industry with innovative FPGA based hardware solutions with increased logical gates and processing power units enable implementation of dynamic and programmable run time reconfiguration of the FPGA boards [4]. The NoC based run time reconfiguration approach can introduce new levels of flexibility to the network architecture, by adapting to different functionalities, through reconfiguration of the on chip components and implemented Intellectual Property (IP) cores connections [5]. In this paper, we propose a novel programmable and reconfigurable network on-chip andoff-chip design and implementation, which enables operation in bitrate ranges of 100Mbps up to ~8.7Gbps using wavelength, and sub-wavelength based technologies, improving networks performance with transparent, highly resource efficient, and ultra low latency communications, well matching with intra datacenter strict requirements. This work is based on open-hardware infrastructure that allows for on-demand programmability that in turn delivers flexibility, agility, efficiency as well as high network performance and high QoS delivery. This design implements FPGA based network line card with runtime reconfigurable on-chip design supporting 10GEthernet and TSON [6] Tx and Rx. The line-card operation of Ethernet or TSON is supported by the flexible and AoD [7] optical transport layer built as offchip network. It supports guaranteed transport of high capacity (9.8 Gbps per 10G NIC) and ultra-low latency (
