ISA Transactions 51 (2012) 333–344
Contents lists available at SciVerse ScienceDirect
ISA Transactions journal homepage: www.elsevier.com/locate/isatrans
PWM-Switching pattern-based diagnosis scheme for single and multiple open-switch damages in VSI-fed induction motor drives Mohamed Trabelsi a,1 , Mohamed Boussak a,∗ , Moncef Gossa b a
Laboratoire des Sciences de l’Information et des Systèmes (LSIS), UMR CNRS 6168 Ecole Centrale Marseille (ECM), 38 rue Joliot Curie, 13451 Marseille Cedex 20, France
b
Unité de recherche en commande, surveillance et sûreté de fonctionnement des systèmes ‘‘ C3S’’, Ecole Supérieure des Sciences et Techniques de Tunis (ESSTT), 5 Avenue Taha Hussein, BP 56, Bab Mnara 1008, Tunisia
article
info
Article history: Received 31 March 2011 Received in revised form 18 October 2011 Accepted 21 October 2011 Available online 6 December 2011 Keywords: AC motor drives Fault detection Line-to-line voltage sensing Pulse-width modulation switching pattern Voltage source inverter (VSI) Single open-switch diagnosis Multiple open-switch diagnosis
abstract This paper deals with a fault detection technique for insulated-gate bipolar transistors (IGBTs) opencircuit faults in voltage source inverter (VSI)-fed induction motor drives. The novelty of this idea consists in analyzing the pulse-width modulation (PWM) switching signals and the line-to-line voltage levels during the switching times, under both healthy and faulty operating conditions. The proposed method requires line-to-line voltage measurement, which provides information about switching states and is not affected by the load. The fault diagnosis scheme is achieved using simple hardware and can be included in the existing inverter system without any difficulty. In addition, it allows not only accurate single and multiple faults diagnosis but also minimization of the fault detection time to a maximum of one switching period (Tc ). Simulated and experimental results on a 3-kW squirrel-cage induction motor drive are displayed to validate the feasibility and the effectiveness of the proposed strategy. Crown Copyright © 2011 Published by Elsevier Ltd on behalf of ISA. All rights reserved.
1. Introduction Motor drive systems fed by pulse-width modulation voltage source inverters (PWM-VSIs) are widely used in industrial applications for variable-speed operation, such as aeronautics, railway traction and robotics. The wide use of the VSIs is due to the high switching frequency of the semiconductors [1,2] and the use of the PWM speed controllers. Most of these inverters use power switches based on the IGBTs because of their high efficiency, fast switching, easy control of the gate-signal commutations, and their ability to handle short-circuit currents for periods exceeding 10 µs [3,4]. In most cases, the drive systems are exposed to loading and hard environmental conditions which may lead, in addition to the natural aging process, to many faults essentially related to the induction motor or inverter. Faults detection and diagnosis in induction motors are widely investigated in the literature [5,6]. Concerning the VSIs, in spite of their better qualities, they can present some drawbacks and remain sensitive to abnormal operating conditions.
∗
Corresponding author. Tel.: +33 491054490. E-mail addresses:
[email protected] (M. Trabelsi),
[email protected] (M. Boussak),
[email protected] (M. Gossa). 1 Tel.: +33 491054490.
Besides, in the previously published statistical studies, as in [7,8], the percentage of faults for variable-speed drives was evaluated to 63% of the user-experienced drive faults during the first year of operation. In addition, the majority (70%) of these faults was related to power switches, such as open circuit faults, short-circuit faults and gate-misfiring faults. Insulated-gate bipolar transistors’ (IGBTs’) open-circuit faults are usually linked to the loss of bonding wires of the control signal or to a short-circuit fault causing rupture of the transistor [3]. In the case of a gate-misfiring fault, the inverter can operate during an important time interval, but with a degraded output voltage and overstress on the other semiconductors, as investigated in [9,10]. An over-voltage or over-temperature can lead to a short-circuit fault [11]. In this context, to improve the reliability and allow continuous operation of the inverter in degradation mode during fault conditions, several fault-tolerant strategies have been adopted, as investigated in [1,12–17]. They consist of three essential processes [4]. The first one is fault detection. This task is achieved by deciding whether the inverter operates under normal or fault conditions. The second one is fault identification. This task is executed to identify the faulty device, and estimate the size, type and nature of the fault. These first two processes are often called ‘‘fault diagnosis’’. After identifying the fault, isolating it consists in removing the faulty device for safety operation. Here, it is obvious that the implementation of fault-tolerant strategies requires first
0019-0578/$ – see front matter Crown Copyright © 2011 Published by Elsevier Ltd on behalf of ISA. All rights reserved. doi:10.1016/j.isatra.2011.10.012
334
M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344
and foremost the information provided by diagnosis methods that will be used to introduce appropriate control of the drive system. Concerning the IGBT open circuit fault mode, there are a number of techniques and approaches that address the fault detection and identification (FDI) problem. The most interesting strategies are based on current or its variants, or voltage measurements of the VSIs. In [18], the average values of the Park’s vector currents in α − β frame and the phase-angle determination are used to detect the fault occurrence. In [19–21], the authors suggest the normalized DC current method. This technique has some drawbacks when implemented in a closed-loop control scheme. The same authors have proposed the modified normalized DC current method. This technique has been improved in [22,23] for single and multiple-fault modes by using fuzzy logic symptoms. Recently, in [4], the fault detection scheme is achieved based on the operating characteristics of the BLDC motor. Other techniques, based on discrete wavelet transform and fuzzy logic, have been investigated in [10,24]. In [25], the knowledge-based model is used for VSI diagnosis where the authors suggested two techniques using the current vector’s instantaneous frequency and the slope of the stator currents trajectory in the α − β frame. More recently, in [26–28], the diagnosis of the VSIs focuses on multiple-fault occurrence in power switches. The time minimization between the fault occurrence and its detection is researched in [29–33]. In [29], the fault occurrence is detected by analyzing the error between the measured and estimated pole voltages in the inverter. By using a ‘‘time criterion’’ and a ‘‘voltage criterion’’, the detection time is less than 10 µs. In [30], the fault detection is achieved by monitoring the voltages endured by the lower switches. From simulation results, the fault condition is detected within 2.7 ms. In [31], the pole, the phase, the line-to-line and the neutral voltages are used for open-switch fault diagnosis. The fault detection is accomplished in less than fourth current period, by evaluating the residual signals deriving from a direct comparison of the measured voltages to their respective references. Recently, in [32], a fast diagnosis method is proposed. It consists in combining the collector–emitter voltage of lower switch for each inverter leg and the reference switching signals. This task is performed based on simple hardware and without voltage sensor. More recently, in [33], the authors proposed a fault detection circuit for open- and short-circuit faults diagnosis. Such a technique is based on the gate-voltage behavior at turn-On transient of the IGBTs. The detection time is less than 3 µs. Generally, it is strongly desirable to avoid the use of extra sensors. So, the methods based on current analysis are more attractive for simplicity and cost effectiveness. Unfortunately, because of the high fault detection time, which is about one fundamental current period, the technique based on current analysis tends to be highly unreliable for some industrial applications (e.g., as those based on sensorless vector control techniques), where the speed and torque tracking is essential [34,35]. The main problem is the high sensitivity to switching device failure. Hence, if the fault is not quickly detected and compensated, it can lead to hard failure and to disconnecting the system. Consequently, the use of extra sensors is justified when it is necessary to maintain the operation of the drive system and to improve its reliability. This paper proposes a detection and identification technique for IGBTs’ open-circuit faults in the switching devices of PWMVSI-fed induction motor drives. As in [31], the measured output quantities used for the FDI scheme are the output line-to-line voltages, but here, a significant extension of such a technique is proposed that does not compare the output voltages with their respective references, but instead aims at improving the previous effort on two aspects. The first one is that this extension requires two voltage sensors instead of three. The second is that it permits
to reduce diagnosis time to a maximum of one switching period instead of fourth of the fundamental current period. The new approach is achieved by analyzing the switching pattern and the change of the line-to-line voltage levels during the switching times, under both healthy and faulty operating conditions. The implementation of the proposal is realized by adding a simple circuit into the existing inverter system. The feasibility and the effectiveness of the proposed diagnosis scheme are verified by both simulation and experimental results. 2. System description and VSI topology The considered electric drive system is illustrated in Fig. 1. It is composed of an AC/DC converter, a three-phase voltage source inverter (Three-Phase VSI), an induction motor controlled by the indirect stator field oriented control (ISFOC) strategy and a variable load generated through a magnetic powder brake. The additional blocs are dedicated to prevent the breakdowns in the dc-bus voltage, the AC/DC converter or the DC/AC converter. Here, the protection scheme includes circuitries to prevent overcurrent in the inverter, overvoltage and/or undervoltage in the dc-link. When a short-circuit fault occurs in one of the three inverter legs, the faulty leg is isolated during a short-lived time by means of the fast fuses or the standard protection systems that detect an over current in the power switches or in the dc-link, [7–10]. 2.1. VSI topology The three-phase voltage source inverter is composed by the parallel connection of three inverter legs, as shown in Fig. 2(a). It uses a constant voltage source provided by a voltage source rectifier and a capacitive DC-link. Each leg features two semiconductor switches (TK , TK +3 k = 1, 2, 3) with antiparallel connected freewheeling diodes (DK , DK +3 ) used to provide a negative current path through the switch. The VSI is controlled by binary gate signals (SK , SK +3 ) ∈ {0, 1}. The gate signal SK or SK +3 is equal to ‘‘1’’ when the switch is conducting and equal to ‘‘0’’ when the switch is open. Note that SK and SK +3 must work in a complementary way to prevent the short circuit of the dc-bus voltage and to avoid both switches to be open producing undefined output voltages. For a healthy condition, the positive alternation of the phase current in (n = a, b, c ) is built by means of the transistor TK and the diode DK +3 . During the negative alternation, the phase current in is built by TK +3 and DK . Without considering the dead time, DK +3 or DK is turned On at the same instant when TK or TK +3 is turned Off, respectively. According to different combinations of the switching states SK and SK +3 , the inverter can generate three different output line-to-line voltage-levels (vdc , 0, −vdc ). For illustration, consider the two inverter legs a and b, as they are shown in Fig. 2(b), which illustrates which semiconductor is conducting (the transistor or the diode), the polarity of the output phase currents and the corresponding output line-to-line voltage. Here, these two inverter legs are controlled by S1 and S2 . Therefore, they feature four different switching states, which are given in Table 1. To each switching state corresponds one output line-toline voltage level. For example, consider the first case (case 1) shown in Fig. 2(b). In this case, the switching state is defined by S1 and S2 = 1. Hence, leg a is connected to the negative potential through the diode D4 , while leg b is connected to the positive potential through the diode D2 . So, the output line-to-line voltage uab generated by the inverter is equal to −vdc . However, under normal conditions and neglecting the dead time introduced in the switching pattern, the general expression of the output line-to-line voltages can be given by uab ubc uca
1 0 −1
= vdc
−1 1 0
0 −1 1
S1 S2 . S3
(1)
M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344
335
Fig. 1. Electric drive system structure.
a a
b
c
b
a
ia > 0
b
ib < 0
a
ia > 0
a
ib > 0
b
ia < 0
b
a
ib > 0
ia < 0
b
ib < 0
uab
Vdc
ia
ib t
-Vdc
Fig. 2. (a) Inverter topology. (b) Two inverter legs conduction states when (Case 1) uab = +vdc , ia > 0 and ib < 0, (Case 2) uab = 0, ia > 0 and ib > 0, (Case 3) uab = −vdc , ia < 0 and ib > 0, (Case 4) uab = 0, ia < 0 and ib < 0.
Table 1 Switching state and line-to-line voltage under normal conditions. Case n°
1 2 3 4
Gating signals
Output current sign
S1
S2
ia
ib
0 1 1 0
1 1 0 0
>0 >0 0, S1 = 1 and S2 = 1. (b) ia > 0, ib > 0, S1 = 1 and S2 = 0. (c) ia > 0, ib > 0, S1 = 1 and S2 = S5 = 0 (dead time in leg b). (d) ia > 0, ib < 0, S1 = 1 and S2 = 1. (e) ia > 0, ib < 0, S1 = 1 and S2 = 0. (f) ia > 0, ib < 0, S1 = 1 and S2 = S5 = 0 (dead time in leg b).
this case, the faulty switch or faulty leg is immediately isolated by the fast-acting fuses or the circuit breakers and the fault will result in an open circuit of the power switch or the inverter leg. In this work, only the single or multiple open-circuit faults (due to gates misfiring) will be considered. Also, the output lineto-line voltages of the inverter are used to perform the fault detection and diagnosis. Indeed, after the fault occurrence, the conduction intervals of the by-pass diodes change. Thus, the voltage components given by Eq. (1) are no longer valid. Based on this fact, the open circuit fault detection can be achieved by evaluating the error between the actual line-to-line voltages and those obtained from Eq. (1). 3.1. Post-fault behavior for an open circuit of the upper switch in leg a (T1 ) To analyze the faulty IGBT’s impact on the commutating sequences of the diodes, let’s consider Fig. 3 which presents the switches conduction states and current paths of two inverter legs when the upper transistor T1 is faulty. The switching state S2 = S5 = 0 corresponds to the dead time interval of the second inverter leg. The open circuit fault causes a loss of the phase current reversibility of the upper switch T1 . Therefore, the current of the faulty leg becomes connected to the negative potential of the dcbus voltage through bypass diode D4 , when gate signal S1 is at high level and phase current ia is positive. During the interval where phase current ia is negative, the inverter’s behavior is the same as under healthy operating conditions. Here, it is clear that the measured line-to-line voltage uab depends on the switching-gate signals and the sign of phase current ia . So, line-to-line voltage uab is interpreted as follows: if ia > 0 and S1 = S2 = 1 (∀ sign ib )
⇒ uab = −vdc
(2)
if ia > 0 and S1 = 1 and S2 = 0 (∀ sign ib ) ⇒ uab = 0
(3)
if ia < 0 and S1 = S2 = 1 (∀ sign ib )
(4)
⇒ uab = 0 if ia < 0 and S1 = 1 and S2 = 0 (∀ sign ib ) ⇒ uab = vdc .
(5)
Table 2 summarizes the different possible states of the line-toline voltage uab for a healthy inverter and when an open circuit fault of the upper IGBT T1 occurs, where ‘‘fault’’ denotes the cases in which the fault can be detected and ‘‘no-fault’’ denotes the cases in which the fault is undetectable.
Here, it is important to underline that the fault can be identified in four cases according to the phase currents signs and the switching pattern. These cases correspond to a positive alternation of phase current ia and when gate signal S1 is at high level. Otherwise, the fault is undetectable. 3.2. Post-fault behavior for an open circuit of the lower switch in leg a (T4 ) Fig. 4 presents the switches’ conduction states and current paths in two inverter legs when the lower transistor T4 is faulty. With similar observations, when current ia is negative and gate signal S4 is at high level, the phase current of the faulty leg becomes connected to the positive potential of the dc-bus voltage through bypass diode D1 . Otherwise, if phase current ia is positive, the inverter operates under normal conditions and the drive system behavior is the same as under healthy operating conditions. Measured line-to-line voltage uab can be changed according to the switching pattern and the sign of the phase current uab , therefore: if ia > 0, S1 = 0 (S4 = 1) and S2 = 1 (∀ sign ib )
⇒ uab = −vdc
(6)
if ia > 0, S1 = 0 (S4 = 1) and S2 = 0 (∀ sign ib ) ⇒ uab = 0
(7)
if ia < 0, S1 = 0 (S4 = 1) and S2 = 1 (∀ sign ib ) ⇒ uab = 0
(8)
if ia < 0, S1 = 0 (S4 = 1) and S2 = 0 (∀ sign ib )
⇒ uab = vdc .
(9)
Table 3 presents line-to-line voltage uab for both a healthy inverter and when an open circuit fault of the lower IGBT T4 occurs. Similarly to the previous case, the fault of the lower transistor can be detected in four cases (denoted by: Fault). These cases correspond to a negative alternation of phase current ia and when gate signal S4 is at high level. During the positive alternation of the phase current, the fault is undetectable. 3.3. Post-fault behavior for simultaneous open-switches (e.g. T1 and T5 ) Other possible fault combinations can appear in the inverter legs (e.g. leg a and leg b); for example, the double fault involving
M. Trabelsi et al. / ISA Transactions 51 (2012) 333–344
337
Table 2 Line-to-line voltage for healthy inverter and when an open circuit fault of the upper switch T1 occurs. ia
>0
ib
>0
Dead time
>0
0, S1 = 0 and S2 = 1. (e) ia < 0, ib > 0, S1 = 0 and S2 = 0. (f) ia < 0, ib > 0, S1 = 0 and S2 = S5 = 0 (dead time in leg b). Table 3 Line-to-line voltage for a healthy inverter and when an open circuit fault of the lower switch T4 occurs. ia
ib
S1
T4 is faulty
D1
D4
D2
D5
uab
D1
D4
D2
D5
uab
On On Off Off
Off Off Off Off
On Off On Off
Off Off Off Off
0
Off Off Off Off
On Off On Off
Off Off Off Off
0
0
On On On On
vdc
Dead time
S1 = S4 = S2 = S5 = 0
On
Off
On
Off
0
On
Off
On
Off
0
No fault
On On Off Off
Off Off Off Off
Off Off Off Off
Off On Off On
0
0
On On On On
Off Off Off Off
Off Off Off Off
Off On Off On
0
0
1 1
1 0
Healthy inverter
T1 and T5 are faulty
uab
uab
0
vdc
vdc
0
Fault Fault
Dead time
S1 = S4 = S2 = S5 = 0
0
0
No fault
>0
1 1 0
0 0
−vdc −vdc −vdc
Fault Fault Fault
