IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING IEEJ Trans 2014; 9: 692–694 Published online in Wiley Online Library (wileyonlinelibrary.com). DOI:10.1002/tee.22027
Letter Realistic Model for the Multiple-Input Floating-Gate Transistor Luis Fortino Cisneros-Sinencioa∗ , Non-member Alejandro Diaz-Sanchez∗∗ , Member Jaime Ramirez-Angulo∗∗∗ , Non-member, Hector Vazquez-Leal∗ , Non-member Multiple-input floating-gate transistor (FGMOS) circuit designers face a serious problem along the design process: the lack of a realistic simulation model. For this reason, a solution that properly predicts the initial voltage at the floating gates is presented in this paper. In order to assess the performance of the proposal, a comparison is made against a test circuit fabricated in a 0.5-μm On-Semiconductor CMOS process. Based on this comparison, the proposed model is shown to be a fundamental tool in the design of FGMOS circuits. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. Keywords: FGMOS circuit design, circuit simulation, device modeling
Received 9 January 2013; Revised 9 October 2013
1. Introduction
2. Electrical Model for the FGMOS Transistor The proposed electrical model for an n-input n-FGMOS transistor is shown in Fig. 2. In this model, V1 , V2 , . . . ,Vn are the input voltages, C1 , C2 , . . . ,Cn are their corresponding input capacitors, a
Correspondence to: Luis F. Cisneros-Sinencio. E-mail:
[email protected]
* Veracruzanian University, Cto. Universitario los Lagos s/n, Xalapa, Ver 91000, Mexico ** National Institute for Astrophysics, Optics and Electronics, Luis E. Erro No. 1, Tonantzintla, Pue 72840, Mexico *** New Mexico State University, 1600 Steward Street, Las Cruces, NM 88003, USA
ln1 ln2
Drain Floating gate
ln3
Source
Substrate
Bulk
Fig. 1. Layout of a three-input FGMOS transistor Vsub V1 V2 ....
Currently, floating-gate metal–oxide–semiconductor (FGMOS) transistors represent a promising alternative for the construction of analog and digital circuits[1,2]. Unfortunately, circuit designers face an important problem: the lack of a reliable simulation model, which is fundamental to correctly predict the behavior of an integrated circuit prior to its fabrication. Even when several models for FGMOS transistors have been previously proposed [3–6], these models are limited to restricted conditions which can be impracticable to implement in complex circuits. For example, the model in Ref. [4] constrains the transistor to a specific region of operation, and the one in Ref. [5] requires all power and stimuli sources to be initially zero. Another common limitation is that the initial charge at the floating gate is considered as, at best, the charge induced by the transistor itself [6], ignoring any charge that could be trapped in the floating gate due to fabrication errors or other stochastic phenomena. Moreover, none of the above models considers the total capacitance of the floating gate, by ignoring the coupling to the substrate beyond the transistor. To illustrate this problem, consider the layout of the FGMOS transistor in Fig. 1. Notice that the floating gate couples the terminals of the transistor (i.e. source, drain, and bulk) not only to the input terminals but also to the substrate below the input terminals. As this coupling could be the largest among the capacitive network, it is essential to accurately predict the behavior of the FGMOS transistor.
Vn
C1 C2
Cn
Cfg
Cgd
VFG
G
D
Cgb Cgs
M1
ILeak S
Fig. 2. Electrical model for an n-input FGMOS transistor and VFG is the voltage at the floating gate that controls the transistor M1 . As part of M1 are the parasitic capacitances from gate to source drain and bulk (Cgs , Cgd , and Cgb , respectively), while the coupling from the floating gate to the substrate beyond the transistor is represented as Cfg with Vsub the substrate voltage. Additionally, the current source ILeak is introduced to model the behavior of the circuit under conditions in which the gate leakage gets worse (e.g. because of variations in the oxide characteristics) in analyses such as Monte Carlo simulations. Additionally, ILeak can be used to simulate charge fluctuations at the floating gate due to parasitic couplings not considered in the model (e.g. crosstalk). Therefore, the charge at the floating gate (QFG ) can be calculated as the initial charge (Q0 ) plus the charge contributions from all the couplings to the floating gate, namely the contributions from the inputs through their corresponding capacitors, from the transistor terminals through Cgs , Cgd , and Cgb , and from the substrate through
© 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
REALISTIC MODEL FOR THE MULTIPLE-INPUT FLOATING-GATE TRANSISTOR
Cfg . Thus, as an outcome of QFG , the voltage at the floating gate can be calculated by VFG =
n k=1
Vk
Analog output buffer
Digital output buffer
Cgd Cgs Cgb Cfg Ck Q0 + Vd + Vs + Vb + Vsub + CT CT CT CT CT CT (1)
where CT is the total capacitance associated with the floating gate (i.e., C1 + · · · + Cn + Cgd + Cgs + Cgb + Cfg ). Observe that the introduction of Q0 allows the simulation of a charge trapped at the floating gate, as happens in real circuits, to achieve realistic results. As for the calculation of CT , several sets of equations define the parasitic capacitances of the transistor [7]; the appropriate set must be selected depending on the accuracy or simplicity desired. Lastly, Cfg is the area of the floating gate that is outside the transistor by the capacitance per area provided by the manufacturer. Once VFG is obtained, this value is used as the initial condition for the corresponding node using the .IC statement. Since VFG is calculated using the actual conditions in the circuit, the validity of the model is no longer constrained to certain analyses or conditions. After the operating point is found, the calculation of VFG will be handled by the circuit simulator according to the voltages coupled to the floating gate and the behavior of ILeak . Since Cgs , Cgd , and Cgb are part of the MOS transistor model (e.g. BSIM), the circuit simulator will handle any change in their value even if the transistor operates in multiple regions. As for Vsub , this is a DC voltage and no changes are expected from Cfg . However, this coupling is part of the FGMOS capacitive network, and thus necessary for the circuit simulator to accurately predict VFG . In the case where the substrate is not tied to a DC voltage (e.g. to simulate noise from the substrate), Vsub must be defined accordingly. To obtain the value of ILeak and Q0 , several experimental methodologies have been proposed [8], although it is advisable to systematically establish a window of possible values for these variables and test the circuit within them to assess the robustness of the circuit to these phenomena.
VDD M1
Out a b c Vbias
Cin1 Cin2
M2
Cin3
Out
M3
Cin4 Cin5
M4
Cin6
Sw1
Sw2
a b c Vbias
Fig. 3. Test chip consisting of a three-input PFFGL gate
Measured Simulated DC sweep
3.0 2.5
Vout
2.0 1.5 1.0 0.5 0.0 –0.5 0.0
0.5
1.0
1.5 Vin
2.0
2.5
3.0
Fig. 4. DC sweep obtained by measurement and simulation
3. Experimental Verification The comparison of the DC characteristics obtained by measurement and simulation are shown in Fig. 4. The results show that, while measurements establish the gate threshold at 1.04 V, simulations of the transient response establish the gate threshold at 1.05 V and the DC sweep at 1.08 V. Although there is a deviation between the three results, the error can be attributed to parametric variations, to the step size of the DC sweep, and to differences in the methodologies followed to obtain the DC characteristics.
To demonstrate the accuracy of the proposed model, the threeinput floating-gate circuit in Fig. 3 has been fabricated under an On Semiconductors 0.5-μm double polysilicon CMOS process. The circuit was fabricated using 1.5 μm/0.6 μm p-MOS transistors, 3.0 μm/0.6 μm n-MOS transistors, and 20 fF capacitors. In order to simulate a residual charge, the floating gates are connected to a known voltage of 0.8 V (Vbias ) through a switch, while the source voltage (Vdd ) is 3 V. As the initial voltage at the floating gate is known (Vbias ) as well as their total capacitance (CT ), the initial charge is also known (Q0 = Vbias × CT ). To drive the probe load for on-chip measurement, a buffer is connected to each of the outputs of the FGMOS gate. As the gate current under this process is negligible, ILeak is taken as zero. Lastly, according to the calculations, Cfg turned out to be 17 fF while Vsub was tied to ground. To obtain the DC characteristics of the test chip, Sw1 and Sw2 were closed to induce Vbias to the floating gates while all the inputs were set to ground. Next, the transient response was measured while applying a slow slope function (Vin ) to one of the inputs just after the switches Sw1 and Sw2 were open. On the other hand, H-SPICE simulations using the proposed model were carried out to obtain the transient response of the circuit while the same slow slope function Vin was applied to one of the inputs assuming Q0 = 0.8 VCT . Additionally, even when for a DC analysis the capacitors behaved as open circuits, a DC sweep was performed using the proposed model by calculating VFG within the range of DC conditions to obtain the DC transfer curves of the test circuit.
4. Conclusion In this paper, a model that accurately predicts the behavior of the FGMOS transistors was proposed. As this model is not constrained to specific conditions, it is valid under a wide variety of analysis scenarios. In a comparison with those of an FGMOS test chip, the results showed that the model correctly predicted the behavior of the circuit. Thus, the main advantage of this simulation model is the ability to appropriately represent the behavior of the floating gate, including parasitic phenomena such as leakage and trapped charge, which is not possible with most commonly used analyses in circuit design. References (1) Keles S, Kuntman HH. A new differential voltage current conveyor. IEEE 19th Conference on Signal Processing and Communications Applications, 558–461, 2011. 693
IEEJ Trans 9: 692–694 (2014)
L. F. CISNEROS-SINENCIO ET AL. (6) Inoue T, Nakane E, Fukuju Y, Sanchez-Sinencio E. A design of a lowvoltage current-mode fully-differential analog CMOS integrator using FG-MOSFETs and its implementation. Analog Integrated Circuits and Signal Processing 2002; 32:249–256. (7) Smith MJS. Application-Specific Integrated Circuits. Addison-Wesley; 1997. (8) Zaka A, Garetto D, Rideau D, Palestri P, Manceau J, Dornel E, Rafhay Q, Clerc R, Leblebici Y, Tavernier C, Jaouen H. Characterization and modelling of gate current injection in embedded non-volatile flash memory. IEEE International Conference on Microelectronic Test Structures, Crolles, France, 2011.
(2) Siskos S. FGMOS based built-in current sensor for low supply voltage analog and mixed-signal circuits testing. IEEE Computer Society Annual Symposium on VLSI, 2010; 259–264. (3) Rapp SJ, McMillan KR, Graham DW. SPICE-compatible modelling technique for simulating floating-gate transistors. IET Electronics Letters 2011; 47:483–485. (4) Yin L, Embabi SHK, S´anchez-Sinencio E. A floating-gate MOSFET D/A converter. Proceedings of the IEEE International Symposium on Circuits and Systems 1997; 1:409–412. (5) Rodr´ıguez-Villegas E, Huertas G, Avedillo MJ, Quintana JM, Rueda A. A practical floating-gate Muller-C element using vMOS threshold gates. IEEE Transactions on Circuits and Systems II 2001; 48:102–106.
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IEEJ Trans 9: 692–694 (2014)
