Reducing embedded SRAM test time under redundancy ... - UBC ECE

Reducing Embedded SRAM Test Time under Redundancy Constraints Baosheng Wang1, Josh Yang1, James Cicalo1, André Ivanov1 and Yervant Zorian2 1 SOC Lab, Department of Electrical & Computer Engineering, University of British Columbia, Vancouver, B.C., Canada, V6T 1Z4, {baosheng, joshy, jamesc, ivanov}@ece.ubc.ca 2 Virage Logic Corporation, [email protected] Abstract Increasingly dense SRAMs of various bit capacities, embedded within current and future Systems-on-a-Chip (SoC) designs, command not only additional complexity due to required redundancy schemes, but also present serious challenges in regards to testing. In particular, the time needed for testing data retention faults (DRFs) and Non-DRFs is growing rapidly. In this paper, we consider the Overall Production Gain (OPG) and delay time associated with the testing of DRFs as the two selection factors for classifying embedded SRAMs, where OPG quantifies the trade-offs between yield and redundancy area overhead. These embedded SRAMs are categorized into four categories for testing Non-DRFs and DRFs. Since both factors above are related to memory capacity, the four categories are named as very small, small, large, and very large types. According to this simple classification, we generate a set of four March test algorithms from an existing March SRD algorithm for each category respectively. As a comparison with March SRD, our investigations reveal that test time can generally be at least halved down to 22nm technology for all capacity e-SRAMs with different IO numbers without losing defect coverage. The evaluation results also show that this reduction ratio is always no less than 50% for those with larger and larger and larger capacity predicted for future e-SRAMs in ITRS documents no matter what complex the comparison algorithms besides March SRD are. Keywords: Embedded SRAMs, March Tests, Memory testing, Memory Test Time, Memory Redundancy

1. Introduction The System-on-a-Chip (SoC) paradigm is associated with a trend from logic-dominant chips to memory-dominant ones. An increasing number of memories with various capacities, e.g., SRAMs, are embedded into the emerging SoCs. Increasingly dense embedded SRAMs (e-SRAMs) are more prone to faults. This not only reduces memory and SoC yield thereby increasingly making redundancy a must, but also poses large test challenges, in particular the overall time for testing both data retention faults (DRFs) and remaining faults named as Non-DRFs in this paper.

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004) 1093-0167/04 $20.00 © 2004 IEEE

Due to the mixed-signal nature of SRAMs, defect-based algorithms, e.g., March SRD from [2], can achieve higher defect coverage than functional-based ones, e.g., [1]. Previous work on reducing the Non-DRFs test time for eSRAMs under defect-based fault models mainly focuses on parallel test algorithms, e.g., those from [3] or the smart test algorithms that consider post-test redundancy schemes, such as those in [4]. However, parallel test algorithms are limited in reducing the test time of multiple memories under increasingly tight power constraints. Obviously, applying them only is not effective at reducing test time when the capacity of the different multiple SRAMs varies considerably. By more tightly coupling the test and repair activities and capabilities in [4], the FFM2 faults mapped from defects and described in [2] are simplified, and consideration is given to the row/column redundancy schemes toward greatly reducing test time without negatively impacting defect coverage. Normally, different capacity e-SRAMs are augmented by different redundancy techniques according to the Overall Production Gain (OPG) [5] factor that quantifies the trade-offs between yield gain and redundancy area overhead. The algorithm as described in [4] can only be considered optimal under specific assumptions, namely that row/column redundancy schemes are used. Unfortunately, it cannot be effective for e-SRAMs with word redundancy schemes or without redundancy schemes (Non-redundancy). These word redundancy schemes are usually those deemed more effective for memories with no larger than 4Mb density in 180nm technology according to the OPG qualifications reported in [5]. In reality, redundancy schemes are not used for very tiny e-SRAMs due to cost considerations. Previous defect-based literature on reducing the test time of DRFs focuses on shortening the delay time for DRFs through test algorithms [4] or on completely removing the delay time for DRFs from the test flow by applying various Design-for-test (DFT) techniques [6-10]. In [4], it is pointed out that this delay time can be effectively eliminated in the case of large capacity SRAMs by effecting the test and test control sequences in specific manners. However, such delay cannot be eliminated typically when testing a large number of small capacity SRAMs, such as those typically found on SoC platforms. When the memory capacity becomes larger, the test time

caused by the extra DFT cycles in [6-10] becomes longer than the removed delay time for DRFs and thus become a penalty. Overall, the above mentioned techniques for reducing both parts of the test time for e-SRAMs deal with the memory capacity and the current universal algorithms cannot test e-SRAMs of any capacity with timingefficient strategies. In this paper, with the goal of reducing test time for embedded SRAMs, we consider the OPG quantification and the delay time for DRF tests as the two deciding factors for testing the Non-DRFs and DRFs. Based on this consideration, e-SRAMs are categorized into four groups: very small, small, large, and very large capacity. Accordingly, we select four corresponding March test algorithms, generated from a comparison algorithm, by combining the advantages of the methodologies proposed in [4] and the DFT technique from [10] since the two concepts currently have the highest test time reduction rates and can be applied jointly to any March test algorithm. The remainder of this paper is organized as follows. In Sec. 2, the methodology for categorizing e-SRAMs by considering both OPG and the delay time for DRF tests is described in detail. In Sec. 3, the test time evaluations in terms of memory capacities, number of I/Os, technology scaling trends and March algorithm impacts are presented and discussed. Finally, Sec. 4 draws some conclusions.

2. Test Concepts

Although functional fault models tend to be easily developed and formulated, difficulties lie in establishing test results from these models that properly reflect yield. Defect-based fault models, e.g., fault models created under Inductive Fault Analysis (IFA) [11] (IFA fault models), are more attractive in terms of yield and defect level results. This is due to their realistic nature since IFA faults are actually translated from physical defects. Hence, in this paper, all the functional faults in [2] are revisited from a defect point of view using the IFA technology. D isable & W a it

T ra d itio na l

TDF

P ro p o se d in [4 ] TDA

The new TDF (TDNF) in the test flow of [4] can be quantified as TDF – TDA, where TDA is dependent on many factors, e.g., memory architecture, test clock period, test sequence, etc. Two typical accessing methods: accessing cells row-by-row and accessing cells column by column, are shown in Figure 1. The DRF test delay time in the proposed test algorithms is quantified from the TDNF using the row-by-row accessing method instead of the TDF. To maintain other March algorithms referenced in this paper, TDF is still used instead of TDNF. A number of different redundancy techniques are generally applied towards reducing memory yield loss. The selection of appropriate redundancy techniques, shown in Figure 2, is usually done according to the tradeoff between the final yield and the redundancy area overhead, e.g., OPG in [5]. If the OPGrc (OPG using row/column redundancy) value is higher than OPGw (OPG using word redundancy) value, the row/column redundancy can be used. Otherwise, the word redundancy is selected. Proposed in [5]

Proposed in this paper Redundancy Schemes Selections

Redundancy Schemes Selections

Y

OPGw > OPGrc

N

Row/Column Word Redundancy Redundancy Note: OPGrc: OPG with Row/Column Redundancy OPGw: OPG with Word Redundancy Y TOH: Overhead Test Time due to DFT k: redundancy adjust factor

2.1 Background

A ccessing S e quences

algorithms can be reduced. This reduction is due to the inherent delay of re-accessing the same memory cell in actual tests, and is quantified as Test Delay Access (TDA) time. The quantification process is shown in Figure 1.

TDNF

TDF = TDNF + TDA

R o w b y ro w a d d re ss se q ue n cin g : w o rd lin e re o p e n a fte r a cce ssin g o th e r (2 x - 1 ) * 2 Y ce lls C o lum n b y C o lu m n a d d re ss se q u e n cin g: w o rd lin e re o p en a fte r a cce ssin g o th e r (2 x - 1 ) ce lls X : R ow A ddress N um ber; Y : C olum n A ddress N um ber; T P : T est C lock P eriod (ns)

Figure 1. DRF test time reduction DRF testing is traditionally done by performing a read operation after a certain pre-determined delay denoted by TDF. According to [4], the applied TDF in the test


Very Small: Word Redundancy & DFT

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OPGw > k * OPGrc

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TDNF > TOH N Large: Row/Column Redundancy & DFT

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Y Very Large: Row/Column Redundancy & Delay

Figure 2. Classify e-SRAMs with redundancy

2.2 Classifications of e-SRAMs for Testing Based on the OPG in [5] and the delay time of DRF tests, the e-SRAMs with redundancy schemes in SoCs can be divided into four categories for test and repair. The proposed division process in this paper is also shown in Figure 2. In [5], as long as the OPGw value is higher than the OPGrc value, word redundancy is selected as the repair technique instead of row/column redundancy. In this paper, row/column redundancy rather than word redundancy is applied if the OPGw value is slightly higher than the OPGrc value. A user-defined k based on the trade-offs among cost-related elements is used as the adjustment factor. The reason for this criterion is that more test time can be reduced under the row/column redundancy scheme, according to [4]. For DRF testing, either a certain delay time (TDNF) or a DFT technique

that circumvents the delay time requirement has to be used. If the necessary delay TDNF is more than the TOH (test time overhead due to extra DFT cycles), DFT techniques are applied. Otherwise, only the delay time is used. It is observed from [5] that row/column redundancy schemes are applied on the larger capacity e-SRAMs. On the contrary, smaller capacity memories cause a larger TDNF. As a result, we classify those memories with redundancy schemes into four categories: very-smallcapacity e-SRAMs (using word redundancy & DFT); small-capacity e-SRAMs (using word redundancy & Delay); large-capacity e-SRAMs (using row/column redundancy & DFT); and very-large-capacity e-SRAMs (using row/column redundancy & Delay). For e-SRAMs without redundancy schemes, we simply consider them as part of the “very-small-capacity” category since i) in reality, their capacities are smaller than any of those with redundancy schemes due to cost considerations; ii) for all the existing test time reduction techniques, there is no difference between them and those with word redundancy.

2.3 e-SRAM Non-DRF Tests Using Redundancy Features In [2], FFM2 denotes functional faults involving two memory cells. Mostly, these faults are caused by bridge defects between two cells. According to physical defect locations instead of different faulty behaviors, if the fourcell configuration in Figure 3 is used, these FFM2s were simplified from five categories in [2] into three types in [11]: Row Coupling Faults (RCFs), Column Coupling Faults (CCFs) and Diagonal Coupling Faults (DCFs). This simplification follows from the fact that the defects causing these faults can be considered to be located between rows, columns and diagonals.

Figure 3. Four-cell memory configuration Since these coupling faults are caused by physical bridge defects, they behave as a cell pair with bi-directional impacts: aggressor and victim. The aggressor cell and the victim cell are named according to the accessing sequence. Usually, the first cell accessed is referred as the victim cell since the next cell accessed of the pair couples the first cell. Obviously, the victim cell will become a good cell as long as the aggressor disappears, e.g., repaired. According to row/column redundancy mechanisms, only redundant rows/columns, not faulty ones, are accessed. Thus, if one of the cell pairs is detected using one of the two address sequences (increasing or decreasing) and repaired using row/column


redundancy techniques, the other cell (victim) automatically becomes a good cell. In other words, as shown in [4], detecting with one address sequence and repairing any faulty cell of a pair due to bridges with row/column redundancy techniques can achieve the same yield as that obtained by performing both address sequencing in the pair. This can be validated through defect injections and following fault detections [4]. Clearly, using one address sequence to achieve the same defect coverage as that obtained by using any defectbased March algorithm reduces the Non-DRF faults test time, by a factor of 2 or more. However, the word redundancy or non-redundancy scheme cannot be applied here since neither are able to achieve the same defect coverage as when using the row/column redundancy. This is because both the repaired cell and the faulty cell are accessed at the same time when using word redundancy, e.g., [12].

2.4 e-SRAM Tests to Detect DRFs In this paper, when TDNF is longer than TOH, we eliminate this TDNF but create TOH by choosing an existing low-penalty DFT, NWRTM [10] to reduce the test time of DRFs. Like the methodology in [8] and [9], in NWRTM, a special write cycle is created to distinguish a good cell from a faulty cell when subjected to a DRF caused by an open defect on the pull-up PMOS. In this section, a typical 6T SRAM cell with storage node A and complementary storage node B, shown in Figure 4, is used to illustrate the differences between the specifically designed write cycle and the normal write cycle.

Figure 4. A Typical 6T SRAM Cell During the normal W1 cycle, node B is pulled down by the bitline BLb that is driven to strong GND by the write control logic, and node A is pulled up due to the charge sharing with the floating bitline BL that has already been pre-charged to VCC. Here, strong GND means that the node is driven to the GND voltage level by other sources. Due to the latch mechanism of the memory cell, the cell flips its value from ZERO to ONE as long as the voltage level of node B is pulled to a sufficiently low level. In algorithms from [8] and [9], by setting the bitlines BL and BLb to a given voltage level between VCC and GND during the write operation, e.g., when the access NMOS is

on, a good cell fails to flip while a faulty cell does. Similarly, we set the voltage level of BL and BLb to weak GND and strong GND respectively. Here, weak GND means the node voltage level is at GND but no sources drive this node. This causes an opposite result, i.e., a good cell succeeds at flipping its logic value while a faulty cell fails to do so. For a good cell, there is no problem writing a ONE because node B can be pulled down by the bitline BLb and the cell can flip to ONE due to the latch mechanism. However, a faulty cell subject to a DRF fails to flip because the voltage level of node A never exceeds that of node B. The voltage level of node A always remains at GND since (i) lacking the PMOS or path to the supply rail, node A cannot be pulled high regardless of how low the node B voltage level reaches, so the latch in this faulty cell malfunctions; and (ii) there are no charge sharing effects with bitline BL because it is set at weak GND. GND is the lowest achievable voltage level and node A remains at GND, the voltage level of node A never exceeds that of node B and the faulty cell fails to flip. As a result, DRFs are detected under NWRTM.

delay is the necessary TDF for Figure 5 and TDNF for others respectively discussed in Sec. 2, “Nw0/Nw1” represents writing 0/1 in the NWRTM. Moreover, either (a) or (b) test algorithms with different address sequencings in Figure 6 and Figure 7 can be used.

From [10], the NWRTM can be merged into any March test by simply adding two extra NWRCs just before its normal write cycles since it can share the same write operation mechanism, i.e., faulty cells will fail to flip during the test. In other words, NWRTM has the advantage of being mergable with any typical March test algorithm without incurring additional test patterns. Other DFT techniques do not share this advantage. Hence, NWRTM is the best in terms of test time reduction for DRFs among all existing DFT techniques.

Figure 8. March 10N Test Algorithm

w0

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Figure 5. March SRD Test Algorithm w0

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Figure 6. March 6N Test Algorithm Nw 1

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Figure 7. March 8N Test Algorithm w0

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Figure 9. March 12N Test Algorithm OPGw O P G rc

R edundancy Schem e

TND F Toh

N /A

N on

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>= 1.01

W ord W ord

>= 1 = 1.01

< 1.01 R ow /C olum n < 1.01 R ow /C olum n

>= 1 < 1

D R F Test C lassification Algorithm s Strategy N W R TM

Very Sm all

12N

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Figure 10. Summary of Test Algorithm Selections

3. Test Time Evaluations

3.1.2 Test Time Quantifications

Since the concepts in Sec. 2.3 and 2.4 have been validated in [4] and [10] respectively, this section evaluates the test time of all capacity memories to show the advantages of the proposed classification.

The row address number X is assumed to be equal to the column address number Y (even total address number) or one more than Y (odd total address number) in order to minimize the physical layout area. Moreover, in this section, the test clock period (TP), TDF, and the IO numbers are assumed to be 50ns (the same as in [8]), 100ms, and 8 bits respectively. The technology used is 180nm.

3.1 A Case Study 3.1.1 Test Algorithm Generations Since test concepts in Sec. 2 are based on March algorithms, we select a typical defect-based test algorithm with high defect coverage, e.g., March SRD from [2] shown in Figure 5, to generate March test algorithms for each category memories in this study. Named according to their complexities, these four time-efficient algorithms and their selection summary are shown in Figure 6 (a) or (b), Figure 7 (a) or (b), Figure 8, Figure 9 and Figure 10 respectively, where “

” means the address sequencing is

” means the address increasing during the test, “ sequencing is decreasing during the test. In addition,


According to Figure 2, we assume that word redundancy is used in e-SRAMs with less than 2 Mb densities since (OPGw – OPGrc) / OPGw is 0.98% for 2.5Mb in [5]. Using the 8bit IO assumption above, the e-SRAMs with less than 256KB use word redundancy (k is assumed as 100.98% in this study) and the others use row/column redundancy, assuming 180nm technology. Based on the concepts in Sec. 2 and the test algorithms above, we evaluate the memory test time with the following flow chart, shown in Figure 11, when using the four proposed test algorithms.

From Figure 13, for frequently used IO numbers, we can apply the proposed test algorithms to achieve a total test time reduction of more than 50 percent for all capacity eSRAMs in 180nm technology.

S ta r t: M e m o r y u n d e r T e s t

D e fin e Y , T P , T D F ( IO = 8 ) , X = Y o r X = Y + 1 T N D F = T D F - T P * ( 2 x - 1 ) * 2 y, T o h = T P * 2 x+y T o ta l T e s t T im e fo r M a r c h S R D : 1 4 * 2 x + y * T P + 2 * T D F

M e m o r y C a p a c ity > 256KB

Y

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M a rc h 1 0 N

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T o ta l te s t tim e : 1 2 * 2 x+y * T P

T o ta l te s t tim e : 1 0 * 2 x+y * T P + 2 * TNDF

3.3 Technology Trends

TNDF > TOH

TNDF > TOH

M a rch 8 N

T o ta l te s t T im e : 8 * 2 x+y * T P

T o ta l te s t T im e : 6 * 2 x+y * T P + 2 * TNDF

T e s t T im e R e d u c tio n P e r c e n ta g e s : ( 1 - T o ta l _ tim e ( x N ) /T o ta l_ tim e ( S R D ) ) * 1 0 0 , w h e r e x = 6 , 8 , 1 0 , 1 2

Figure 11. A Flow Chat of Test Time Evaluation The reduction percentages in terms of memory capacity, compared with that of March SRD, are shown in Figure 12 and their corresponding classifications are shown in Table 1.

Reduction

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Test Tim e Reduction vs. Mem ory Capacity 100 90 80 70 60 50

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Figure 12. e-SRAMs Test Time Reductions Table 1. Classifying e-SRAMs under 8 bits IO X+Y … 17 18 19 20 21 … 6N (%)

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As shown in Figure 12 and Table 1, in this case study, using different time-efficient test algorithms, the test time of various capacity e-SRAMs can be reduced by a percentage of 50% or greater.

3.2 IO Number Effects The number of IOs for e-SRAMs may vary depending on applications. Following the evaluation steps above and using the same other assumptions except for the number of IOs, the test time reduction evaluations for e-SRAMs of 4, 8, 16 and 32 bit IOs are shown in Figure 13.

(%)

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Test Tim e Reduction vs. Mem ory Capacity 100 90 80 70 60 50

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Figure 13. Evaluating Test Time Reduction Considering IO Numbers


Test Tim e Reduction vs. Mem ory Capacity

180nm 130nm

100 90 80 70 60 50

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On one hand, both the yield and the redundancy area overhead are related to the entire physical layout area. Thus, if the total memory area is kept the same, the OPG does not change. Therefore, the division line between which memory capacity is appropriate for word redundancy and which is appropriate for row/column redundancy increases twice per technology node. This is true since the transistor number in a fixed layout area increases twice per technology node. Reduction Percentage (%)

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14 16 18 20 22 Memory Capacity (X + Y)

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32nm 22nm

Figure 14. Evaluating Test Time Reduction Considering Technology Trends On the other hand, the on-chip Built-in-self-test (BIST) clock period (TP) is also shrinking based on the technology nodes. According to the on-chip clock frequency in Table 4a of the ITRS1999 document [13] and Table 4c of the ITRS2001 document [14], the on-chip clock period is predicted to decrease by the following factors for each technology step, starting at the 180nm to 130nm step, and ending at the 32nm to 22nm step: 1.403, 2.37, 1.690, 1.710, 1.681, and 1.486. The TP reduction ratios are assumed to have the same trend as that of an onchip clock. By maintaining other assumptions, the evaluation results when varying the technology nodes are shown in Figure 14. Figure 14 shows that when compared with March SRD, the proposed test algorithm achieves more than a 50 percent reduction of the overall test time for all the memories, without a loss of test quality. This trend holds true at least down to the 22nm technology node.

3.4 March Algorithm Complexity Impacts The March Algorithms for e-SRAMs test may vary depending on the defect coverage requirements. Following the evaluation steps above and using the same other assumptions in the case study except for the different comparison March algorithm, the test time reduction evaluations for March 9N [4], March SRD (14N) [2] and Symmetric March G (24N) [15] are shown in Figure 15.

6. References [1]

Figure 15. Evaluating Test Time Reduction Considering March Algorithm Complexity Impacts From Figure 15, it can be seen that the higher the March algorithm complexity the more the total test time reduction, e.g., more than 50%, when the memory capacity is large enough, e.g., those with row/column redundancy. It is also can be derived from the test time quantification procedure that the reduction ratio will not always more than 50% if the March algorithm is complex enough, e.g., March 50N.

4. Conclusions More and more embedded SRAMs of various capacities occupy larger and larger area percentages within current and future SoCs. Increasingly dense e-SRAMs present a challenge in terms of test time. There are no universal time-efficient test algorithms. The parallel test algorithm proposed in [3], the smart test algorithm that considers the post-test redundancy schemes in [4], and DFT-based test algorithms in [6-10] are not suitable to cover all capacity e-SRAMs in reducing the overall test time. By reviewing all the test time reduction techniques under the defect-based fault models, OPG in [5] and the new delay time (TDNF) for DRF tests in [4] are selected to classify e-SRAMs into four categories and these memories are tested with different time-efficient test algorithms in order to reduce their overall test time as much as possible. The entire test time reduction evaluations show that the classification can achieve test time reductions by more than a factor of two at least down to 22nm technology for all capacity e-SRAMs with different IO numbers when compared with March SRD algorithm in this paper. No matter what the comparison March algorithm complexity is, the test time reduction ratio is always no less than 50% for the memories with row/column redundancy and larger and larger capacity predicted in the ITRS documents.

5. Acknowledgements We wish to thank Gennum, NSERC, Micronet and the Canadian Microelectronics Corp. for providing financial support. We also thank Partha Pande for invaluable comments to this paper.


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