RID-GRASP: Redundancy Identification and Removal Using GRASP Joonyoung Kim
[email protected]
João P. M. Silva
[email protected]
Abstract Redundancy identification and removal is a critical step that typically follows logic synthesis or optimization. In principle, it should be possible to restrict the transformations applied by synthesis and optimization algorithms to those that preserve testability. In practice, however, few, if any, synthesis programs can guarantee the irredundancy of the logic circuits they produce. It may also be argued that identifying and removing redundancy as a post-processing step affords synthesis tools greater flexibility in restructuring the logic. This paper presents RID-GRASP, an ATPG-based redundancy identification and removal system. Unlike structural analysis-based redundancy removal algorithms, ATPG-based systems can guarantee 100-percent redundancy removal assuming there is no aborted fault. But the downfall of this approach is that it can show its worst case behavior for redundant faults. GRASP, a new search algorithm for boolean satisfiability is known to show good performance in proving unsatisfiability. GRASP is used to prove the redundancy of a logic element in our redundancy removal system. The most notable feature of RID-GRASP is that it can implicitly remove a redundancy in a logic circuit by simply setting a constraint in the CNF (conjunctive normal form) representation of the circuit without changing the circuit structure.
1. Introduction The presence of redundancy in logic circuits can have several undesirable effects. Although undetectable faults don’t affect the operation of the circuit, they may invalidate the completeness of a test set that was generated for the unfaulted circuit [2]. This is one more reason why redundancy removal is necessary besides economy. Two major approaches have emerged for the identification of redundant elements in a logic circuit. The first relies on the use of automatic test pattern generation (ATPG) to prove the untestability of redundant lines [9]. Thus, this approach can be viewed as a by-product of ATPG. While completely general, ATPG algorithms typically exhibit their worst-case exponential behavior when applied to undetectable faults. The other approach is faultindependent: it is based on analyzing the structure of the
Hamid Savoj
[email protected]
Karem A. Sakallah
[email protected]
logic circuit, particularly the reconvergent fanout regions, in order to determine necessary conditions for fault undetectability [3]. Such analysis cannot determine all untestable faults, but it can be much faster than ATPG, and is usually suggested as a pre-processing phase to ATPG. The cost of the final circuit produced after redundant lines and gates are removed depends on the order in which redundant faults are targeted and removed. This is caused by dependencies that may exist between faults; a redundant fault can mask another redundant fault or make a redundant fault detectable [1]. In [4], it was shown that some faults in a certain category can be removed concurrently while those in another category cannot be removed at the same time. In this paper we describe the algorithms and implementation of RID-GRASP, an ATPG-based redundancy identification and removal system. RIDGRASP is based on a modern search algorithm for CNF satisfiability called GRASP (Generic seaRch Algorithm for Satisfiability Problem) [7]. The rest of the paper is organized as follows. Section 2 briefly reviews GRASP and its relationship with RIDGRASP and Section 3 describes the algorithms and procedures used in RID-GRASP. Experimental results are presented in Section 4 and Section 5 concludes the paper.
2. Using GRASP in Redundancy Identification and Removal GRASP is an algorithmic framework for Satisfiability problems that arise in many fields of electronic design automation (EDA). The most notable feature of GRASP is its ability to analyze and record the causes of conflicts during its search for a satisfying assignment which, in turn, allows it to 1) augment its “clause database” with additional knowledge that may be helpful at later stages of the search, and to 2) backtrack non-chronologically, thus avoiding the search in large portions of the space that provably do not contain a solution. The effectiveness of the GRASP search engine has been amply demonstrated by comprehensive experimental results on a wide variety of benchmarks [6]. In earlier work, a boolean satisfiability based test pattern 1
RID-GRASP: Redundancy Identification and Removal Using GRASP
generator was developed with promising results [8]. Our redundancy identification and removal system, RIDGRASP, is based on this test pattern generator that we call TG-GRASP. The use of GRASP for redundancy identification and removal is particularly suitable because: ■
It is very efficient for solving unsatisfiable problems.
■
It accommodates the presence of redundancies by simply “fixing” the value of an undetectable stuck line, effectively imposing a restriction on the solution space for subsequent tests. It can be shown that such fixing is equivalent to “removing” the redundancy. Thus, the circuit need not be structurally modified until the end when all redundancies have been identified.
■
It has a mechanism for “tagging” CNF clauses so that only those clauses that are directly involved in the search for a test for a given fault are processed. This clause hiding feature improves efficiency.
3. Algorithms and Procedures
0 or 1. Once a redundancy is identified, it can be implicitly removed by fixing a value in clause database. As an example of how this is done, consider Figure 1. The CNF formula for a unfaulted 3-input AND gate can be expressed as follows: ( ¬Z + A ) ⋅ ( ¬Z + B ) ⋅ ( ¬Z + C ) ⋅ ( Z + ¬ A + ¬ B + ¬C )
(1)
If the fault C stuck-at-1 is undetectable as in Figure 1(b), we can remove the C input to the AND gate, thus effectively changing it into a 2-input AND gate. The CNF formula for this 2-input AND gate is ( ¬Z + A ) ⋅ ( ¬Z + B ) ⋅ ( Z + ¬ A + ¬ B ) We can obtain this formula by setting removing satisfied clause(s).
(2)
C = 1
and
Now consider C stuck-at-0 as in Figure 1 (c). In this case output of the 3 input AND gate is 0 regardless of values of A and B. The formula for 3-input AND gate with the constraint C = 0 and satisfied clause(s) removed is
In this section we describe redundancy removing techniques used in RID-GRASP and its basic algorithm.
( ¬Z + A ) ⋅ ( ¬Z + B ) ⋅ ¬Z
(3)
3.1 Setting a Value in CNF Formula
Since ¬Z is a unit clause, Z should be 0 to satisfy the clause database.
RID-GRASP creates a clause database in Conjunctive Normal Form (CNF) for the circuit under test and converts a test pattern generation problem to a satisfiability problem [5]. The presence of faults can be viewed as imposing a constraint that forces the value of the affected line to either
Now consider Figure 2 (a), a circuit with 3 gates. The CNF formula (clause database) for this circuit is obtained by taking the conjunction of formulas for all gates. A B
A B
Z
C
E G
C D
(a)
F s-a-1
A B C
Z s-a-1
A B
Z
(b)
A B
(a) E G
A B C
C
Z s-a-0
(c)
0
Figure 1: The effect of a redundancy in CNF formula (a) unfaulted gate (b) C s-a-1 (c) C s-a-0
F (b)
Figure 2: Fixing a variable in a circuit (a) before (b) after
2
RID-GRASP: Redundancy Identification and Removal Using GRASP
( ¬E + A ) ⋅ ( ¬E + B ) ⋅ ( E + ¬ A + ¬ B ) ⋅ ( ¬F + C ) ⋅ ( ¬F + D ) ⋅ ( F + ¬C + ¬D ) ⋅ ( G + ¬E ) ⋅ ( G + ¬F ) ⋅ ( ¬G + E + F )
(4)
Assuming that there is a redundant fault D stuck-at-1, we can set D to 1 in the clause database. The resulting formula is ( ¬E + A ) ⋅ ( ¬E + B ) ⋅ ( E + ¬ A + ¬ B ) ⋅ ( ¬F + C ) ⋅ ( F + ¬C ) ⋅ ( G + ¬ E ) ⋅ ( G + ¬F ) ⋅ ( ¬G + E + F )
(5)
Note that this is identical to the formula for Figure 2 (b), where the AND gate F is replaced with a buffer.
3.2 Redundancy Identification and Removal Procedure The pseudo-code for RID-GRASP is shown in Figure 3. RID-GRASP reads in a netlist C and a fault list F, and writes back an equivalent redundancy-free netlist. Basically, its operation consists of targeting each fault in F and invoking TG-GRASP to determine if that fault is detectable. Depending on the outcome, that fault is classified as detectable, redundant, or aborted. If redundant, the corresponding line is set to the stuck-at fault value by imposing a constraint on clause database. Since the presence of undetectable faults affects the detectability of other faults, all detectable and aborted faults are reinserted into the fault list F for subsequent processing. Redundancy identification terminates when all faults in F are detectable. Generation of the redundancy-free circuit is accomplished by propagating the fixed values found in the previous phase forward and backward through the circuit. This is followed by the actual removal of lines and gates that no longer affect the circuit output. It is worth noting that the same fault can be targeted several times if there are multiple dependencies between undetectable faults; the presence of a redundancy may invalidate the completeness of a test set and tests must be generated for already detected faults.
4. Experimental Results In this section experimental results from ISCAS 85 benchmark circuits are presented. RID-GRASP was prototyped in C++ and was compiled with g++ 2.7.2 and tested on Pentium Pro 200MHz machine running Linux with 128MBytes of RAM. In Table 1, “Number of passes” denotes the number of
RID-GRASP(netlist C, faultlist F) { // lists of detected, redundant // & aborted faults faultlist D = R = A = ∅; boolean still_redundant; do { D = R = A = ∅;// clear all lists still_redundant = false; foreach f ∈ F { F = F - {f}; // calls TG-GRASP find a test for f; if undetectable(f) { still_redundant = true; R = R ∪ {f} ; Set line f to undetectable stuck-at value; } elseif aborted(f) A = A ∪ { f } else D = D ∪ { f } } if (still_redundant) F = D ∪ A while (F ≠ ∅) or timeout; C = simplify C by removing redundancies; return C; }
Figure 3: Pseudocode of the RID-GRASP is iterated until there is no redundancy identified from the fault list. If this number is 1, it means there is no logical redundancy and the procedure is almost identical to ATPG. If it is greater than 2, it means that undetectable faults identified in one pass affect the faults targeted in the next pass; removal of a redundancy can unmask another redundancy or make a previously undetectable fault detectable. The procedure in Figure 3 can be expedited by integrating a fault simulator with RID-GRASP. For a given fault list, a random pattern fault simulation is performed until the number of detected faults falls below a certain preset limit. After this, a fault oriented deterministic procedure starts. If the fault chosen from the remaining fault list is proven to be detectable, the test pattern obtained during this procedure is used for a deterministic fault simulation. Faults that are detected with this pattern are appended in detected fault list. “Number of deterministic test patterns” is the number of test patterns generated for those faults that are chosen from the fault list after the random fault simulation phase for deterministic test pattern generation (DTPG): Since “Number of passes” can be greater than 1, the same fault can be targeted multiple times from different passes. The results show that RID-GRASP can generate a 1003
RID-GRASP: Redundancy Identification and Removal Using GRASP
Table 1: Experimental Results Number of Circuit
Number
Gates
Faults
of passes
C432
196
524
2
C499
243
758
C880
443
C1355
Number of deterministic test patterns
Number of
Number of removed
Time
detected faults
Gates
Lines
(sec)
4
514
3
7
2.09
2
8
750
0
8
0.14
942
1
18
942
0
0
0.02
587
1566
2
33
1558
0
8
0.37
C1908
913
1878
2
84
1868
2
8
31.95
C2670
1426
2747
3
280
2245
227
275
63.4
C3540
1719
3428
2
153
3234
79
115
11.45
C5315
2485
5350
3
152
5272
9
69
4.45
C6288
2448
7744
2
0
7692
17
35
9.15
C7552
3719
7550
4
1202
7355
71
124
82.38
percent testable circuit for all ISCAS85 benchmark circuits.
References
5. Conclusion
1.
M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
2.
A.D. Friedman, “Fault Detection in Redundant Circuits,” IEEE Trans. Electronic Computers, vol. EC16, pp. 99-100, Feb. 1967.
3.
M. Harihara and P. R. Menon, “Identification of Undetectable Faults in Combinational Circuits,” in proc. ICCD, pp. 290-293, 1989.
4.
S. Kajihara, H. Shiba and K. Kinoshita, “Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults,” in proc. Int’l Sympo. on FaultTolerant Comput., pp. 263-270, Jul. 1992.
5.
T. Larrabee, “Test Pattern Generation Using Boolean Satisfiability,” IEEE Trans. CAD, vol 11, pp. 4-15, Jan. 1992.
6.
J. P. M. Silva, K. A. Sakallah, “GRASP - A New Search Algorithm for Satisfiability,” Technical Report CSETR-292-96, The University of Michigan, EECS Department, April 1996.
7.
J. P. M. Silva, K. Sakallah, “GRASP - A New Search Algorithm for Satisfiability,” in proc. ICCAD-96, pp. 220-227, Nov. 1996.
8.
J. P. M. Silva, K. Sakallah, “Robust Search Algorithms for Test Pattern Generation,” in proc. Int’l Sympo. on Fault-Tolerant Comput., 1997.
9.
G. Tromp and A. J. Goor, “Logic Synthesis of 100percent Testable Logic Networks,” in proc. ICCD, pp. 428-431, 1991.
Our preliminary results on using the GRASP satisfiability algorithms for identifying and removing redundancies in logic circuits show that it is indeed quite effective in proving unsatisfiability. The GRASP search engine we are currently using contains no circuit structure information but the new version of GRASP will build a clause database with more circuit information and thus help expedite the search process. A preprocessor using structural analysis to remove redundancy will be integrated to form a complete system. The redundancy identification and removal procedure used in RID-GRASP is general and efficient. By setting a value to a variable in CNF formula which corresponds to a redundant element, the circuit under test can be implicitly modified. While the structural fault-independent approach for redundancy identification and removal can yield a substantial speed-up over fault-oriented approach like RIDGRASP, it can’t guarantee to identify and remove all redundancies. The final cost of the circuit is known to be dependent upon the order in which redundancies are removed. Research to explore this relationship to find the optimal ordering is under way.
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