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RSFQ Pseudo Random Generator and Its Possible Applications Anna Yu. Kidiyarova-Shevchenko

Institute of Nuclear Physics, Moscow State University, Vorobiyovy Gory, Moscow, Russia

Dmitry Yu. Zinoviev

Department of Physics, State University of New York, Stony Brook, NY 11794{3800, USA DC/SFQ CLOCK DISTRIBUTION LINE Abstract| We have analyzed theoretically and sim..... ulated a set of 4-bits RSFQ-logic-based Pseudo Random Generators (PRG). These circuits have been fabSR ricated using low-TC Niobium technology. We have also investigated experimentally an XOR cell and a shift register with parallel outputs that have been used XOR as compound parts of the PRGs. Experimentally measured margins for DC power supply voltage for a PRG SFQ/DC DC/SFQ with a serial output, an XOR cell and shift register were 10%, 15%, and 15% respectively. In this paper we discuss various possible applications of a PRG in Fig. 1. Block diagram of a Pseudo Random Generator. SR denotes testing RSFQ circuits and also as a source of \quasi- Shift Register white" digital noise. External Clock

Pseudo Random Output

I. Introduction

In dierent elds of engineering such as noise measurement and computer testings generation of random signals is an important task. There exist many methods of generating random signals using digital equipment [1]. All of them consider a Pseudo Random Generator (PRG) that creates the desired random telegraph signal, as a main part. A PRG has a wide frequency range, and the upper boundary of this range is of a great importance in computer testing and code-decode tasks. It is especially important in testing superconductor digital circuits with extremely high operating frequency, e.g., RSFQ logic/memory cells [2]. During the last ve years the RSFQ logic family has made remarkable progress. It has become obvious that digital circuits based on RSFQ logic elements are the constituent part of modern superconductive electronics. Multiple RSFQ devices have been suggested, analyzed theoretically, and demonstrated experimentally to date [3]. Traditionally, low-speed methods, in which all inputs are fed manually using external RS ip- ops with microsecond periods and delays, have been used to test RSFQ devices [3]. A typical RSFQ unit can operate at very high frequencies (more than 350 GHz) [?], so high-speed testing Manuscript received January 18, 1999. The work was supported in part by Russian State Program on High Temperature Superconductivity, by International Science Foundation (grant #002), by International Soros Fund (grant #MDP000) and BMFT Germany under the project 13N 6329.

Initializing

is necessary to demonstrate the advantages of this family. Unfortunately, external semiconductor sources cannot provide such high-frequency signals, neither can external semiconductor receivers handle such signals. In this paper we suggest an RSFQ PRG which, being built into an RSFQ circuit, can generate testing sequences at the required rate. Also we discuss the possibility of using PRG as a source of \quasi-white" digital noise to calibrate noise detectors and similar devices. II. RSFQ PRG Design and Testing

The simplest RSFQ PRG (Fig. 1) consists of a shift register, a mixing element (typically a two-input XOR gate) and an initializing cell (e.g., a DC/SFQ converter [3]). The inputs of the XOR element are connected to the last and some intermediate (but not arbitrary) cells of the shift register while the output is connected to the rst cell, to form a feedback loop. The number of bits in the register N determines the correct way of connecting XOR element to the register (in particular, the number of the second source cell Z ) and the longest period Tmax of a pseudo random sequence generated by the PRG: Tmax = 2N ? 1. The value of Z may be calculated using the theory of non-reducible primitive binary polynomes (see Table I TABLE I SOME IDEAL COMBINATIONS OF TOTAL NUMBER N OF CELLS IN A SHIFT REGISTER AND THE INDEX Z OF THE INTERMEDIATE CELL USED FOR THE FEEDBACK LOOP. N Z N Z N Z 4 1,3 6 1 9 4 5 2 7 1,3 10 3

Fig. 2. Schematics of shift register with parallel outputs (the rst and the last stages are shown); nominal circuit parameters are: Ja1 = Jb1 = 2:0, Ja2 = Jb2 = 2:25, Ja3 = Jb3 = 1:75, Ja4 = Jb4 = 2:25, Ja5 = Jb5 = 2:0, Ja6 = 1:5, Ia1 = Ib1 = 1:54, Ia2 = Ib2 = 2:0, Ia3 = 1:6, Ia4 = 3:0, Lin = 0:6, Lout = 1:5, La1 = Lb1 = 1:1, La2 = Lb2 = 3:0, La3 = Lb3 = 0:3, La4 = Lb4 = 1:0, La5 = Lb5 = 1:8, La6 = Lb6 = 0:22, La7 = La8 = 1:5. Here and below currents are normalized to 0:125 mA, inductances - to 2:63 pH .

Fig. 3. Schematics of XOR cell; nominal circuit parameters are: J1 = J4 = 1:75, J2 = 1:0, J3 = 2:75, J5 = 1:5, J6 = 2:25, I1 = 1:9, Lin = 1:5, L1 = 3:0, Lout = 1:3.

for several examples). In our particular implementation N = 4 and M = 3 that yields the following sequence of length L = 24 ? 1 = 15: 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1. Note that a PRG may be either serial or parallel. A serial PRG has only one output taken from the last cell of the shift register whereas a parallel PRG may have up to N outputs taken from any combination of the shift register cells (actually, the size of this combination is limited to some M < N to reduce extra correlation between neighboring bits). Delay time of a PRG is determined by delays ta (in the shift register) and tb (in the feedback loop with XOR). So the total clock period of PRG T = ta + tb strongly increases with the number of stages. To generate a non-trivial pulse sequence, a PRG must be initialized, i.e., at least one bit of the shift register must be set to 11. The initial state of the shift register does not aect the maximum period of the generated sequence and its spectrum. Fig. 2,3 show detailed schematics of one stage of a shift register used in PRG, and an original XOR cell used as a mixer. This shift register is a slightly modi ed version of the last reported one [4], and XOR is based on a T ip1 Another approach is to use an inverted XOR cell as a mixing element.

Fig. 4. Low-speed operation of a 4-bit Pseudo Random Generator; the input signal is generated by a current source; the output is being read out by a T ip- op sensor

op cell. The peculiarity of this version of XOR gate is that input signals are merged and then counted modulo 2. Simulated with the help of PSCAN program [5] operating margins for the register's and XOR's supply voltage are 25% and 27% respectively. A 4-bit PRG has been fabricated in the Institut of Radioelectronics and Automatics of the Russian Academy of Science (IRE RAS) using low-TC Niobium technology. The PRG has 4 parallel outputs but in this particular experiment an SFQ/DC converter with the magnitude of an output digital pseudo random signal of about 0.1 mV is connected only to the last of them. A DC/SFQ converter has been used as an initializing element. The experiment has been conducted in low-frequency mode, and a saw-tooth-like signal has been applied to imitate a highfrequency clock (Fig. 4). Before testing the PRGs, we investigated experimentally (also at low frequencies) an XOR cell and a shift register with parallel outputs that had been used as componets of the PRG. Experimentally measured margins for DC power supply voltage for these PRG, XOR cell and shift register were 10%, 15%, 15% respectively. III. Applications

There are many methods of high-speed RSFQ device testing. The most direct way is to store required test sequences (produced by some external devices) into shift registers (separate for each input of a tested unit) and then send the contents of these registers to the circuit under test (CUT) at high clock frequency. Unfortunately, when using this method, the complexity of the equipment grows fast as we increase the number of inputs of the CUT. A PRG can successfully substitute these external test sequences' generators because it works simultaneously as a pulse generator and a shift register (storage). Moreover, its complexity depends linearly on the number of inputs of the tested circuit. A parallel PRG with L + M + 1 outputs is able to perform an exhaustive digital test of an RSFQ device with M inputs and L internal states. The

DC/SFQ

PRG

ClockController

1

Spectral Density 1/Tclock

External Clock

..... CUT ..... 0.5

Signature Generator

DC/SFQ

..... SFQ/DC

Output Data Register

Fast Clock Generator

0 1/Tmax

Fig. 5. Block diagram of an RSFQ implementation of BILBO testing concept

time for this test is Tmax . One of the most frequently application of PRG in testing is a so-called BILBO (Built-In Logic Block Observer) scheme. We propose an RSFQ analog of this scheme (Fig. 5). Here the testing sequence from PRG gets to the CUT in Tmax, the results of the test are written to the special shift register where they are mixed, and the resulting signature is written to an output shift register. External semiconductor devices read these data at low clock frequency. A clock controller is needed in order to provide a correct sequence of clock pulses. At the beginning of each period, the clock controller must send N low-speed clock pulses. During this time the output information can be read out, and all initialization processes can be completed. Then the clock controller sends 2N ? 1 fast clock pulses, exhaustive test sequences reach the CUT, signature is constructed and stored in the output register. When using a PRG as a source of \quasi-white" noise, it is extremely important that its spectral density be precisely calculated. In this case, a signal from a PRG passes through a device to be calibrated, and the spectral density of the output is compared with the calculated pattern. In this case the spectral density of a serial PRG has linear structure and consists of two sets of lines: with amplitude A and period 1=Tclock and with amplitude A1 = A=2 and period 1=Tmax, where Tclock is the period of clock pulses. The shape of the spectral density envelope depends on the shape of an SFQ pulse and looks like function sinc(x) with the period =T  500 GHz (T is the characteristic width of an SFQ pulse) (Fig. 6), but fortunately, it is not necessary to know the shape of SFQ pulses exactly. Taking into consideration the fact that with RSFQ techniques and long enough shift register (on which a PRG is based) T  Tclock  Tmax, we see that at least at radio frequencies the signal produced by the PRG may be considered as a \quasi-white" digital noise. In the case of smaller N , the output signal during one period Tmax may be calculated exactly from the equation:

t ? k
T  clock ; '(t) = ak
f T k=0 TX max

(1)

π/δΤ

ω

Fig. 6. Typical shape of an RSFQ PRG output spectral density

where f (t) if the shape of the pulse and ak are coecients that determine the pseudo random nature of the signal. These coecients can be obtained from the equation:

X (k
Tclock ) = H^
X ((k ? 1)
Tclock ) : (2) Here X (t) is a vector of PRG's output states in the moment t, and H^ is the translating matrix of the PRG. IV. Conclusion

The paper describes the rst implementation of an RSFQ Pseudo Random Generator that can run at a frequency of more than 50 GHz and can be used in high-frequency testing or as a \quasi-white" digital noise source. Acknowledgment

The authors would like to thank T. Filippov for useful discussions. References [1] H. Suttcli and K. F. Knott, \Standard LF noise sources using digital techniques and their application to the measurement of noise spectra," Radio and Electronic Engineer, vol. 40, pp. 132{ 135, Sept. 1970. [2] K. Likharev and V. Semenov, \RSFQ logic/memory family: a new Josephson junction technology for sub-teraherz clock frequency digital systems," IEEE Trans. on Appl. Supercond., vol. 1, pp. 3{28, Mar. 1991. [3] S. Polonsky, V. Semenov, and D. Schneider, \Transmission of single- ux-quantum pulses along superconducting microstrip lines," Applied Superconductivity, vol. 3, pp. 2598{2600, Mar. 1993. [4] O. Mukhanov, \Rapid single ux quantum (RSFQ) shift register family," Applied Superconductivity, vol. 3, pp. 2578{2581, Mar. 1993. [5] S. Polonsky, V. Semenov, and P. Shevchenko, \PSCAN: Personal superconductor circuit analyzer," Supercond. Sci. Technol., vol. 4, pp. 667{670, 1991.