Progress in Directed Self-Assembly Hole Shrink Applications Todd R. Younkina,b,*, Roel Gronheidb,*, Paulina Rincon Delgadillob,c, Boon Teik Chanb, Nadia Vandenbroeckb, Steven Demuynckb, Ainhoa Romo-Negreirab,d, Doni Parnellb,d, Kathleen Nafusb,d, Shigeru Taharab,e, Mark Somervellf a
Intel Corporation, 2501 NW 229th Avenue, Hillsboro, OR 97124 USA b IMEC, Kapeldreef 75, B-3001 Leuven, Belgium c Institute for Molecular Engineering, University of Chicago, 5747 South Ellis Avenue, Jones 222, Chicago, IL 60637 d Tokyo Electron Europe, Kerkenbos 1015, Unit C, 6546 BB, Nijmegen, The Netherlands e Tokyo Electron Miyagi Limited, 1 Techno-Hills, Taiwa-cho, Kurokawa-gun, Miyagi 981-3629 f Tokyo Electron America, 2400 Grove Blvd., Austin, TX 78741 USA ABSTRACT Directed Self-Assembly (DSA) has become a promising alternative for generating fine lithographic patterns. Since contact holes are among the most difficult structures to resolve through traditional lithographic means, directed selfassembly applications that generate smaller contact holes are of particular interest to the industry. In this paper, DSA integrations that shrink pre-patterned contact holes were explored. The use of both block copolymers (BCPs) 1 and blended polymer systems2 was considered. In addition, both wet3 and dry4 techniques were used to develop the central core out of the respective phase-separated morphologies. Finally, the hole patterns created through the various contact hole applications were transferred to substrates of interest with the goal of incorporating them into an IMEC 28 nm node via chain electrical test vehicle for direct, side-by-side comparison. Keywords: Directed Self-Assembly, DSA, contact hole, blend, block copolymer, BCP, PS-b-PMMA, shrink, rectification, electrical testing, etch, wet development.
1. INTRODUCTION Both IMEC5 and TEL6 have made a multi-year commitment to Directed Self-Assembly (or DSA) such that they can – [1] establish standard methods for the use of DSA as a complementary patterning technique to both 193i and EUVL, [2] develop a robust baseline process that the industry can use in order to collaborate, characterize, optimize, and understand the fundamentals of DSA (critical gains are needed in material control, pattern layout/decomposition, pattern transfer, pattern placement, and defectivity), [3] provide feedback from integration efforts to material solution providers in order to refine and mature the chemical supply chain, and [4] ensure that any DSA-specific hardware is identified and understood with sufficient lead time to intercept our industry’s manufacturing needs. As part of that plan, IMEC’s materials competence center (CCM) has been tasked with establishing the foundation for this long term effort. We have already disclosed some of the progress that has been made for both grapho- and chemiepitaxial L/S multiplication schemes at IMEC, with the L/S multiplication flow that originated in the Nealey group at the Univ. of Wisconsin now serving as our standard 300 mm DSA process of record.7-8 While that work is maturing at a healthy pace and is providing insight on patterning and pattern transfer requirements, material selection and stability, and the nature of DSA-related defects9-10 – our industry needs solutions to the C/H layer challenges that are heading towards us at an ever-alarming rate. These include the need to make < 25 nm holes at < 50 nm pitch with both improved uniformity and pattern placement error.11 While it won’t be an easy task, we believe that DSA can provide a solution to these challenges, and as illustrated in Figure 1, we’ve set out to expand our in-house DSA capabilities such that we can get high-quality insight on how to use DSA in real-world C/H applications.
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Success Criteria
Step 1 Quick-Turn Test
Step 2 Screening & Optimization
Step 3 Layer Qualification/Use
Traditional Lithography
Line/ Space DSA
Contact/ Hole DSA
Figure 1. IMEC is building a library of DSA solutions for both grapho- and chemi-epitaxial L/S & C/H applications. In STEP 1, we quickly characterize materials via fingerprint patterns in order to cross-correlate performance to material design as well as to define processing and pattern transfer requirements. In STEP 2, we focus on the integrated requirements to achieve the desired order – raising questions such as :: What is the integrated sensitivity to film thickness, anneal time, pattern transfer, or the type of wafer stack employed? Is there a trade-off between process margin and DSA-induced defectivity? Are we able to reliably measure such (small) features? Can we utilize these features downstream or will metal fill and increased resistance for small features pose an insurmountable challenge? Finally, while not the focus of this manuscript, STEP 3 is where we will utilize these schemes to tackle some of the many challenges for critical layers at the < 14 nm node. Continued progress will require a stronger commitment from the simulation/OPC community in order to understand how design decomposition can reliably yield our target features.
We do have some concerns about using DSA for C/H applications. These include - [1] the vertical integrity of DSAgenerated morphologies, [2] the pattern transfer of DSA-based process flows that utilize materials which have similar etch selectivity (such as PS and PMMA), [3] the defect density of both defects that are fundamental to DSA as well as those that are related to the integration scheme we choose to use, [4] pattern placement error, and [5] the design rule restrictions imposed by our DSA process flow. We believed that several of these questions could be investigated by the use of a more complete wafer flow that relied upon an integrated metric as our final success criteria. In addition, since we are using IMEC’s defect metrology tools (such as the KLA2835) on the Nealey L/S flow to characterize and understand the nature of DSA-induced defects, we wanted to take a different/orthogonal approach to evaluate ‘DSA defect density’. As such, we set out to leverage IMEC’s existing 28 nm node integration flow to develop an electrical test vehicle that could ‘easily’ incorporate DSA into a single C/H layer.
2. IMEC ELECTRICAL TEST VEHICLE FOR DSA - EV28-VA0 LAYER IMEC’s mainstream integrated test vehicle is currently derived from the ‘EVEREST’ mask set. This is a 28 nm node planar flow that relies on the use of two local interconnect (or LI) layers to achieve sufficient device density yet rely solely on 193i patterning. For the remainder of this paper, we will refer to this as EV28-(LAYER). As illustrated in figure 2, we determined that the fabrication of a 3-layer short loop test vehicle composed of two metal layers (LI2 & MT1) sandwiching a via layer (VA0) built with our DSA process flow(s) - would allow us to probe a series of Kelvin and via chain electrical test structures through the 4-contact points illustrated in figures 2(a) and 2(b) respectively. The key post-lithography patterning targets for our EV28-VA0 DSA layer that complement this goal are outlined in figures 3(a) – 3(c). These features serve as the resolution requirement for our blend and BCP guide resists.
Kelvin
(a) LI2 V0 M1 LI2 V0 M1
Chain
Dummy M1
(b) Dummy M1
(c) Figure 2. The electrical features available on IMEC’s 28 nm node ‘EV28 LI2-VA0-MT1’ short loop test vehicle. (a) The VA0-Kelvin structures come in a wide assortment of CD/pitch combinations. (b) The VA0-chains come in 10, 100, and 10k chain versions – allowing us to probe, understand, and optimize the integrated “missing C/H” or error rate for flows that incorporate DSA. The dotted black square illustrated in figures 2(a) and 2(b) represents the key repeat unit that makes up our primary DSA target – a staggered 55P90-110 contact (XSEM) array - as shown in figure 3(a).
EV28-VA0 Pattern
Primary Target
Secondary Target
Tertiary Target
Post-Lithography Target
(a) Staggered 55P90-110
(b) Dense 55P110
(c) Isolated
Figure 3. The EV28-VA0 lithography features that we will use to optimize our DSA process flows. The images illustrated above are actually from our polymer blend guide resist 1, which is a well-balanced patterning media. After employing our DSA shrink, we anticipated that our primary target – the staggered C/H array shown in figure 3(a) – would have a CD of < 30 nm in our polymer blend flow and a CD < 22 nm in our BCP flow.
To better understand how the degrees of freedom available at the molecular level impacts our DSA result and integrated performance, we wanted to compare two different systems which have recently been made available by IMEC’s material solution providers – a blended polymer system and a PS-b-PMMA BCP system. The material attributes are listed in Table 1. The polymer blend is an A/B system that is physically mixed (like oil and vinegar) and, as such, has no intrinsic order; just the drive to phase separate on the microscopic length scale. This material acts as a fairly flexible/weakly rectifying agent, largely following the order introduced via our lithographic pre-pattern. Our BCP is also an A/B system made of dissimilar blocks. Unlike the blend, however, the A and B blocks of the BCP are covalently attached such that they can only rearrange on the nanometer length scale with an intrinsic order introduced by the chemist during the synthesis of the BCP. While this agent is a bit more stubborn, it will be shown later in the paper that we can generate very small CDs and this approach can be highly rectifying! So….what are the minimum dimensions we can get to with the weakly rectifying blend agent? Will the strongly rectifying BCP agent give us a working process window (i.e. some CD and pitch latitude)? What are the tradeoffs (and can we live with them?)? With the aforementioned goals in mind, we defined the flow for our electrical test wafers. First, we wanted to use standard IMEC processing for the EV28-LI2 and -MT1 layers. Second, we believed the easiest approach to use for our EV28-VA0 DSA layer would be to make use of a negative tone resist template (as first described by Cheng and coworkers12). Because of their enhanced aerial image, negative tone resists are known to be better for printing holes. Also, because a negative tone resist is insoluble in most organic solvents, our polymer blend and PS-b-PMMA BCP can
Polymer Blend2
Block Copolymer (BCP)1
Reference Name Used Herein Polymer Composition
Blend-A / Guide Resist 1 Polar/Non-Polar Polymer Blend
Without Guidance from Lithography
No Specific Dimension, Morphology, or Periodicity
BCPs A-C / Guide Resist A-D PS-PMMA Block Copolymer Intrinsic Dimension and Pre-determined Morphology with L0 ranging from 33 nm – 52 nm.
EV28-VA0 Integration Cartoon (Orange = Guide Resist) Anneal Temperature Neutral Layer Current Core Removal Option(s) C/H Shrink
120-150C Not needed Organic Solvent Polar polymer adheres to the guide pattern and the less polar polymer is removed via wet etch.
Concern
Aggressive undercut or footing if the substrate, guide resist, and polar component are not well balanced; Etch selectivities.
Design Rule Restrictions/Flexibility Minimum CD Achieved to Date
Flexible/Weak Rectification > 20 nm
200-250C (To date) Needed on top of SiOC HM Wet or Dry Etch Techniques PS or PMMA wets the guide pattern, resulting in a PS outer plug and PMMA core. The PMMA inner core is removed by wet or dry etch. The 3D nature of the PMMA inner core does not reach the substrate – disrupting the pattern/pattern transfer and increasing the missing C/H rate; Etch selectivities. Less Flexible/Strong Rectification < 20 nm
Table 1. The two DSA integration options explored in this paper – the use of either a polymer blend or a PS-b-PMMA BCP - on a guide resist prepattern. Each process is observed to have pros and cons with the polymer blend having the more advantageous annealing temperature and improved flexibility whereas the BCP flow yields smaller CDs and a significant uniformity improvement. The images in this table were borrowed from K. Maruyama, et al. Int. Symposium on EUVL. Oct.1-2012 with consent from the author.13
Figure 4. In our initial DSA C/H shrink process flow, we have put most of our effort on the new DSA steps (Steps 2 and 2a). We are also using the wafers that are generated at step 6 to look for alternate metallization schemes (in step 7) that improve performance in the
