Scan-Chain Partition for High Test-Data ... - Semantic Scholar

716

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009

Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint Sying-Jyan Wang, Member, IEEE, Katherine Shu-Min Li, Member, IEEE, Shih-Cheng Chen, Huai-Yan Shiu, and Yun-Lung Chu

Abstract—The degree of achievable test-data compression depends on not only the compression scheme but also the structure of the applied test data. Therefore, it is possible to improve the compression rate of a given test set by carefully organizing the way that test data are present in the scan structure. The relationship between signal probability and test-data entropy is explored in this paper, and the results show that the theoretical maximum compression can be increased through a partition of scan flip-flops such that the test data present in each partition have a skewed signal distribution. In essence, this approach simply puts similar scan flip-flops in an adjacent part of a scan chain, which also helps to reduce shift power in the scan test process. Furthermore, it is shown that the intrapartition scan-chain order has little impact on the compressibility of a test set; thus, it is easy to achieve higher test compression with low routing overhead. Experimental results show that the proposed partition method can raise the compression rates of various compression schemes by more than 17%, and the average reduction in shift power is about 50%. In contrast, the increase in routing length is limited. Index Terms—Entropy theory, routing, scan-based design, test power, test-data compression.

I. I NTRODUCTION

T

HE LARGE amount of test data in modern very large scale integration (VLSI) circuits become a great challenge, as they require not only large automatic-test-equipment (ATE) memory but also significant test application time [1]. In order to minimize test cost, compression techniques can be used to reduce test-data volume. Existing test-data compression methods can be classified into three types [2]: code-based [3]–[19],

Manuscript received September 19, 2008; revised December 10, 2008. Current version published April 22, 2009. This work was supported in part by the National Science Council of Taiwan under Grants NSC-95-2221-E-005153-MY2 and NSC-96-2221-E-110-090-MY2 and in part by the Ministry of Economic Affairs of Taiwan under Grant 97-EC-17-A-01-S1-104. This paper was recommended by Associate Editor N. K. Jha. S.-J. Wang and Y.-L. Chu are with the Department of Computer Science and Engineering, National Chung Hsing University, Taichung 402, Taiwan (e-mail: [email protected]; [email protected]). K. S.-M. Li is with the Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (e-mail: smli@cse. nsysu.edu.tw). S.-C. Chen is with Global Unichip Corporation, Hsinchu 300, Taiwan (e-mail: [email protected]). H.-Y. Shiu is with the Chinese Army, Taiwan (e-mail: s9456044@cs. nchu.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCAD.2009.2015741

linear-decompression-based [20]–[22], and broadcast-based [23]–[25] schemes. Code-based techniques achieve test compression by encoding test cubes with data compression codes. In these schemes, the original data are partitioned into symbols, and each symbol is replaced by a codeword. Since a codeword is usually smaller than the original symbol, smaller memory space and less ATE channel bandwidth is consumed by the compressed test data. Encoding schemes are usually classified according to how test and encoded data are handled [2]. If the lengths of both symbols and encoded codewords are fixed, this scheme is classified as a “fixed-to-fixed” encoding technique [3], [4]. If a scheme encodes fixed-length symbols into variable-length codewords, it belongs to the “fixed-to-variable” category [5]–[8]. Similarly, a “variable-to-fixed” scheme [9] encodes symbols of variable lengths into codewords of a specified number of bits, while in “variable-to-variable” schemes [10]–[14], the lengths of both symbols and codewords are variable. Some schemes can encode symbols with both fixed and variable lengths [15], [16], while others apply multilevel techniques to achieve even better compression rates [17]–[19]. The effectiveness of a code-based compression scheme depends on the encoding efficiency as well as the structure of test data. It is usually difficult to compress random data, as all symbols appear with roughly equal probability, and thus, no encoding method can achieve significant reduction in the amount of compressed data. Hence, one possible way to improve the test compression rate is to find a set of test data that is easier to compress. Entropy is associated with the amount of disorder in a system. In information theory, the Shannon entropy [26] is a measure of the amount of information contained in a set of data; thus, it represents an absolute limit on the best possible lossless compression of any communication. The idea of using entropy to calculate the test-data compression limits was first applied to frequency-directed run-length (FDR) codes with don’t cares assigned to zeroes [27]. The concept was then extended to incompletely specified test data [28]. In these studies, it is shown that the maximum amount of compression of a test-data set is directly related to the entropy. The entropy in a test-data set is affected by how test data are treated in an encoding scheme. For example, it is shown that different ways of partitioning test data into symbols will affect the entropy [28]. The proper use of don’t cares is helpful to achieve lower entropy. In this paper, we explore the feasibility

0278-0070/$25.00 © 2009 IEEE

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

WANG et al.: SCAN-CHAIN PARTITION FOR HIGH TEST-DATA COMPRESSIBILITY AND LOW SHIFT POWER

of reducing entropy in a test set from a different perspective. In a scan-based test, a symbol is the bit patterns appearing in a set of consecutive scan flip-flops (also known as scan cells). Thus, by altering the order of scan cells in the scan chain, the symbols to be encoded are changed and so is the entropy of the test-data set. If it is possible to put similar scan cells (in terms of test data appearing in them) close to each other in the scan chain, one can effectively reduce the entropy in a test set. As a result, a higher compression can be achieved for the same test set. Conceptually, this can be analogous to the fact that multiple crystal structures of the same material exhibit very different physical properties. Furthermore, since adjacent scan cells contain similar data, the shift power, which is caused by bit transitions between adjacent scan cells, will also be reduced. Another way to look at the test power problem is that, since the entropy represents the disorder in the system, a low-entropy test set means fewer random bit transitions in symbols and, thus, lower shift power. The scan-chain ordering has been applied to various problems, including shift power reduction [29], [30] and the enhancement of delay fault coverage (FC) in launch-off-shift delay tests [31]. However, scan-chain reorder may adversely affect scan-chain routing by creating very long routing paths, and in some cases, the reorder algorithm can be rather involved. In this paper, the scan-chain ordering is achieved by a simple partition of all scan cells. It is shown that intrapartition orders have modest impact on the entropy, and thus, the scan cells can be ordered to minimize routing length. Experimental results show that the proposed method can effectively improve the compression results of all encoding techniques with very small routing-length penalty. The proposed partition scheme is based on a given test-data set; therefore, a change of test set may be problematic when the design is finished. Experimental results suggest that a partition derived from a given test set is also helpful in reducing test data in a different test set for the same circuit, which implies that the proposed method is less affected by the change of test set. The remaining part of this paper is organized as follows. The next section gives a brief survey of existing compression techniques and introduces how to calculate entropy in such methods. In Section III, an analysis on the entropy of a test-data set with respect to the probability distribution of bits is given. According to the entropy analysis, a scan-cell partition scheme that effectively reduces the entropy of a testdata set is proposed in Section IV. In order to restrict the overall scan-chain length, a partition scheme targeted for low routing overhead is further explored. The revised partition algorithm can improve the compression rates in various compression schemes with low routing-length overhead. Experimental results are presented in Section V and VI concludes this paper. II. P RELIMINARIES This section provides an overview of the classification of compression schemes and introduces the entropy in these schemes [27], [28].

717

A. Fixed-Symbol-Length Codes For encoding schemes that fall in the fixed-to-fixed and fixed-to-variable categories, the test data are partitioned into fixed-length symbols, which are replaced by the corresponding codewords. An example of a fixed-to-fixed scheme is the dictionary coding [3], [4]. In this scheme, the original test cubes are partitioned into fixed n-bit symbols, which are encoded by b-bit codewords. The decoding process is carried out by looking up a dictionary, which is essentially a table. Each codeword is a table index, and the corresponding symbol is the table entry. For an n-bit symbol block, in all, there are 2n possible symbols. Assume that there are only S distinct symbols appearing in all test cubes. One can encode the symbols with b-bit codewords if 2b > S is true. If the overhead due to the dictionary is ignored, the compression ratio is roughly n/b. The best example of fixed-to-variable coding is the Huffman codes [5]–[8]. Huffman codes are statistical coding schemes, in which codewords are assigned according to each symbol’s frequency of occurrence. The more frequent a symbol occurs, the fewer bits are assigned to its codeword. As a result, the average length of a codeword is minimized. A Huffman code is obtained by constructing a Huffman tree, in which a path from the root to a leaf gives the codeword for the symbol corresponding to the leaf. The full Huffman coding achieves good compression but requires significant hardware overhead for the decompressor. To alleviate this problem, some modified Huffman encoding schemes have been proposed [6]–[8]. For the fixed-symbol-length schemes, the entropy is defined as follows [28]. Definition 1: Assume that S is the set of all distinct symbols in a test set, and Z is a random variable. Let Pr(Z = zi ) be the probability of occurrence of symbol zi in the test set. The entropy of the test set is  H=− Pr(Z = zi ) · log Pr(Z = zi ). zi ∈S

The entropy is the lower bound on the average number of bits required for each codeword. Thus, the maximum achievable compression is defined as follows. Definition 2: The maximum achievable compression in a fixed-symbol-length scheme is [28] Max_compression_rate =

symbol_length − entropy . symbol_length

B. Variable-Symbol-Length Codes Variable-symbol-length schemes are based on run-length codes. A run is a sequence of consecutive 0s or 1s, which is the symbol to be encoded. Therefore, the symbol length is variable. The codeword corresponding to a symbol is the length of the run. The simplest way for run-length coding is to use fixedlength codewords [9], and thus, it is a variable-to-fixed scheme. However, better compression ratio is usually achieved by using variable-length codewords. Examples of variable-length codes include Golomb code [10], [11], FDR code [12], and variableinput-length Huffman codes [13], [14]. In some schemes, only

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

718

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009

Fig. 1. Entropy versus p0 in fixed-length schemes.

Fig. 2.

runs of 0s are encoded to simplify the decoder design, while in others, both runs of 0s and 1s are encoded. The entropy of a variable-length code is calculated in the same way as fixed-length codes; the only difference is that the symbols are now variable-length runs. However, the maximum achievable compression is different. Definition 3: The maximum achievable compression in a variable-symbol-length scheme is [28]

According to the aforementioned discussion, the best way to derive an easy-to-compress test-data set with don’t cares is to assign X’s to the bit (0 or 1) that occurs more frequently in the test set.

Max_compression_rate =

avg_symbol_length − entropy . avg_symbol_length

III. A NALYSIS ON E NTROPY AND M AXIMUM C OMPRESSION In this section, an analytical model for entropy and maximum compression versus the distribution of 0s and 1s in a test set is given. For simplicity, it is assumed that the size of the test-data set is infinity, and the probabilities of 0, 1, and X (i.e., don’t cares) in the set are p0 , p1 , and pX , respectively. A. Fixed-Symbol-Length Codes First, we assume that the test-data set is fully specified; in other words, it is assumed that pX = 0 and p0 + p1 = 1. Let the symbol length be n, and the probability of occurrence of a symbol consisting of i 0s is equal to pi0 pn−i 1 . According to Definition 1, the entropy is n      H(p0 ) = − Cin · pi0 (1−p0 )n−i · log pi0 (1−p0 )n−i

(1)

i=0

where Cin is the number of combinations of i 0s in an n-bit symbol. The entropy versus p0 is shown in Fig. 1 for n = 2, 4, 6, 8, and 10. As expected, the maximum entropy equals n with p0 = 1/2, and the entropy function is symmetric with respect to p0 = 1/2. In other words, the maximum entropy occurs when the symbols are truly random. The maximum compression is (n − H(p0 ))/n, according to Definition 2. Thus, the achievable compression rate will be higher if the difference between p0 and p1 becomes larger. The maximum compression is shown in Fig. 2 for n = 10. The plots of maximum compression for other symbol lengths are hardly distinguishable from the one in Fig. 2 and, thus, are not shown here.

Maximum compression of fixed-length schemes (n = 10).

B. Variable-Symbol-Length Codes In order to derive the maximum compression of run-length codes, we need to calculate both the average run lengths and the entropy (Definition 3). In test cubes consisting of 0, 1, and X, the X bits are assigned in such a way to maximize the run length. To achieve this goal, a simple yet effective approach is to assign X to the same value of its preceding bit. The expected value of run length can be calculated as follows. First, consider the case where runs of both 0s and 1s are encoded. Assume that the length of a run of 0s is l. In such a run, the first bit must be 0. Assume that the run starts at position p in a cube; the next l − 1 bits should be either 0 or X. Since this run terminates at the p + l − 1, the bit at position p + l must be 1. Let random variable RL0 be the length of the run of 0s. Therefore, the probability that RL0 = l is Pr(RL0 = l) = (p0 + pX )l−1 × p1 .

(2)

It is easy to verify that Pr(RL0 = l) is a probability distribution function. Similarly, we have Pr(RL1 = l) = (p1 + pX )l−1 × p0 .

(3)

Theorem 1: The expected length of a run of 0s is 1/p1 , and the expected length of a run of 1s is 1/p0 . Proof: The expected length of a run of 0s is ∞  l × (p0 + pX )l−1 × p1 . (4) E[RL0 ] = l=1

Let y = (p0 + pX ), and denote the expected run length as L0 . Rewrite (4), with i + 1 = l L0 = p1 ×

∞ 

l × y l−1

l=1

= p1 ×

∞ 

(i + 1) × y i

i=0

= p1 ×

∞ 

i × y i + p1 ×

i=0

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

∞  i=0

yi .

(5)

WANG et al.: SCAN-CHAIN PARTITION FOR HIGH TEST-DATA COMPRESSIBILITY AND LOW SHIFT POWER

719

By changing the index in (5), the equation becomes L0 = p1 ×

∞  l=0

= p1 × y ×

l × y l + p1 ×

∞ 

yi

i=0 ∞ 

l × y l−1 + p1 ×

∞ 

yi .

(6)

p1 . 1−y

(7)

i=0

l=0

Therefore L0 = y × L0 + p1 ×

∞ 

y i = y × L0 +

i=0

Rearrange (7), and given that 1 − y = p1 Fig. 3. Entropy versus p1 in variable-length schemes.

(1 − y) × L0 = 1.

(8)

As a result, L0 = 1/p1 . The expected length of a run of 1s can be calculated in the same way.  In many run-length codes, only runs of 0s are encoded. In this case, the X bits are assigned to 0s. Corollary 1: The expected run length L0 = 1/p1 in case X bits are assigned to 0s. The proof of Corollary 1 is the same as the L0 part of Theorem 1, except that pX is 0 as all X bits become 0. This result can be explained as follows. Since a run of 0s is interrupted by a 1, the expected run length of 0s is decided by the occurrence frequency of 1s. Thus, in both cases, the expected run lengths of 0s are the same. Similarly, the expected run length L1 = 1/p0 in case X bits are assigned to 1s. The next step is to calculate the entropy associated with a run-length code. For simplicity, we only consider the case where X bits are assigned to 0s. According to Definition 1 and (2), the entropy of run-length codes is H= − =−

∞  l=1 ∞ 

Pr(RL0 = l) · log Pr(RL0 = l)   (p0 + pX )l−1 p1 · log (p0 + pX )l−1 p1

l=1

=−

∞ 

(p0 + pX )l−1 p1 · [(l − 1)·log(p0 + pX ) + log p1 ] .

l=1

(9) As before, let y = (p0 + pX ), and (9) becomes H=−

∞ 

y l−1 p1 · [(l − 1) · log y + log p1 ]

l=1

= − p1 · log y

∞ 

l · y l−1 + p1 · (log y − log p1 )

l=1

∞ 

y l−1 .

l=1

(10) Note that the left summation in (10) is similar to the calculation for average run lengths [see (5)] and the right summation in (10) is a power series with y < 1. Therefore log y H = (log y − log p1 ) − . p1

(11)

Fig. 4. Maximum compression of variable-length schemes.

The entropy H in this scheme (i.e., all X bits are assigned to 0) versus probability p1 is shown in Fig. 3. In Fig. 3, the entropy is shown only for p1 ≥ 0.05, as (11) indicates that the entropy of run-length codes becomes infinity as p1 approaches 0, and it becomes 0 when p1 = 1. However, what really matters is the maximum compression, which is given in Definition 3 for run-length codes. The average symbol length (run length) is 1/p1 as shown in Corollary 1. The plot of the maximum compression for variable-length schemes is shown in Fig. 4. The compression is plotted with respect to p1 since X bits are assigned to 0s. As in the fixed-symbol-length schemes, no compression is possible for random data (i.e., 0s and 1s appear with the same frequency), and the compression rate will be higher if the difference between p0 and p1 increases. In summary, for all compression schemes, the minimum compression occurs at p0 = p1 = 1/2, which represents true random data. The compression rate is maximized at either p0 = 1 or p1 = 1; unfortunately, in this case, the symbols hardly contain any useful information. To increase the compression rate, one possible solution is to assign 0 to all X bits in a test set, and in this way, the frequencies of occurrence of 0s and 1s are skewed. In the next section, we will explore another way to improve achievable compression. IV. S KEW -D ISTRIBUTION S CAN -C HAIN P ARTITIONING From the discussion in Section III, the compression efficiency of any given code is decided by the distribution of 0s

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

720

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009

Fig. 6.

Modified scan chain.

Fig. 7.

Graph representation of two-bit symbol blocks and clique partition.

Fig. 5. Partition example.

and 1s in the test vectors. If we can divide a scan chain into parts so that the distribution of 0s and 1s can be optimized according the applied code, improved compression rate can be achieved. A. Scan-Chain Partition The distribution of 0s and 1s may vary widely from one scan cell to another, and we can exploit the variance to partition scan chains. The basic idea is explained by the example in Fig. 5, in which a test set of six vectors is applied to a scan chain consisting of eight scan cells. For scan cells 1, 2, and 8, there are more 0s than 1s in the test set, and thus, they are assigned to the 0-dominant part. On the other hand, in scan cells {3, 4, 5}, 1s outnumber 0s, and they are put into the 1-dominant part. In scan cells 6 and 7, the number of 0s and 1s are equal, and they are assigned randomly to equalize the lengths of chains, as shown in Fig. 5(b). The 0- and 1-dominant parts are referred to as chain-0 and chain-1 henceforth for simplicity. As a result, even though the number of 0s and 1s are roughly the same in the test set in Fig. 5, we have p0 = 2p1 in chain-0 and p1 = 2p0 in chain-1. The proposed scan-chain partition creates two chains in which the probabilities of p1 and p0 are skewed. The reason that this method can improve compression efficiency follows the results presented in Section III, where it is shown that maximum compression in all schemes will be higher if the frequencies of the occurrences of 0s and 1s become uneven. 1) Variable-Symbol-Length Codes: Consider the run-length codes. Let p0 and p1 be the probability of 0 and 1 in a given test set. If the scan chain is partitioned according to the procedure described in this section, the probabilities will be changed in both chains. Let p0,0 and p0,1 be the probabilities of 0 and 1 in chain-0, respectively. The probabilities p1,0 and p1,1 are defined similarly. Obviously, p0,1 < p1 , and p1,0 < p0 . Since all X’s in chain-0 will be filled by 0 and those in chain-1 are assigned to 1, runs in chain-0 are mostly 0s while runs in chain-1 are mostly 1s. As a result, the expected run lengths in either chain are longer than those in the initial chain. Thus, the efficiency of run-length code-based compression methods can be greatly improved.

A drawback of the aforementioned coding scheme is that runs of both 0s and 1s have to be encoded, which somewhat complicates the decoder design. The problem can be easily solved by including a bit inversion between chain-0 and chain-1, as shown in Fig. 6. This can be done by inserting an inverter between chain-0 and chain-1, or one can simply connect the Q output of the last scan cell in chain-0 to chain-1. In this example, vectors t1 , t2 , and t3 of the test set in Fig. 5(b) are to be applied. First, the X bits in the vectors are filled, and then, test data in chain-1 are complemented and stored. When stored vectors are shifted into the scan chain, data to be sent to chain-1 are complemented and become the vectors to be applied. Since the majority bits in stored vectors are 0s, multivector run-length encoding is possible. For example, the last seven 0-bits in stored t1 and the first six 0-bits in t2 can be encoded as a single run of 0s. 2) Fixed-Symbol-Length Codes: The compressibility of fixed-symbol-length schemes also benefits from skewed probability distribution in scan chains. For example, the Huffman code achieves better results when some patterns appear more frequently than others, and the partition of chain-0 and chain-1 can achieve this goal. We shall explain the reason through an example. First, in Example 1, we consider fixed-length-symbol blocks with n = 2 where p0 and p1 are equal. Fig. 7 shows the graph representation of the compatibility among symbol blocks. In this figure, each vertex represents a distinct pattern in a two-bit block, and an edge connecting two vertices implies that these two patterns are compatible. For example, vertices (00) and (X0) are compatible, and they will become the same symbol if X is assigned to 0.

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

WANG et al.: SCAN-CHAIN PARTITION FOR HIGH TEST-DATA COMPRESSIBILITY AND LOW SHIFT POWER

721

Example 1: Assume p0 = p1 = pX = 1/3, and the occurring frequency of each vertex in Fig. 7 is 1/9. In order to achieve a higher compression rate with Huffman encoding, it is necessary to maximize the occurring frequencies of some symbols. For example, in Fig. 7, vertices (00), (0X), (X0), and (XX) are mutually compatible, and they are assigned to symbol 00, as shown in the dark area. If we apply the clique partition shown in Fig. 7, the probabilities that cliques 00, 01, 10, and 11 occur are 4/9, 2/9, 2/9, and 1/9, respectively. When the blocks are encoded with Huffman code, the lengths of the encoded symbols will be 1, 2, 3, and 3; thus, the average codeword length would be 17/9, which is slightly shorter than the block size (2). Next, in Example 2, we consider two-bit blocks in which p0 and p1 are different. Example 2: Assume that the scan chain in Example 1 is partitioned, and now, we want to encode chain-0. Consider the twobit blocks shown in Fig. 7, and let p0,0 = 1/2, p0,1 = 1/6, and p0,X = 1/3. Applying the same clique partition in Fig. 7, the probabilities of cliques 00, 01, 10, and 11 are 25/36, 5/36, 5/36, and 1/36, respectively. The average codeword length will be 53/36, which is much shorter than that in the original chain. B. Intrapartition Order Versus Entropy A potential problem of scan-chain ordering for a specific purpose is that it may adversely affect other design objectives. For example, it was reported that a scan-chain reorder scheme targeted for low shift power without routing constraint may create a scan chain that is more than ten times longer [29], [30]. Therefore, when the scan-chain partition is carried out for compressibility optimization, it is important to ensure that other objectives will not be neutralized. The proposed scheme basically partitions the scan cells into two groups. Moving cells from one partition to the other is not desirable, as it affects the probabilities of 0s and 1s in both groups (i.e., p0,0 , p0,1 , p1,0 , and p1,1 ). On the other hand, the order of scan cells within a given partition may not have a significant impact on the test set compressibility, as the probability distributions in both partitions are not affected. In order to establish the relationship between intrapartition scanchain order and entropy, we conduct experiments on several ISCAS’89 benchmark circuits, and the results are shown in Fig. 8. In this experiment, when a scan chain is partitioned, the scan cells are partitioned into two scan chains whose lengths are roughly equal according to a given test-data set. A formal description of the procedure is given in the following. First, the scan cells are classified into three types: 0-dominating, 1-dominating, and balanced. Definition 4: For a given test set T , the number of specified 0s in scan cell i is denoted as Ci,0 , and the number of specified 1s in this cell is Ci,1 . For instance, consider the test set shown in Fig. 5, which consists of six test vectors. In this example, C1,0 = 2 and C1,1 = 1. In other words, in two vectors, scan cell 1 contains 0s, and in another one (t1 ), its content is 1. In the remaining three vectors, this cell contains X. Therefore, this cell is a 0-dominating cell.

Fig. 8. Entropy distribution of fixed-length symbols (n = 16): (a) s9234, (b) s15850, and (c) s38417.

Two sets of experiments have been conducted; one is for the nonpartitioned scan chain, and the other is for partitioned scan chains. The MinTest [32] vectors are used as the test set, and a bit-raising procedure [33] is applied to increase the amount of X bits. In the nonpartitioned scan chain, initially, scan cells are ordered as they are listed in the benchmark, and all X bits are assigned to 0. In the partitioned scan chain, X bits in chain-0 are assigned to 0s, while those in chain-1 are assigned to 1s. In

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

722

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009

each case, 1000 random moves are made to randomly selected scan cells. The only difference is that, in the partitioned scan chains, a selected scan cell is only allowed to move to a place within the same partition, while in the nonpartitioned scan chain, a cell can be moved to any place. In this experiment, the entropy is calculated for a fixed symbol length with block size 16. The results are shown in Fig. 8. In each histogram, the red lines at the left-hand side are the distribution of partitioned chains, while the blue lines on the right-hand side represent the distribution of the nonpartitioned chain. Two conclusions can be made from the results: 1) The partition scheme indeed reduces the test-data entropy and, thus, will provide a higher compression rate, and 2) the entropy, and thus, the maximum compressibility, is less significantly affected by a change of scan-chain order in partitioned scan chains. This can be seen from the histograms in Fig. 8, as the variance of partitioned case is always smaller than that of a nonpartitioned case. C. Scan-Chain Partition Under Routing Constraint In this section, a partition scheme that is targeted for both high compressibility and low routing overhead is proposed. The tradeoff between these two goals is controlled by a threshold value α. The definitions of the three types of scan cells are modified according to α as follows. Definition 5: Scan cell i is 0-dominating if Ci,0 − Ci,1 > α; and it is 1-dominating if Ci,1 − Ci,0 > α. A balanced cell satisfies the condition |Ci,1 − Ci,0 | ≤ α. To improve test-data compressibility, 0-dominating cells should belong to chain-0, and 1-dominating cells are designated to chain-1. Balanced cells can be assigned to either chain according to the requirement of other optimization goals. When α is 0, a scan chain is partitioned strictly according to Ci,0 and Ci,1 , which may lead to a better compression rate. A larger α implies that more cells can be moved from one partition to the other, which may hurt the test compression rate while improve other goals. A partition example is shown in Fig. 9, where the goal is to improve compression rate with a short scan chain. Initially, the threshold value α is set to 0, and the result is shown in Fig. 9(a). In this case, chain-1 contains cells {3, 6, 7, 8, 9}, which spans over a wide area and requires a long routing path to connect these cells. When α is raised to 1, cells 3 and 6 become balanced, as shown in Fig. 9(b). In this case, cells 1 and 3 should be assigned to chain-0 since their Euclidean distance to chain-0 is shorter; similarly, cell 6 is designated to chain-1 because of physical adjacency. As a result, the final scan chain will have a shorter routing length. D. Multiple Scan Chains The partition scheme described in this section is also applicable to the multiple-scan-chain architecture if multiple-scanchain decompressors are available [16], [19]. Fig. 10 shows how the proposed method works with multiple scan chains. Assume that the scan cells of a circuit under test are divided into m scan chains, as shown in Fig. 10(a). The jth scan cell in scan chain i is denoted as SCi,j . Therefore, a test vector is divided into m subvectors. For simplicity, it is assumed that the lengths of

Fig. 9.

Partition example.

all scan chains are equal, and let the length be denoted as l. If some scan chains are shorter than others, X bits are added to the end of these subvectors to make them equal in length [16]. In each scan chain, the cells in the first half of a scan chain belong to the 0-dominant part, while the remaining cells belong to the 1-dominant part. A bit inversion is introduced between the two parts in each scan chain, as shown in the figure. The decoder produces an m-bit word, where each bit is fed to a scan chain. In other words, scan cells in the same column contain an m-bit decoded word. Thus, an l · m-bit vector is conceptually loaded into a virtual scan chain according to the following order: SC1,1 , SC2,1 , . . . , SCm,1 , SC1,2 , . . . SCm,2 , . . . , SC1,l , . . . , SCm,l . It can be seen from Fig. 10(a) that the first part of this “virtual scan chain” consisting of cells belong to the 0-dominant part and the remaining scan cells belong to the 1-dominant part if all subchains in the 0-dominant part are of the same length. The compression algorithm should encode a test vector according to this virtual scan-chain order instead of the physical scan chains. Fig. 10(b) shows the multiple-scan-chain equivalent of the single-scan-chain example shown in Fig. 6 with m = 2. The virtual order of the multiple-scan-chain architecture is the same as the single scan chain shown in Fig. 6. Thus, any compression technique that can be applied to a single scan chain is also applicable this multiple-scan-chain architecture. It is not necessary to make the 0-dominant parts of all scan chains equally long once an inversion is inserted between the two parts of each scan chain. In this case, all bit positions in a decoded vector are 0-dominant, as shown in Fig. 10(b). The only requirement is that the 0-dominant part has to precede the 1-dominant part. In summary, in the multiple-scan-chain architecture, the proposed scheme works as follows. First, partition the scan cells

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

WANG et al.: SCAN-CHAIN PARTITION FOR HIGH TEST-DATA COMPRESSIBILITY AND LOW SHIFT POWER

723

TABLE I CIRCUIT STATISTICS AND MINTEST [16] TEST SET STATISTICS

A. Predetermined Test Set

Fig. 10. Multiple scan chains: (a) General architecture and (b) an example.

into 0- and 1-dominant parts using the method discussed in Section IV-C. In each part, m subchains are formed targeted for short routing lengths only, as the physical scan chains are not the same as the virtual scan chain for compression. A complete scan chain is formed by connecting two subchains from different parts according to geometric vicinity. A compression algorithm encodes test vectors according to the virtual scanchain order of a given multiple-scan-chain architecture to get compressed test data. V. E XPERIMENTAL R ESULTS In this section, we present experimental results that show that the proposed partition method indeed improves compressibility under various test compression schemes, while at the same time, it can restrict the overall scan-chain routing length. The overall test power will be reduced as well. The partition is carried with respect to a determined test set, which may render it less efficient for other test sets. In the later part of this section, we will show that the proposed method still provides improved compressibility for a different test set. All experiments are carried for the single-scan-chain architecture.

We have conducted experiments on some larger ISCAS’89 benchmark circuits; the numbers of scan cells in these circuits are given in the second column of Table I. These circuits are synthesized with UMC 0.18-μm technology to obtain the final circuit layouts. The MinTest [32] vectors as used as the initial test set, and the related statistics are also listed in Table I, including the number of test vectors (#TV), test-data volume (TD ), and achieved FC. The MinTest vectors are fully specified; therefore, we apply the bit-raising technique [33] to raise specified bits to X whenever it is possible. The number of X bits and the percentage of X bits in each circuit are listed in the last two columns of Table I. The test sets are then compressed by various encoding schemes with and without scan-chain partitioning; the encoded test-data volume (TE ) are summarized in Table II. In the nonpartitioned scan chain, the scan cells are ordered according to the way that they are specified in the benchmark example. In the partitioned case, scan cells are ordered to achieve minimum length routing [34]. Four encoding schemes are tried. The first two are full Huffman coding [5] and optimal selective Huffman coding [8] (fixed-symbol-length code), and the other two are Golomb and FDR encoding (variable-symbol-length codes). In each scheme, the test data are encoded with nonpartitioned (column “No Partition”) and partitioned (columns “Partitioned”) scan chains. In the partitioned case, two types of partitioned scan chains are constructed, in which one is for α = 0 and the other is for α = 5. For the Huffman encoding, the block size is n = 8, and for the optimal selective Huffman coding [8], 16 encoded distinct blocks are used. The encoded data volumes are shown in Table II. In all compression schemes, the partitioned scan chains achieve higher reduction rate than the nonpartitioned ones. The compression rates of these schemes are listed in Table III. For a given compression scheme, the compression rate (CR) is defined as follows: CR = (TD − TE )/TD . According to the results, scan chains partitioned with α = 5 achieve slightly lower CRs than scan chains partitioned with α = 0. However, even with α = 5, the partitioned scan chains still provide 9.4% (Huffman code) to 12.2% (FDR code) more compression than those provided by nonpartitioned scan chains. The overall routing length of the scan chains are listed in Table IV. The second column shows the wire length of a scan chain synthesized for the shortest routing length [34]. The third and fourth columns give the wire lengths of the scan chains synthesized with α = 0 and α = 5, respectively. As expected, the overall wire lengths are longer with α = 0. However, even in this case, the scan chain is only about 35% longer than

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

724

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009

TABLE II COMPRESSION RESULT: ENCODED TEST-DATA VOLUME (TE )

TABLE III COMPRESSION RESULT: DATA COMPRESSION RATE

TABLE IV ROUTING LENGTH (IN MICROMETERS)

TABLE VI COMPARISON OF POWER REDUCTION TO 0-FILLING HEURISTIC [35]

TABLE V TEST POWER REDUCTION: ESTIMATED BY WSA

those achieved by an algorithm targeted for the minimum length routing [34]. When α increases to five, the extra routing overhead quickly reduces to about 21%, while the average loss of compression rate is lower than 2% in all cases. Since the proposed scheme puts scan cells containing similar test data in the same partition, it is natural that the amount of bit transitions between adjacent cells will be lower than those in a nonpartitioned scan chain. In this paper, the dynamic power is estimated by weighted switching activity (WSA), and the results are listed in Table V. In each circuit, both peak and total WSA are given. The MinTest [32] patterns are launched through a single scan chain according to the given input order.

In the proposed method, the scan-chain order obtained by partition with α = 5 is used. The results show that, compared to the MinTest patterns, the proposed partition scheme can provide nearly 50% reduction in total power. Since MinTest patterns are not optimized for test power, it is not surprising that the proposed method can provide significant test power reduction compared with such patterns. Therefore, it is more interesting to compare power reduction results to other low-power test schemes. It was reported that the 0-filling heuristic [35] achieves the best shift power reduction, as it reduces transitions in both input stimuli and output responses. In Table VI, the proposed method is compared to the 0-filling heuristic. In this table, the power consumed by the 0-filled patterns is normalized to one. Two sets of comparisons are shown. In the first part, only the WSA due to scan-in test patterns is compared. If we consider the power consumption by scan-in patterns only, the proposed method achieves higher reduction. The reason is that patterns produced by the proposed method have lower entropy, which implies fewer bit transitions in patterns. However, the 0-filled patterns achieve better overall power reduction, as the output response of such patterns are mostly 0s. As a result, the shift power due to output response is

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

WANG et al.: SCAN-CHAIN PARTITION FOR HIGH TEST-DATA COMPRESSIBILITY AND LOW SHIFT POWER

725

Fig. 11. Scan-chain routing of (a) s5378, (b) s13207, and (c) s38417. Three routing orders have been implemented (from left to right): Shortest path, α = 0, and α = 5.

also lower with 0-filling [35]. Nevertheless, except for S13207, the power reduction achieved by the proposed method is not far from that of 0-filling. For S13207, the performance of 0-filling is much better, mainly due to the larger percentage of X bits, as shown in Table I. The power estimation presented in Table V only takes into account the dynamic power consumed in the circuit under test, while power consumption in the decoder is not considered. For complicated encoding schemes, the power consumed by decoders can be a significant portion of the test power. Nevertheless, the proposed scheme can efficiently shift power in the test process. The physical routing paths of three benchmarks are shown in Fig. 11, where the left column gives the results of minimum length routing, the middle column shows routings for the α = 0 partition, and the right column illustrates routings of the α = 5 partition. In the partitioned cases, red and blue lines indicate chain-0 and chain-1, respectively. It can be seen from the figure that, with α = 0, scan cells in chain-0 and chain-1 are interwoven over the routing surface; thus, the overall routing paths are longer. In contrast, with α = 5, scan cells in chain-0 and chain-1 tend to locate in different parts of the routing surface, which leads to a shorter routing path. B. Extension to Other Test Sets One problem of the scan-chain partition scheme is that it is targeted for a given test set; therefore, a change of test pattern set may be problematic. Fortunately, the essence of this scheme

TABLE VII STATISTICS OF A NEW TEST SET [37]

is to create subchains with skewed distributions of 0s and 1s, and this goal is usually achievable even if the test set is changed. In order to show that the partition scheme can still provide an improved compression rate even if the test set is changed, we use the Atlanta [36] automatic test pattern generator (ATPG) to generate a new set of test cubes. To produce a skew probability distribution, in chain-0, two-thirds of randomly selected X bits are assigned to 0; similarly, two-thirds of randomly selected X bits in chain-1 are assigned to 1. Since this test set is very large, a modified fault detection count-directed clustering [37] procedure is invoked to produce a more compact test set. The statistics of this new test set are summarized in Table VII. The remaining procedure is the same as before. First, a bit-raising procedure is executed to increase the amount of X bits. Second, in the nonpartition scan chains, X bits are assigned to 0s, while in partition scan chains, X bits are assigned to their preferred values. The results are shown in Table VIII, where columns under titles “NP” and “P” are the results for nonpartitioned and partitioned scan chains, respectively.

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

726

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009

TABLE VIII COMPRESSION RESULTS OF A NEW TEST SET (PARTITION WITH α = 5)

From the results in Table VIII, it is evident that, for a different test set, this scheme still provides an improved compression rate if the ATPG process is executed carefully. VI. C ONCLUSION This paper showed that the maximum compression rate of a test compression scheme can be higher if the distribution of 0s and 1s in the test set is skewed. A simple way to achieve this goal is to partition the scan cells according to the specified values in them. Since this scheme puts scan cells that contain similar data in the same part of a scan chain, the shift power is lowered as well. An interesting aspect of this scheme is that only the probabilities of 0s and 1s matter; therefore, the scancell order in each chain is not important. Thus, scan cells in the same partition can be ordered to minimize routing length or to serve other purposes. In case new test patterns have to be added to the test set, a higher compression rate is still achievable if the new patterns comply with the required probability distribution of 0s and 1s. In order to achieve the optimal compression result, it is necessary to provide data with better compression lower bound (i.e., entropy) and apply a compression scheme that actually reaches the lower bound. In this paper, we only addressed how to reorganize test data to get a better lower bound. Since the reorganized test data were less random, the compression results were better in all experimented encoding schemes. R EFERENCES [1] Y. Zorian, E. J. Marinissen, and S. Dey, “Testing embedded core based system chips,” in Proc. IEEE Int. Test Conf., 1998, pp. 130–143. [2] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures. San Mateo, CA: Morgan Kaufmann, 2006. [3] S. M. Reddy, K. Miyase, S. Kajihara, and I. Pomeranz, “On test data volume reduction for multiple scan chain designs,” in Proc. IEEE VLSI Test Symp., Apr. 2002, pp. 103–108. [4] L. Li, K. Chakrabarty, and N. A. Touba, “Test data compression using dictionaries with selective entries and fixed-length indices,” ACM Trans. Des. Autom. Electron. Syst., vol. 8, no. 4, pp. 470–490, Oct. 2003. [5] A. Jas, J. G. Dastidar, and N. A. Touba, “Scan vector compression/ decompression using statistical coding,” in Proc. VLSI Test Symp., 1999, pp. 114–120. [6] A. Jas, J. G. Dastidar, M. Ng, and N. A. Touba, “An efficient test vector compression scheme using selective Huffman coding,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 6, pp. 797–806, Jun. 2003. [7] M. Nourani and M. H. Tehranipour, “RL-Huffman encoding for test compression and power reduction in scan applications,” ACM Trans. Des. Autom. Electron. Syst., vol. 10, no. 1, pp. 91–115, Jan. 2005. [8] X. Kavousianos, E. Kalligeros, and D. Nikolos, “Optimal selective Huffman coding for test-data compression,” IEEE Trans. Comput., vol. 56, no. 8, pp. 1146–1152, Aug. 2007.

[9] A. Jas and N. A. Touba, “Test vector compression via cyclical scan chains and its application to testing core-based designs,” in Proc. Int. Test Conf., Oct. 1998, pp. 458–464. [10] A. Chandra and K. Chakrabarty, “System-on-a-chip test-data compression and decompression architectures based on Golomb codes,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 3, pp. 355–368, Mar. 2001. [11] A. Chandra and K. Chakrabarty, “Test data compression and decompression based on internal scan chains and Golomb coding,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 6, pp. 715–722, Jun. 2002. [12] A. Chandra and K. Chakrabarty, “Test data compression and test resource partitioning for system-on-a-chip using frequency-directed runlength (FDR) codes,” IEEE Trans. Comput., vol. 52, no. 8, pp. 1076–1088, Oct. 2003. [13] P. T. Gonciari, B. M. Al-Hashimi, and N. Nicolici, “Variable-length input Huffman coding for system-on-a-chip test,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 6, pp. 783–796, Jun. 2003. [14] X. Kavousianos, E. Kalligeros, and D. Nikolos, “Test data compression based on variable-to-variable Huffman encoding with codeword reusability,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 7, pp. 1333–1338, Jul. 2008. [15] E. H. Volkerink, A. Khoche, and S. Mitra, “Packet-based input test data compression techniques,” in Proc. IEEE Int. Test Conf., 2002, pp. 154–163. [16] M. Tehranipour, M. Nourani, and K. Chakrabarty, “Nine-coded compression technique for testing embedded cores in SoCs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 719–731, Jun. 2005. [17] L. Lingappan, S. Ravi, A. Raghunathan, N. K. Jha, and S. T. Chakradhar, “Test-volume reduction in systems-on-a-chip using heterogeneous and multilevel compression techniques,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 10, pp. 2193–2206, Oct. 2006. [18] X. Kavousianos, E. Kalligeros, and D. Nikolos, “Multilevel Huffman coding: An efficient test-data compression method for IP cores,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 6, pp. 1070–1083, Jun. 2007. [19] X. Kavousianos, E. Kalligeros, and D. Nikolos, “Multilevel-Huffman test-data compression for IP cores with multiple scan chains,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 7, pp. 926–931, Jul. 2008. [20] B. Köenemann, “LFSR-coded test patterns for scan designs,” in Proc. Eur. Test Conf., Apr. 1991, pp. 237–242. [21] A. Al-Yamani and E. J. McCluskey, “Seed encoding for LFSRs and cellular automata,” in Proc. ACM/IEEE Des. Autom. Conf., Jun. 2003, pp. 560–565. [22] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Embedded deterministic test,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 5, pp. 776–792, May 2004. [23] K.-J. Lee, J.-J. Chen, and C.-H. Huang, “Broadcasting test patterns to multiple circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 12, pp. 1793–1802, Dec. 1999. [24] I. Hamzaoglu and J. Patel, “Reducing test application time for full scan embedded cores,” in Proc. IEEE Int. Symp. Fault Tolerant Comput., Jun. 1999, pp. 260–267. [25] D. Xiang, K. Li, J. Sun, and H. Fujiwara, “Reconfigured scan forest for test application cost, test data volume, and test power reduction,” IEEE Trans. Comput., vol. 56, no. 4, pp. 557–562, Apr. 2007. [26] C. E. Shannon, “A mathematical theory of communication,” Bell Syst. Tech. J., vol. 27, no. 1, pp. 379–423, Jul. 1948. [27] A. Chandra and K. Chakrabarty, “How effective are compression codes for reducing test data volume,” in Proc. IEEE VLSI Test Symp., 2002, pp. 91–96.

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.

WANG et al.: SCAN-CHAIN PARTITION FOR HIGH TEST-DATA COMPRESSIBILITY AND LOW SHIFT POWER

[28] K. J. Balakrishnan and N. A. Touba, “Relationship between entropy and test data compression,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 26, no. 2, pp. 386–395, Feb. 2007. [29] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “Efficient scan chain design for power minimization during scan testing under routing constraint,” in Proc. IEEE Int. Test Conf., 2003, pp. 488–493. [30] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and A. Virazel, “Design of routing-constrained low power scan chains,” in Proc. IEEE Des. Autom. Test Eur. Conf. Exhib., 2003, pp. 62–67. [31] S.-J. Wang, K.-L. Peng, K.-C. Hsiao, and K. S.-M. Li, “Layout-aware scan chain reorder for launch-off-shift transition test coverage,” ACM Trans. Des. Autom. Electron. Syst., vol. 13, no. 4, pp. 1–16, Sep. 2008. [32] P. Hamzaoglu and J. H. Patel, “Test set compaction algorithms for combinational circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 8, pp. 957–963, Dec. 2000. [33] K. Miyase, S. Kajihara, I. Pomeranz, and S. M. Reddy, “Don’t care identification on specific bits of test patterns,” in Proc. Int. Conf. Comput. Des., Sep. 2002, pp. 194–199. [34] K. D. Boese, A. B. Kahng, and R.-S. Tsay, “Scan chain optimization: Heuristic and optimal solutions,” in “Research Report,” UCLA CS Dept., Los Angeles, CA, Oct. 1994. [35] K. M. Butler, J. Saxena, A. Jain, T. Fryars, J. Lewis, and G. Hetherington, “Minimizing power consumption in scan testing: Pattern generation and DFT techniques,” in Proc. IEEE Int. Test Conf., Oct. 2004, pp. 355–364. [36] K. Lee and D. S. Ha, “Atlanta: An efficient ATPG for combinational circuits,” Dept. Elect. Eng., Virginia Polytechnic Inst. State Univ., Blacksburg, VA, Tech. Rep., 93-12, 1993. [37] A. El-Maleh and S. Khursheed, “Efficient test compaction for combinational circuits based on fault detection count-directed clustering,” IET Comput. Digit. Techn., vol. 1, no. 4, pp. 364–368, Jul. 2007.

Sying-Jyan Wang (S’90–M’92) received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1984 and the Ph.D. degree in electrical engineering from Princeton University, Princeton, NJ, in 1992. From 1984 to 1986, he was a Reserve Officers’ Training Corps officer with the Air Force, Taiwan. From 1986 to 1987, he was a Teaching Assistant with the Department of Electrical Engineering, National Taiwan University. He was a Consultant with AT&T Bell Laboratories, Holmdel, NJ, from 1989 to 1990. Since 1992, he has been with the Department of Computer Science and Engineering, National Chung Hsing University (NCHU), Taichung, Taiwan, where he was the Chair from 1999 to 2005 and where he is currently a Professor. His research interests include very large scale integration (VLSI) design, digital testing, and computer-aided design of VLSI systems.

727

Shih-Cheng Chen received the M.S. degree in computer science and engineering from National Chung Hsing University, Taichung, Taiwan, in 2007. He is currently a Computer-Aided Design (CAD) Engineer with Global Unichip Corporation, Hsinchu, Taiwan. His research interests include very large scale integration testing and CAD.

Huai-Yan Shiu received the B.S. degree in industrial technology education from National Taiwan Normal University, Taipei, Taiwan, in 2005 and the M.S. degree in computer science from National Chung Hsing University, Taichung, Taiwan, in 2008. Currently, he is with the Chinese Army, Taiwan. His research interests in digital testing and computeraided design of very large scale integration systems.

Yun-Lung Chu received the B.S. degree in computer science and information engineering from National Taitung University, Taitung, Taiwan, in 2007. He is currently working toward the M.S. degree in the Department of Computer Science and Engineering, National Chung Hsing University, Taichung, Taiwan. His research interests include digital testing and computer-aided design of very large scale integration systems.

Katherine Shu-Min Li (S’04–M’06) received the B.S. degree from Rutgers University, New Brunswick, NJ, and the M.S. and Ph.D. degrees from the National Chiao Tung University, Hsinchu, Taiwan, in 2001 and 2006, respectively. She is currently an Assistant Professor with the Department of Computer Science and Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan. Her research interests focus on crosstalk effects, signal integrity, system-on-a-chip testing, floorplanning and routing for testability and yield enhancement, design for manufacturing, design for yield, transition faults, scan reordering, scan routing, low-power scan techniques, particularly on oscillation-ring test scheme, and interconnect optimization in deep submicrometer and nanotechnology. Dr. Li is a member of the IEEE Circuits and Systems Society, the Association for Computing Machinery (ACM), and the ACM/Special Interest Group on Design Automation.

Authorized licensed use limited to: National Chung Hsing University. Downloaded on June 5, 2009 at 05:16 from IEEE Xplore. Restrictions apply.