In the first paper, BCooling a .... the Technical Director for DARPA Heretic project ... in 2000, and the UCSC School of Engineering FIRST Professor Award.
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Scanning the Special Issue on On-Chip Thermal Engineering BY ALI SHAKOURI, Member IEEE
Guest Editor SUNG-MO KANG, Fellow IEEE
Guest Editor AVRAM BAR-COHEN, Fellow IEEE
Guest Editor BERNARD COURTOIS, Member IEEE
Guest Editor
H
EATING and thermal management are among the key factors limiting the performance of future integrated circuit (IC) chips. As feature sizes decrease and clock frequencies increase, overall This Special Issue brings power dissipation, heat generation disparate disciplines density, and chip heat flux all in- together and discusses crease. This constrains the ultimate key topics and future performance of the chip, accelerating electromigration and oxide break- thrusts in the most down, which are both exponentially relevant thermal dependent on temperature, and ne- management cessitating thermally aware design technologies. and aggressive thermal management to achieve the desired performance goals. Despite increasing emphasis on lowpower design, the demand for higher levels of system integration on-chip or in a package is leading to higher power density and thus requiring more effective on-chip thermal management. In this special issue, you will find a series of papers that covers various aspects of on-chip thermal engineering. The breadth of these papersVranging from device and circuit models, to power- and temperature-aware very large scale integration (VLSI) design, to identification of packaging and material limitations, and to the description of different liquid, microchannel, or solidstate cooling solutionsVdemonstrates the significance and interest of on-chip thermal engineering. These topics are typically discussed in different conferences and journals sponsored by various IEEE societies (i.e., those relating to packaging, reliability, materials, devices, and solid-state circuits). Very rarely is Digital Object Identifier: 10.1109/JPROC.2006.879788
0018-9219/$20.00 Ó 2006 IEEE
the whole subject discussed in a holistic manner so that engineers and researchers could consider various tradeoffs and options to solve specific problems. This special issue tries to bring these disparate disciplines together and discusses key topics and future thrusts in the most relevant thermal management technologies. In the first paper, BCooling a Microprocessor Chip,[ Mahajan et al. brings out real-world problems and challenges in cooling hot chips such as Intel Pentium III and Intel Itanium microprocessors. Some examples of the current packaging and system thermal solutions are presented, followed by a brief discussion of some of the future trends in demand and some solution strategies being considered to meet such demands. The second paper, BThermal Modeling, Analysis and Management in VLSI Circuits: Principles and Methods,[ by Pedram and Nazarian, presents key sources of power dissipation and its dependence on temperature in CMOS VLSI circuits, and techniques for full-chip temperature calculation
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with special attention to its implications on the design of high-performance, low-power VLSI circuits. The authors also present an overview of techniques to improve the full-chip thermal integrity by means of the offchip method versus on-chip method and the static method versus the adaptive method. The third paper, BTemperatureAware Placement for SOCs,[ by Chen et al., addresses thermal integrity in SOCs, where temperature effects may lead to reliability issues. Various placement algorithms are presented and discussed. Finally, selected research topics for further investigation are briefly addressed, such as interconnect thermal distribution, thermal floor planning, chip-package thermal codesign, and three-dimensional circuits. The fourth paper, BDynamic Surface Temperature Measurements in ICs,[ by Altet et al., addresses temperature measurements at the surface of an IC. As noted before, temperature effects may lead to reliability issues; they may also affect the performance of the device. Various temperature monitoring systems are reviewed before presenting a more detailed analysis of two sensing techniques: namely, optical methods and embedded sensors. The fifth paper, BOn-Chip Thermal Management With Microchannel Heat Sinks and Integrated Micropumps,[ by Garimella et al., deals with liquid-based electronics cooling systems. The capabilities of microchannel heat sinks and micropumps are discussed. Selected research topics, necessary for wider incorporation of these techniques in practical solutions, are addressed. Use of dielectric liquids in intimate contact with the ICs eliminates the deleterious effects of solid-solid and thermal interface material (TIM) interface resistances and harnesses the highly efficient phase-change processes to the critical thermal management of advanced IC chips. In BDirect
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Liquid Cooling of High Flux Micro and Nano Electronic Components,[ Bar-Cohen et al. review the thermophysics of phase-change processes and describe the available dielectric liquid cooling techniques and their history. They then turn to the phenomenology of pool boiling, spray/jet impingement, gas-assisted evaporation, and synthetic jet impingement with dielectric liquids. Available correlations for predicting the heat transfer coefficients and limiting heat transfer rates, as well as documented empirical results for these promising techniques for on-chip hot spot cooling, are also provided and compared. TIMs play a key role in the thermal management of ICs, serving to mechanically and electrically isolate the chip, heat spreader, and heat sink, while accommodating the transfer of high heat fluxes from the chip to the external surfaces of the package. The dominant role played by TIMs in the chip-to-ambient thermal resistance has stimulated considerable effort in the rheology-based modeling and design of polymeric TIMs and brought renewed attention to the thermal characteristics of solders. The paper BThermal Interface Materials: Historical Perspective, Status, and Future Directions,[ by Prasher, addresses these aspects of TIMs and also explores the available literature on the reliability of polymeric TIMs, along with the potential benefits associated with the use of nanoparticles and nanotubes in thermal interface materials. Heat transfer research for integrated electronics has traditionally focused on the transport off the semiconductor chip. However, technology roadmap trends and the introduction of novel device technologies are projected to lead to significant thermal bottlenecks at the transistor and circuit level. The paper, BHeat Generation and Transport in Nanometer-scale Transistors,[ by Pop et al., deals with thermal challenges in current and future transistors. Their research shows that
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decreasing dimensions leads to nanometer scale hot spots in the transistor drain region. This can increase the series electrical resistances. The authors give a comprehensive overview of subcontinuum phenomena such as ballistic electron transport and the nonequilibrium between electrons and optical and acoustic phonons. The paper also emphasizes how the increased surface-to-volume ratio of novel transistor designs, such as ultrathin body and nanowires, and the introduction of materials with lower thermal conductivity, such as germanium, will bring additional complexity to thermal management within individual devices and circuits. The paper, BOverview of SolidState Thermoelectric Refrigerators and Possible Applications to On-Chip Thermal Management,[ by Sharp et al., gives an overview of the operation of solid-state Peltier coolers, describing how they could be applied inside the package for either thermal management of an entire chip or targeted hot spot cooling. Useful rules of thumb are given for the design of thermoelectric modules and the key parasitic effects which are important limiting factors in practical applications. The last paper, BNanoscale Thermal Transport and Microrefrigerators on a Chip,[ by Shakouri, provides a brief overview of recent advances in nanoscale thermal transport, with an emphasis on the impact on IC thermal management. The latest results on the reduction of silicon thin-film thermal conductivity and the thermal properties of carbon nanotubes and their bundles are reviewed. Various techniques to remove dynamic hot spots in IC chips are described, complementing the discussion on package-level solutions in the paper by Sharp et al. Silicon-based microrefrigerators that could be monolithically integrated with circuits are described. Various theoretical and experimental results for different superlattice structures are reviewed and future prospects are discussed. h
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A B O U T T H E G U E S T E DI T O R S Ali Shakouri (Member, IEEE) received the undergraduate degree from Ecole Nationale Superieure des Telecommunications de Paris, France, in 1990 and the Ph.D. from the California Institute of Technology, Pasadena, in 1995. He is Professor of Electrical Engineering at University of California Santa Cruz (UCSC). He was the Technical Director for DARPA Heretic project that demonstrated SiGe-based micro refrigerators on a chip. He is currently the Director of the Thermionic Energy Conversion Center, an Office of Naval Research multiuniversity research initiative aiming to improve direct thermal to electric energy conversion technologies. His current research is on nanoscale heat and current transport in semiconductor devices, submicrometer thermal and ac imaging, microrefrigerators on a chip, and novel optoelectronic ICs. He received the Packard Fellowship in 1999, the NSF Career award in 2000, and the UCSC School of Engineering FIRST Professor Award in 2004.
Sung-Mo (Steve) Kang (Fellow, IEEE) received the Ph.D. degree in electrical engineering from the University of California at Berkeley in 1975. Until 1985 he was with AT&T Bell Laboratories at Murray Hill and Holmdel, and also served as a faculty member of Rutgers University. From August 1985 to December 2000, he was Professor of Electrical and Computer Engineering, Computer Science and Research Professor of Coordinated Science Laboratory and Beckman Institute for Advanced Science and Technology of the University of Illinois at Urbana-Champaign. From August 1995 to December 2000, he served as Head of the Department of Electrical and Computer Engineering. In January 2001, he joined the University of California at Santa Cruz as Dean of Baskin School of Engineering and Professor of Electrical Engineering. He was named the first Charles Marshall Senior University Scholar, an Associate in the Center for Advanced Study, and has served as the Founding Director of Center for ASIC Research and Development at the University of Illinois at Urbana-Champaign. He was a Visiting Professor at the Swiss Federal Institute of Technology at Lausanne in 1989, at the University of Karlsruhe in 1997 and at the Technical University of Munich in 1998. He was a Chaired Visiting Professor of Electrical Engineering and Computer Science of Korea Advanced Institute of Science and Technology (KAIST) from 2002 to 2004. From July 2002 to June 2003, Dr. Kang served as President of Silicon Valley Engineering Council which is the alliance for engineering leaders in Silicon Valley. He has served as a member of Board of Governors, Secretary and Treasurer, Administrative Vice President, and 1991 President of IEEE Circuits and Systems Society. He has served on the editorial boards of PROCEEDING OF THE IEEE, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, International Journal of Circuit Theory and Applications, and Circuits, Signals and Systems. He was the Founding Editor-in-Chief of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He holds 15 patents, published over 350 papers and coauthored eight books: Design Automation For TimingDriven Layout Synthesis (Kluwer, 1992), Hot-Carrier Reliability of MOS VLSI Circuits (Kluwer, 1993), Physical Design for Multichip Modules (Kluwer, 1994), Modeling of Electrical Overstress in Integrated Circuits (Kluwer, 1994), Electrothermal Analysis of VLSI Systems (Kluwer, 1999), CMOS Digital Circuits: Analysis and Design (3rd ed. McGraw-Hill, 2002), and Computer-Aided Design of Optoelectronic Integrated Circuits and Systems (Prentice-Hall, 1996). Dr. Kang is a Fellow of Association for Computing Machinery and the American Association for the Advancement of Science, a Foreign Member
of National Academy of Engineering of Korea, and listed in Who’s Who in America, Who’s Who in Technology, Who’s Who in Engineering and Who’s Who in Midwest. He is recipient of the Outstanding Alumnus Award in Electrical Engineering, UC Berkeley (2001), IEEE Third Millennium Medal (2000), SRC Technical Excellence Award (1999), IEEE CAS Society Golden Jubilee Medal (1999), KBS Award in Industrial Technology (1998), IEEE CAS Society Technical Achievement Award (1997), Humboldt Research Award for Senior US Scientists (1996), IEEE Graduate Teaching Technical Field Award (1996), IEEE Circuits and Systems Society Meritorious Service Award (1994), SRC Inventor Recognition Awards (1993, 1996, 2002), IEEE CAS Darlington Prize Paper Award (1993), and best paper awards such as the 22nd EOS/ESD Best Paper Award (2000), ICCD Best Paper Award (1986), and Myril B. Reed Best Paper Award (1979). He is a Distinguished Lecturer of the IEEE Solid-State Circuits Society and the IEEE Circuits and Systems Society.
Avram Bar-Cohen (Fellow, IEEE) is a Distinguished University Professor and Chair of the Mechanical Engineering Department, University of Maryland, College Park, where he continues his research in the thermal management of micro/ nano systems. He is coauthor (with A. D. Kraus) of Design and Analysis of Heat Sinks (Wiley-Interscience, 1995) and Thermal Analysis and Control of Electronic Equipment (McGraw-Hill, 1983) and has coedited nine books in this field. He has authored and coauthored approximately 250 journal papers, refereed proceedings papers, and chapters in books and has delivered more than 50 keynote, plenary, and invited lectures at major technical conferences and institutions. He has advised to completion 52 Ph.D. and M.S. students. Dr. Bar-Cohen currently serves as the Editor-in-Chief of the three IEEE CPMT Transactions, is on the Steering Committee of ASME’s Nanotechnology Institute, and is the ASME representative for the United States on the Assembly for International Heat Transfer Conferences.
Bernard Courtois (Member, IEEE) received the ´rEngineer degree from the Ecole Nationale Supe ´matiques Appliieure d’Informatique et Mathe ´es de Grenoble, Grenoble, France, in 1973 que ´ nieur and Docteur-e ` sand the Docteur-Inge Sciences degrees from the Institut National Polytechnique de Grenoble. He is currently Director of the Laboratory of Techniques of Informatics and Microelectronics for Computer Architecture (TIMA), Grenoble, where researches include CAD, architecture and testing of integrated circuits and systems. He is also the Director of CMP Service, which services universities and companies from about 60 countries for ICs, MCMs, and MEMS prototyping and small volume production. He has been general chair or program chair of various international conferences and workshops, including EDAC-ETC-EUROASIC, Electron and Optical Beam Testing, EUROCHIP, Mixed-Signal Testing, Rapid System Prototyping, THERMINIC, Design, Test and Microfabrication of MEMS/MOEMS ,and POLYTRONIC. He is a member of the Association for Computing Machinery, the American Society of Mechanical Engineers, and the International Microelectronics And Packaging Society. He is an IEEE Computer Society’s Golden Core member, and he is Doctor Honoris Causa of the Technical University of Budapest.
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