FAM 16.4: An All-MOS Charge-Redistribution A/D Conversion Technique*. Ricardo E. Suarez, Paul R. Gray and David A. Hodges. University of California.
SESSION XVI: A/D and D/A Techniques FAM 16.4:
An All-MOS Charge-RedistributionA/D Conversion Technique* Ricardo E. Suarez, Paul R. Gray and David A. Hodges University of California Berkeley, Cai.
THE HIGH COST of the analog-digital conversion function has impeded the application of digital processing of analog signals in cost-sensitive areas such as automotive and consumer electronic control systems. The simultaneous requirement in classical as approaches for high-performance analog circuitry, such operational amplifiers, and digital circuitry forcounting, sequencing,anddatastoragehastended to result in hybrid approaches - one or more bipolar analog chips and an RlOS chip to economically perform the digital functions’. In thispaper anall-MOS charge-redistributionconversion technique realizable witha single low-cost “ I S chip willbe described. In contrast to earlier charge redistribution converters,* no operational amplifiers and only two grounded capacitors are required.Thetechnique is based on the serial D/A converter shown inFigure 1. The conversionbeginswith both capacitors discharged and is accomplished serially by considering the least significant bit b o first. If thisbit is one; a S2 is closed momentarilycharging C 2 to VREF; if it is azero, C2 is left discharged. Switch S1 is then closed momentarily giving a voltage Vout of
Vout =
[bo VREF T I
Leaving the charge on C1, the precharging of C2 is repeated, this timcconsideringthenextleastsignificant bit b1.After redistribution, the output voltage is bo VREF b l VREF Vout = ___ + 4 2 ~
This repetitive procedure has the effect
*This work was supported in Foundation Grant GK-40912.
as the nth redistribution
part by the National Science
‘Schoeff. J. A.. “A Monolithic Analog Subsvstem for HighAccuracyAIDConversion”. I S S C C D I G E S T OF T E C H N I C A L P A P E R S , p. 18-19; Feb., 1973. ‘Schmidt, H.. “Analog Reinholt; 1970.
Digital Conversions”, Van Nostrand-
’Poujors, R., et ai., “Low Level MOS Transistor Amplifed Using StorageTechniques”, ISSCC D I G E S T OF T E C H N I C A L P A P E R S , p. 152-153; Feb., 1973.
of dividing the existing charge on C1 by two and adding a charge of
bn VREF 2 so that for an n-bit D/A conversion
Trout =
c n-0
bn2 ~ v R E F 2N
which is the desired output. With theaddition of a voltage comparatorandsequencing logic the serial D/Aconvertercan beused to constructa successive-approximation A/D converter as shown inFigure 2. In contrast to the D/A conversion, the Most Significant Bit (MSB) must be determined first for A/D. The control logic takes on a particularly simple form since the DAC input string at any given point in the conversion is just the previously encoded word LSB first. For example, consider a point during the A/D conversion in which the k most significant bits have been decided. To decide the ( k + l ) t h bit, a(kt1) bitD/A conversion is carried out assuming the bit under consideration is a I . If the bit should indeed have beenazero, the D/A output voltage will exceed the analog voltage being encoded, and this will be indicated by the comparator. The correct valueof the bit is stored,andthenext serial D/A is started. Since the D/A conversion for the kth bit requires k rcdistributions, the total number of redistributions required for an M-bit A/D conversion is M(M+l). The principal factors limiting the linearity of this technique are theerrorchargescoupled onto C 1 and C2by theswitch parasitics, the capacitor matching and the capacitor nonlinearity.Thecffect of comparatoroffsetisminimized by an offset cancellation circuit. C 1 and C2 Theerror charge transferred tothecapacitors throughtheswitchcapacitancesduringswitchtransitionsin effect places a lower limit on the capacitor size that can be used while achieving a specified accuracy. This in turn places a limit on the speed with which the redistribution can take place, and hence the overall converter speed. While this design tradeoff can be cased by the use of charge cancellation techniques as described later, it is a fundamental factor limiting speed. The properties of the integrated capacitors C1 and C2 have a strong effecto n the performance of the converter. Because of the freedom to choose an optimum shape factor, mask-edge-induced
mismatches between MOS capacitor pairs is significantly smaller than those for diffused resistors of practical value and comparable physical size. Experimental results from 25 pF round MOS dots of on N+ substratesindicatethat50thpercentilemismatch .06 per cent is achievable with this size capacitor; mismatches from this source are inversely dependent on device size. Capacitance linearity is dependent on the surface concentration in the MOS structure; it was found experimentally that surface concentrationsontheorder of 1020cm-3wererequired to achieve thelinearityrequiredforan8-bitconverter.Inthe prototype circuit, a P+ channel stop diffusion is used to form thebackplate of thepolycrystalline-silicon-Si02 - silicon capacitor. The feasibility of this conversion technique was investigated by the design andfabrication of aprototype8-bitconverter shownschematicallyinFigure 2. Thecritical analog circuitry shown within the dotted lines was fabricated as an N-channel silicon-gate MOS integratedcircuit, while theremaining logic was performed with TTL. Fortybits of registerandassorted
logic are required; in a complete NMOS realization this amount of logicrequires less dieareathantheanalogportion of the of the circuit. A schematic of themonolithicanalogportion prototype circuit is shown in Figure 3. Charge-cancelling devices Q5 and 46 serve t o cancel partially the error charge transferred onto the capacitorsby the switch transistorsQ1, Q3, and Q4;the waveform applied to the gates is the complement of that applied to the gates of the switch transistors. The voltage comparator utilizesanoffsetcancellationscheme3 which simultaneously provides a level shifting function. Prior to the conversion, the two inputs of the comparator are shorted together by 433, and C4 then switches 4 3 0 and 431 are closed. Capacitors C3 and charge to the common mode voltage plus a difference voltage equal to the first stage input offset voltage multiplied by the first stage gain. Upon turnoff of 430, 431, and Q32, the input referred offset then becomes the second stage offset divided by the first stage gain. The stability problem inherent in feedback correction schemes using multistage MOS amplifiers is avoided. A die photois shown in Figure4.
PARALLEL DATA OUT
TEMPORARY STORAGE SHIFTREGISTER
0
'REFERENCE
I
I
SERIAL DAC
! STATUS
CI = c 2 FIGURE
1-Serial
LOGIC
sz
*
CONTROL ( vII)
SHIFT RIGHT
STORAGE
REGISTER
S3 CONTROL ( V I O )
IS1 CONTROL ( V I * )
S E P U E N C E 8 CONTROL
I
PARALLEL XFER DATA
SHIFT LEFT
I
FIGURE 2-Complete analog-digital converter.
-
0
I> -
0
= s FqgJ 9
DAc
START
charge-redistribution digital-to-analog converter.
+-No
1
I*
vss ( - 5 V ) FIGURE 3 4 i r c u i t schematic of monolithic DAC and voltage comparator. [See page 248 for Figure 4.1
FIGURE 4-Photomicrograph of experimental die containing the circuitry of Figure 3.
