Shared Binary Decision Diagram with Attributed Edges for Efficient ...

Shared

Binary Decision Diagram with Attributed Edges for Efficient Booleian Function Manipulation. Shin-ichi

MINATO, Nagisa ISHIURA and Shuzo Department of Information Science Faculty of Engineering Kyoto University Kyoto, 606, JAPAN

YAJIMA

Abstract The efficiency of Boolean function manipulation depends on the form of representation of Boolean funcBinary Decision Diagrams (BDD’s) are ,graph tions. representations proposed by Akers and Bryant. BDD’s have some properties which can be used to enable efficient Boolean function manipulation. In this paper, we describe a technique of more efhcient Boolean function manipulation that uses Shared Binary Decision Diagrams (SBDD’s) with attributed include an ordering algorithm edges. Our implements of input variables and a method of handling don’t care. We show experimental results produced by the implementation of the Boolean function manipulator.

1

Introduction

The manipulation of Boolean functions is one of the most important operations in various application of computer-aided design of digital systems, such as test generation[$], synthesis, and verification[3][7]. Th.e efficiency of the Boolean manipulation depends on the form of representation of the Boolean functions. Binary Decision Diagrams (BDD’s) are graph representations of Boolean functions proposed by Akers[l] and developed by Bryant[2]. BDD’s have important properties that give canonical form to the Boolean functions, and the size of the graph is feasible for many practical functions. Multiple BDD’s can be joined into a single graph which consists of the BDD’s sharing their sub-graphs. We call the graph Shared Binary Decision Diagram improvement of (SBDD). SBDD ‘s are the marked BDD’s. We have been developed an efficient method of manipulating Boolean functions using SBDD’s. There have been several researches on imp.roving BDD’s in terms of the speed and storage. One of them

proposed the use of typed edgesf31. In this paper, we that uses attributed edges in compropose a technique tables. The attributed edges are bination with truth attached to several sorts of attributes. We introduce three kinds of the attributed edges. The size of SBDD’s greatly depends on the order of input variables. We propose a dynamic weight assignment method which computes an appropriate order from the topological information of a circuit. Where we apply SBDD’s to CAD systems, we sometimes use ternary valued functions containing don’t care to mask unnecessary information. In this paper, we propose a D-variable to represent the ternary valued funcWe explain a method of representing the functions. tions by relating the method with the order of the input variables. This argument can be applied to multi-valued functions. In section 2, we begin with a discussion of the properties of SBDD’s and show the techniques of managing SBDD’s. In section 3 we d.emonstrate the improvement of SBDD’s by using attributed edges and truth tables. In section 4 we show the ordering method of inpu t variables. We mention the representation of don’t care in section 5. In section 6 we show experimental results obtained by using these techniques.

2

Shared

2.1

Binary

Properties

Decision

D:iagrams

of BDD’s

BDD’s are graph representations of Boolean functions as shown in Figure 1. The following operations make a BDD from a binary tree which expresses the recursive Shannon’s expansion of a Boolean function. 1. Deleting node.

a node whose two edges direct

2. Sharing

isomorphic

to the same

sub-graphs.

BDD’s give unique form to a Boolean. function when the order of the input variables is fixed. Such graphs axe called Ordered Binary Decision Diagrams (OBDD’s)

27th ACM/IEEE Design Automation Conference@ Paper 3.3 52

0 1990 IEEE 0738-l 00>090/0006/0052 $1 .OO

Figure 2. SBDD

Figure 1. BDD’s

I R? di xltxz~x3

Figure 3. Output inverters

xztx3~x4 x4 1

0

0 x3 1

x3

0 1

0 x2 x2 1 Xl 1 1 0

0

0

Figure 4. Input inverters

1

EIEI

Figure 5. Var iable shifters

and minutely explained by Bryant[2]. In this paper, we simply call them BDD. BDD’s have the following properties. 1. The equivalence between checked by the isomorphism

two functions can be check of these graphs.

2. When the number of input variables is n, the maximum size of BDD’s is O(zn/n). However, in many practical cases, the size is feasible for handling BDD’s on a computer. 3. Logic operations between functions can be carried out within a time almost in proportional to the size of a BDD. 2.2

Properties

of SBDD’s

Multiple BDD’s can be joined into a single SBDD which consists of the BDD’s sharing their sub-graphs as shown in Figure 2. Two isomorphic sub-graphs do not coexist in our SBDD’s. This constraint brings about the following advantages to manipulate Boolean functions. 1. The equivalence between two functions checked by only comparing the pointers graphs.

can be to the

2. By using the quick equivalence checking during Boolean operations, we can apply the following rules: f ’ f = f, f &, f = 0, f +-J = 1, etc.

Figure 6. Combination with truth tables

3. In operations such as f . 1 = f, 0 + f = J, etc., we simply direct an edge to the graph of f without copying it. 4. By sharing sub-graphs, we can compactly many functions together. 2.3

Management

represent

of SBDD’s

In an SBDD, two isomorphic sub-graphs are surely shared. This property is preserved by recording all the nodes in a node table. Every time there is a need of creating a new node, we check the node table. When there exists a node whose two edges and an index are the same, we simply direct an edge to the existing node without creating a new node. The node table is implemented as a hash table for quick checking. In this method, no red?dant nodes are created so that we do not need to reduce the graphs. In Bryant’s algorithm apply[2], redundant nodes are created temporarily and then reduced. It. is an important operation of SBDD’s to delete the subgraphs of unnecessary functions. We attach a reference counter to each node in order to check its necessity. The reference counter shows the number of incoming edges on the node. When a function becomes unnecessary, we decrease the reference counter on the root,node of the function. When it becomes zero, the node is deleted and its child nodes are checked recursively. Unnecessary nodes are not deleted until the memory

Paper 3.3 53

becomes full, because it may be loss of time if we Idelete the node that is unnecessary at the moment but that later becomes necessary. The waste nodes are deleted in a lump like a garbage collection. We use another hash table in order to avoid duplicate operations in binary operations as explained in [2]. Because of the limitation of the memory size, we can record only the recent operations. When the size of the table is insufficient, the hit rate of the table falls down and the operation time increases suddenly. We use the following techniques of raising the hit rate within a limited table size. 1. When both root nodes of operand functions have only one incoming edge, we do not record the operation because it will never come to pass again. 2. We reduce the entries of the table by applying rules,f.g=g.f,f+g=g+f,J.~==++, f cl39 = f f3 9, etc.

3

Attributed

Edges

and Truth

the

Tables

We propose the use of attributed edges in SBDD’s. The attributed edges are attached to several sorts of attributes; each attribute is associated with a certain operation. It is regarded as a generalization of the typed edge proposed by Madre[3]. In this paper, we introduce three attributed edges named output inverters, input inverters and variable shifters. The three attributed edges can be used in combination. In addition to the attributed edges, truth tables are linked by by ed.ges in SBDD’s. 3.1

Output

Inverters

An output inverter indicates to complement the function of a sub-graph pointed by the edge (Figure 3). It is based on the same idea as that of Akers’s inverters[l] and Madre and Billon’s typed edges[3]. By using output inverters, we can reduce the size of SBDD’s to half in the best case and execute a NOT operation without generating the graph. The abuse of output inverters breaks an important property; that is, each subgraph uniquely represents a Boolean function. In order to maintain this property, we place the following constraints on the location of the output inverters. 1. We use only ‘0’ as the value of a terminal 2. We do not use an output

inverter

These constraints are basically Madre and BilIon’s work[3]. 3.2

Input

node.

on a ‘0’ edges.

the same as those of

Inverters

We propose another attribute edge that indicates an operation of swapping a ‘0’ edge and a ‘1’ edge at the next node (Figure 4). This operation is regarded as

Paper 3.3

54

complementing

au input

variable,

and we call it input

inverter.

By using input inverters., we can reduc:e the size of an SBDD to half in the best case. There are cases where the input inverter is very effective, while the output inverter is not so effective. The abuse of input inverters breaks a property; that is, each subgraph uniquely represents a. Boolean function. We therefore place a constraint on the location of the input inverters as we do on the output inverters. Due to the use of input inverters two child nodes of each node satisfy the constraints: (‘0’ child) < (‘1’ child), where ‘ First assignment (b) Second assignment Figure 7. Dynamic weight assignment method functions as shown in Figure 8. The use of this technique enables us to reduce the size of the graph and speed up the operations.

4

Ordering

of Input

Variables

It is important to find an appropriate order of input variables because the size of SBDD’s depends on the order[6] [7]. The foll owing properties are observed when an SBDD is generated from a given combinational circuit. 1. The inputs that greatly affect the output should be high in the order.

functions

2. The inputs whose connections are topologically close to one another in the circuit should be near in the order. On the basis of these properties we developed the following dynamic weight assignment method, in which the order of input variables is computed from the topological information of the circuit. First, we assign a weight 1.0 to one of the primary outputs. The weight is propagated toward the primary inputs as follows: 1. At each gate, the weight on the output distributed to the inputs.

is equally

2. At each fan-out point, the weights of the fan-out branches are accumulated into the fan-out stem.

When a circuit has multiple outputs, we select an output of the deepest depth from the primary inputs and start weight assignment. After the ordering, if we have not ordered all the inputs, the output of the next deepest depth is selected to order the remaining inputs.

Representation D-variable

5

5.1

Valued

BDD’s

Care

and BDD

using pairs

In many applications we use not only 0 and 1 but also don’t care in order to mask unnecessary information in an approximate computation. It is an important technique to handle don’t care in BDD’s. There have been two methods of representing don’t care. The first method uses three values on terminal nodes consisting of ‘0’, '1' and ‘*’ as shown in Figure 8. We call it ternary valued BDD. The second method[4] encodes the ternary value into a pair of binary values and represents the function by a pair of usual BDD’s. We call it BDD pair. We denote the pair of the binary functions as f : [fs, Jr]. The assignment of coding affects the efficiency of the operations. We choose the encoding: 1: 11111, * : [o, 11. cl: PA, Under this encoding, attributed edges works effectively in the following operations.

PO,Al = vxl [fo,

The highest order is given to the primary input with the heaviest weight. Because the weight reflects how it contributes to the primary output in a topological sense, the primary inputs with a heavy weight are expected to have large influence on the output function. In order to choose the next primary input, we delete a part of the circuit that can be reached only from the primary input already chosen, and reassign weights from the beginning. An appropriate order is obtained by repeating the assignment and deletion of the sub-circuit. An example of this weight assignment is shown in Figure 7(a)(b). Wh en we delete the sub-circuit, the largest weight in the last assignment is distributed to the neighboring inputs so that their weights are greatly increased. Therefore, the neighboring inputs are given near orders in many cases.

Ternary

of Don’t

Al

- [go,

911

=

[fo

* go,

PO,fll + [go,911 = If0

fl

.L711

+ Sll There is a question whether the ternary valued BDD’s is more efficient than the BDD pairs on vice versa. We compare the two methods using a D-variable in the following section.

5.2

+90,f1

D-Variable

We propose a D-variable to represent don’t care. As shown in Figure 9, a BDD pair can be joined into a single BDD by using a D-variable on the root-node whose subgraphs represent fo and fl. When the function f gives no ‘*’ for any input, fc and fl become the same function and we do not need the D-variable any more. Namely, the graph is consistent with a usual BDD.

Paper 3.3 55

Figure 8. Ternary valued BDD

Figure 9. D-variable

When we extract an irredundant sum of product.r form of the function regarding the D-variables as a usual input variable, the expression has a significant pro:perty; that is, the products including a D-variable represent a don’t care set and the other products represent an on set.

By using D-variable we can relate the ternary valued BDD’s with the BDD pairs. In Figure 9, the D-variable is placed on the highest order of the input variables. When we remove the D-variable to the lowest order, the graph shown in Figure 9 is transformed into a graph in Figure 10. In this graph, the paths through the Dvariable node represent jo = 0 and jr = 1 namely don’t care value, and the other paths represent je = jr = 0 or f0 = jr = 1. Therefore, the form of this graph corresponds to the ternary valued BDD except the node of the D-variable. Consequently, we can say that both of ternary valued BDD’s and BDD pairs are the special forms of BDD’s with a D-variable. The efficiency of the two methods can be compared by changing the order of the D-variable. We had better place the D-variable on a higher order when the D-variable greatly affects the function.

6

Experimental

Results

We implemented a Boolean function manipulator on SUN3/60 (24 MByte, SunOS 4.0) using the above methods. The program consists of about 700 lines of C codes, and the storage requirement is about 22 bytes a node. It can manage a maximum of about 700,000 nodes in our machine. We implemented the three attributed edges and the program of ordering input variables. The efficiency of the program was evaluated by an experiment that generates an SBDD from a given. combinational circuit. Notice that in this experiment the SBDD represents not only a primary output set but also all the internal net set of functions. The storage requirement will become less when we do not represent ,211the functions together. Besides, unnecessary garbage collection is executed in order to count the nodes exactly. The results are shown in Table 1. The circuit tlec8 is an 8 bit decoder, and the circuit encd is an 8 bit encoder.

Paper 3.3

56

Figure 10. D-variable in the lowest order

The circuit add8 and addl6 are adders, and the circuit mu& and mu/t8 are multipliers. The rests are chosen from benchmark circuits in ISCAS’85[5]. The column #Node shows the number of the nodes. Time(sec) shows the total time for loading the circuit data, ordering the input variables, and generating the SBDD. The results show that the functions of these practical circuits can be quickly and compactly represented by the program. We can observe that the CPU time is almost proportional to the.size of the SBDD. Another experiment similar to the above was conducted in order to evaluate the effects of increasing the kind of the attributed edges as shown in Table 2. The column (A) sh ows results of the experiments using a pure SBDD. The column (B) shows the results only using output inverters, and the column (C) shows the results using output inverters and input inverters as well. The column (D) sh ows the results using output inverters, input inverters and variable shifters. The above results show that the use of attributed edges brings 30%:‘50% reduction in the graph size without an increase in CPU time. The rest&s also exhibit that the use of the combination of the three attributed edges is much effective in many cases, though neither of them is all-round effective alone. Table 3 shows the results produced by the combinational use with truth tables. The truth tables is effective only to the circuits that have a small number of inputs. In Table 4 we show the results by ordering input variables. The column (B) lists the results u.sing an original order of the circuit data. The column (C) lists the results of the reverse order of (B), and the column (D) lists the results using a random order. The above results show that the ordering method is important except in a few cases in which the order seems insensitive. The random ordering is quite impracticable. Although the original order sometimes gives a good results, it is a passive method and can not always brings satisfactory results. In short, the ordering method is much effective and essential for many practical applications.

Circuit de& encd add8 add1 6 mult4 mult8

~432 c499 Cd80

cl355 cl908 c5315

Table 1: Experimental Results Circuit size i#Node Time(sec In. out. Nets

12

2 4

9 18

29 31

40 33

9

65

33

17

129

49 97

8

8

97

330

16 36 41 60 41 33 178

16 7 32 26 32 25 123

418 203 275 464

46594 89338

36362 30543

619 938

119201 39373

2608

Circuit de& encd adds add16 mult4 multd

0.3 0.3 0.4 a.7 0.5 18.3 34.1 21.5 11.5

56

0.3 0.4

48

0.3

(31 161

0.4

81

0.7

524 66161

0.5 24.8

417 52750

0.6 0.5

161 400 50504

131299 69217 54019 212196

55.5 22.9 17.5 89.9

104066 65671

119 239

~432 c499 cc380

cl355

51.4

72537 c5315 I 60346 . .

33.0 31.3

cl908

22.5

40306

Table 2: Effects of the Attributed Edges / (A) . , (‘3) #Node Time #Node Time #Node Time 78 0.3 0.4 51 0.3 51

29.8

31378 208324 60850 48353

19.1 36.5 21.3 10.8 49.3

21.6

103998 36986 30903 119465 39533

29.2

41542

A) Using nothmg B) (A)+output inverters Ta Circuit deed en& add8 add16 mult4 mu1t.S

c432 c499 c&30 cl355 cl908

c5315

.e 3: Effect of ‘1?rclth Tables (Not using) -. #Node Time T (Using) #Node Time

51 48 dl

161 400 50504

0.4 0.3 0.4 0.7 0.4

103998

19.8 36.8

36966

21.6

30903 119465 39533

11.1

41542

52.8 22.3 28.6

47 33 66 146

269 49780

103954 36934 30899 119412 39517

41538

0.3 0.3 0.4 0.6 0.5 16.7 35.5 22.4 11.1 52.1

22.4 29.4

Circuit de& en& addd add16 mult4 mult8

#Node

(A)

40 33 49 97

330

~432

46594 89338

c499 a380

36662 30548

cl355 cl908

c5315

119201 39373

40306

Table 4: Orderings (B) Time #Node Time .

0.3 0.3 0.4 0.7 0.5 18.3 34.1 21.5 11.5 51.4

22.5 29.d

Conclusion

We have shown an efficient method of representing and manipulating Boolean functions using SBDD’s, and presented that the use of the attributed edges makes improvement of SBDD’s. We have proposed an ordering method of input variables and a method of representing the functions with don’t care. We have developed a Boolean function manipulator using the above methods, and show that the manipulator is very much efficient in terms of the speed and storage. We expect that this manipulator is useful for the various applications of CAD systems.

References [I] S. B. Akers:

“Binary

Trans. on Computers, 516, (June, 1978).

Decision Diagram”, IEEE Vol. C-27, No. 6, pp. 509

[2] R. E. Bryant: “Graph-Based Algorithms for Boolean Function Manipulation”, IEEE Trans. on Computers, Vol. C-35, No. 8, pp. 677-691, (AUgust, 1985).

0.3 0.4 0.7

0.4

Time

40 33 49

97 330

0.3 0.3 0.4 0.6 0.5 18.3 34.1 21.5 11.5

19.8 36 .d 21.d 11.1

46594

52.8 22.3 28.6

119201 39373

51.4

40306

29.8

89338 36862 30543

22.5

C) (B)+-input j rerters (D) (C)+variable shifters of the Inputs

(C)

-I-

A) Using dynamic weigh i B) In the original order

7

48

(“1 #Node

I

41 31 120 248 358 38187 11348 68816

I1t (>5ook) 246937 47990

105200

assignment

0.3 0.3 0.4 0.5 0.4 14.5 7.4

#Node 390

30 452 1700 304 31026 6205 32577

Time

0.4 0.3 0.4

37 1163

0.4 0.6

0.9

94814

24.1

0.5 14.0 5.6 21.0

394 77517

0.5 26.1 278.6 78.0

479711 112815 (>500k) (>500k) 102.9 103301 46.9 373974 179.0 22.7 65895 63.3 47.4 91082 32.5 (>500k) , (>50Ok) method (C) In the origina tl order (reverse) (D) In a random order 39.1

[3] J. C. Madre and J. P. Billon: “Proving Circuit Correctness using Formal Comparison Between Expected and Extracted Behaviour”, Proc. 25th ACM/IEEE DAC, pp. 205-210, (June, 1988). [4] K. Cho and R. E. Bryant: “Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation”, Proc. 26th A CM/IEEE DA C, pp. 418423, (June, 1989). [5] F. Brglez, H. Fujiwara: combinational circuits”,

“A neutral

netlist

of 10

Special Session on ATPG and Fault Simulation, Proc. 1985 IEEE International Symposium Circuit and Systems, Kyoto, Japan, (June, 1985).

“Eval[6] M. Fujita, H. Fujisawa and N. Kawato: uation and Improvements of Boolean Comparison Method Based on Binary Decision Diagrams”, IEEE ICCAD-88 Tech. Papers, pp. 2-5, (November, 1988). [7] S. Malik, A. R. Wang, R. K. Brayton and “Logic Verification using BiA. S. Vimcentelli: nary Decision Diagrams in a Logic Synthesis Environment” IEEE ICCAD-88 Tech. Papers, pp. 6-9, (November, 1988).

Paper 3.3

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