Statistical Power Estimation for IP-Based Design - IEEE Xplore

Statistical Power Estimation for IP-Based Design Yaseer A. Durrani

Teresa Riesgo

Universidad Politécnica de Madrid E.T.S.I. Industriales. División de Ingeniería Electrónica C/ José Gutiérrez Abascal, 2, 28006 SPAIN [email protected]

Universidad Politécnica de Madrid E.T.S.I. Industriales. División de Ingeniería Electrónica C/ José Gutiérrez Abascal, 2, 28006 SPAIN [email protected]

Abstract –In this work, we present a power macromodeling technique for register transfer level model of digital circuits. This technique is applied to the statistical knowledge of the primary inputs/outputs of the intellectual property (IP) components. During power estimation procedure, the sequence of an input stream is generated using input metrics and the macromodel function is used to construct a set of functions that maps the input metrics of a macro-block to its output metrics. Monte Carlo zero delay simulation is performed and power dissipation is predicted by a power macromodel function. In experiments with the IP blocks, the results are effective and highly correlated, with an average error of 1.84%. Our model provides accurate power estimation.

I. INTRODUCTION During the years of inception, the use of integrated circuits (IC) was confined to traditional digital electronic systems such as wearable computers, wireless communication systems. Nowadays not only those devices play an increasingly important role but also the use of integrated systems is much more widespread, from controllers used in home appliances to the automobile industry. The digital electronic circuits are becoming more application specific. The shrinking of devices due to the development of new fabrication technology has increased dramatically the number of transistors available for use in a single chip. The larger capacity of the chips is also being used to extend the functionality of the systems. However, the importance of low power dissipative digital circuits is being increased rapidly. In order to handle the ever increasingly complexity, CAD tools have been developed. Those tools also help minimizing power dissipation of digital devices and accurate power estimation tools are needed at high abstraction levels. In response to this need, power macromodeling technique is a promising solution to the problem of high-level power estimation. The macromodel is to generate a mapping between the power dissipation of a circuit and certain statistics of input signals. This technique has been proven to be effective for individual IP components [1]. The urgent need of a feasible IP power model is becoming more useful in recent years. The application of power macromodeling on IP blocks of the system requires knowledge of the signal statistics among different IP blocks. To obtain this information, the architect must perform different functional simulations. In this paper, we focus on the problem of power estimation at register transfer level (RTL) for IP-based designs. Various power estimation techniques have been introduced previously. These techniques can be divided into two 1-4244-0136-4/06/$20.00 '2006 IEEE

categories: probabilistic and statistical. Probabilistic techniques [2], [3], [4] are about the input stream to estimate internal switching activity of the circuit. These techniques are very efficient, but they cannot accurately capture factors like glitch generation, propagation etc. While in statistical techniques [5], [6], [7] the circuit is simulated under randomly generated input patterns and monitoring the power dissipation using simulator. For accurate power estimation, we need to produce required number of simulated vectors, which are usually high and causes run time problem. To handle this problem, a Monte Carlo simulation technique was presented in [8]. This technique uses input vectors that are randomly generated and the power sample (power dissipation) is computed. Those samples combined with previous power samples are required to determine whether the entire process needs to be repeated in order to satisfy a given criteria. Survey sampling perspective was addressed in [9]. The sequence vectors were provided to estimate power dissipation of a given circuit with certain statistical constraints such as confidence levels and error. This technique divides the vectors sequence into small units, e.g. consecutive vectors, to constitute the population of the survey. The average power was estimated by simulating the circuit by a large number of samples drawn from the population. A look-up table (LUT) based macromodel was presented in [10] and further improved in [11]. The LUT stores the estimates for equi-spaced discrete values of the input signal statistics. The interpolation method was introduced for estimates, if the input statistics do not correspond to LUT. In [12], [13] interpolation scheme was improved by using power sensitivity concept. For better accuracy, numerous power macromodeling techniques [14], [15] have been introduced. In recent work [18], the authors used analytical macromodeling approach without considering temporal correlation Tin. The temporal correlation captures those features that missed by Spatial correlation Sin. In this paper, we present a new power macromodeling technique based on the above methodology with temporal correlation. Our model is LUT based. The input output (I/O) metrics of our macromodel are the average input signal probability Pin, average input transition density Din, input spatial correlation Sin, input temporal correlation Tin, average output signal probability Pout, average output transition density Dout, output spatial correlation Sout and output temporal correlation Tout. Our macromodeling technique achieves good accuracy. We use intellectual property macro-blocks for our experiments.

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The rest of this paper is organized as follows. In Section II we give the background of input parameters of our macromodel. In Section III, we discuss about our macromodel construction. Our macromodel is evaluated in section VI. Section V summarizes our work. II. POWER MACROMODEL CHARACTERIZATION Similar power macromodeling techniques were presented in [13], [14], [15]. Our macromodel consist of a nonlinear function based on LUT approach. This model estimates the average power dissipation:

Pavg = f ( Pin , Din , Sin , Tin )

(1)

The function f is obtained by a given IP macro-block, the components are simulated under different input sample streams with Pin, Din, Sin, Tin. The input metrics of function are the average input signal probability Pin, average input transition density Din, input spatial correlation Sin and input temporal correlation Tin. Given an IP macro-block with the number of primary inputs r and the input binary stream

q ={(q11,q12,...,q1r ),(q21, q22,...,q2r ),... ( q s1 , q s 2 ,..., q sr )} of length s, these metrics are defined as follows [11], [14], [16], [17], [18]:

Pin

∑ ∑ =

s

i=1

j =1 ij

∑ ∑

s −1

j =1

i =1

III. MACROMODEL CONSTRUCTION Several approaches [13], [14], [15] have been proposed to construct power macromodel on ISCAS-85 benchmark circuits. We have observed that the same methodology works as well for IP macro-blocks such as array multipliers, comparators in terms of the statistical knowledge of their primary inputs/outputs. By the following method of [11], we

Input Pattern

qij ⊕ qi +1 j

r × (s − 1) r

r

s

j =1

k =1

i =1

(3)

q ij ⊕ qik

s × r × (r − 1)

∑ ∑

Genetic Algorithms (GAs) [21] have proved success in solving electronic design problems [22], [23] and have shown a high degree of flexibility in handling power constraints [21]. They are more dynamic to combine power of randomness and evolution to analyze large solution space. For this reason, they are more useful with large space related problems, where an exact approach is not applicable. Therefore, GAs are good candidates for solving power estimation problems. Once the I/O metrics are selected, the I/O sequences are computed by our genetic algorithm (GA) method [19], [20]. Monte Carlo zero delay simulation technique is performed and for the IP macro-blocks, the power dissipation is predicted by our macromodel function. The interpolation scheme [11], [12] can be applied (to improve the power sensitivity concept), if the input metrics do not match on their characteristics. The flow of the RTL power estimation is shown in “Fig. 1,”.

(2)

r

∑ ∑ ∑ =

Tin =

(9)

q

r×s

Din =

S in

r

Tout = f D (Pin , Din , Sin , Tin )

r

s − t +1

j =1

t −1

RTL Circuit

(4)

(yj ⊗ qj )

r×s

Power Libraries

(5)

The macromodel function f in (1) can be used to construct to a set of functions f A , f B , f C and f D that maps the input metrics of a macro-block to its output metrics Pout, Dout, Sout, Tout. The output metrics of functions are the average output signal probability Pout, average output transition density Dout, output spatial correlation Sout and output temporal correlation Tout.

Pout = f A ( Pin , Din , Sin , Tin ) Dout = f B (Pin , Din , Sin , Tin ) S out = f C ( Pin , Din , Sin , Tin )

Power Simulator

Operation for generating new patterns

No Convergence ?

Yes

Average Power Estimation

(6) (7)

Fig. 1. The flow of RTL power estimation.

(8)

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found that a good choice of the Pavg in (1), for array multipliers and comparators circuits. In our static power estimation procedure, the sequence of an input stream is generated at the inputs and using simulation, the output stream sequence is extracted by the output waveforms. The power dissipation is predicted using Pavg. All this process we can divide into two steps. In first step, the metrics of the I/O sequences are computed by our GA method [19], [20] and the power dissipation is predicted using Pavg in (1). The interpolation scheme [12], [13] can be applied (to improve power sensitivity concept), if the input metrics do not match based on their characteristics. In second step, Monte Carlo zero delay simulation [8] is performed with different sequences of their signal statistics and evaluate the quality of Pavg. At end we get the power estimation results.

power dissipation and less sensitive than transition density. We have observed that the number of inputs does not influence at the output metrics for comparator-blocks, while for the array multiplier-blocks results are vice versa. In “Fig. 2,” we illustrate the combined scatter plot of intellectual property macro-block between our macromodel and the reference simulated power. Regression analysis is performed to fit the model’s coefficients. For different blocks, we measured prediction correlation coefficient around 97%. TABLE I

ACCURACY OF POWER ESTIMATION

Circuits

IV. MODEL ACCURACY EVALUATION In this section, we show the results of our LUT based power macromodeling approach. We have implemented this approach and built the power macromodel at RTL. The accuracy of the proposed model is evaluated on IP macroblocks. For those blocks, we generated random input vectors for different values of Pin, Din, Sin, Tin and the function f in (1) is used to construct to a set of functions

f A , f B , f C and f D that maps the input metrics of a macroblock to its output metrics Pout, Dout, Sout, Tout. The input sequences we use are highly correlated generated by our new method. The power is estimated using Monte Carlo zero delay simulation technique. The power values predicted by LUT are compared with those from simulations, and average error and maximum errors are computed. Experimental results show that our generated sequences are with accurate statistics and high convergence. For the input metrics, Pin, Din, Sin, Tin we specify the range between [0.1, 0.9]. We generated 550 sequences with 8, 16, 32 bits wide. The sequence length is 2000 and 1000 vectors for macro-blocks.

Average Error

Max Error

Mult8x8-1

0.76%

2.36%

Mult8x8-2

1.53%

3.02%

Mult8x8-3

0.60%

2.99%

Mult4x4-1

0.65%

2.31%

Mult4x4-2

2.15%

3.00%

Mult4x4-3

2.92%

4.70%

Mult4x4-4

0.94%

2.44%

Mult4x4-5

10.07%

11.31%

Mult4x4-6

1.21%

2.83%

Comp-1

1.60%

2.96%

Comp-2

0.29%

1.10%

Comp-3

0.73%

1.57%

Comp-4

0.47%

0.66%

10.6

Pattern Validation and Power Sensitivity

It is evident from the “Table I” that the function is accurate for estimating the average power for array multiplier and comparator circuits. In “Table I” the first column shows the name of the circuits. Columns two and three give the average and maximum relative error for the estimates obtained with our macromodel. Reference values for the circuit’s power dissipation are obtained using time delays from the Synopsys PowerCompiler. In our experiments, the average absolute error is 1.84%, and the average maximum error is 3.17%. The maximum worst-case error is no more than 11.31%. The results show that the transition density is very effective for power dissipation and it is relatively linear to the power. The correlation metrics do not effect significantly

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Pow er from Sim ulation

10.4

A.

10.2 10 9.8 9.6 9.4 9.2 9

9.5 10 Power from Macromodel

10.5

Fig. 2. Power comparison between macromodel

and reference simulated power.

B. 1.35

The minimum simulations length can be determined through convergence analysis. Converging on the average power figure help us to identify the minimum length necessary for each simulation, by considering when the power consumption gets close to a steady value. In our implementation, we start with the quadratic model. The sequences generated by our GA have high convergence and uniformity. “Fig. 3,” plots the variation of the power value with the trial interval length. Figure shows the interval length is 2000 and 1000 for different IP blocks. The warm-up length is about 400, 600, and 800 while the vertical line represents the steady state value at 600, 1200 and 1400 respectively.

Steady State

P o w e r (m W )

1.3 1.25 1.2

1.15 1.1 1.05

100

200

300

400 500 600 700 Interval Length (Clock Cycle)

800

900

V. CONCLUCIONS

1000

10

We have presented a new power macromodeling technique for high-level power estimation. The experimental results show that our power estimation is faster than lowlevel. Our technique was applied on IP macro-blocks using the zero delay model for the given input sequence and has demonstrated good accuracy. Our model showed average error of 1.84% and prediction correlation coefficient of 97%. We are currently evaluating our macromodel on sequential circuits. We are also exploring the accuracy of our macromodel when propagating estimated output statistics through characterized blocks.

9.5

VI. REFERENCES

12 Steady State 11.5

11 P o w e r (m W )

Convergence Analysis

10.5

[1]

9

8.5

200

400

600

800 1000 1200 1400 Interval Length (Clock Cycle)

1600

1800

2000

[2]

52 Steady State

[3]

50

P o w e r (m W )

48 46

[4]

44 42 40

[5]

38 36

200

400

600

800 1000 1200 1400 Interval Length (Clock Cycle)

1600

1800

2000

[6]

Fig. 3. Power changes with respect to sequence length for different IP blocks.

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X. Liu and M. Papaefthymiou, “A static power estimation methodology for IP-based design,” in Proceedings IEEE Conference on Design, Automation, and Test in Europe, 2001. A. A. Ghose, S. Devdas, K. Keutzer and J. White, “Estimation of average switching activity in combinational and sequential circuits,” in Proceedings of the 29th Design Automation Conference , June 1992, pp. 253-259. F. N. Najm, R. Burch, P. Yang, and I. N. Hajj, “Probabilistic simulation for reliability analysis of CMOS circuits,” IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, April 1990, 9(4):439-450. R.Marculescu, D. Marculescu, and M. Pedram, “Logic level power estimation considering spatiotemporal correlations,” in Proceedings of the IEEE International Conference on Computer Aided Design, Nov. 1994 pp. 224-228. G.Y. Yacoub and W.H.Ku, “An accurate simulation technique for short-circuit power dissipation,” in Proceedings of International Symposium on Circuits and Systems, 1989, pp. 1157-1161. C. M. Huizer, "Power dissipation analysis of CMOS VLSI circuits by means of switch-level simulation,” in IEEE European Solid State Circuits Conf., 1990, pp. 61-64.

[7]

[8]

[9]

[10] [11]

[12]

[13] [14] [15]

[16]

[17]

[18]

[19]

[20]

[21]

C. Deng. “Power analysis for CMOS/BiCMOS circuits,” in Proceedings of 1994 International Workshop on Low Power Design, April 1994, pp. 3-8. R. Burch, F. N.Najm, P.Yang, and T.Trick, ”A Monte Carlo approach for power estimation,” in IEEE Transactions on VLSI Systems, March 1993, 1(1):6371. C-S. Ding, C-T.Hsieh, Q. Wu and M. Pedram, “Stratified random sampling for power estimation,” in Proceedings Int’l Conf. on Computer Aided Design, Nov. 1996, pp. 577-582. S. Gupta and F.N. Najm, “Power macromodeling for high level power estimation,” in Proceedings 34th Design Automation Conference, June 1997. S. Gupta and F.N. Najm. “Analytical model for high level power modelling of combinational and sequential circuits,” in Proceeding IEEE Alessandro Volta Workshop on Low Power Design, March 1999. Z. Chen, K. Roy, and T. L. Chou, “Power sensitivity-a new method to estimate power dissipation considering uncertain specifications of primary inputs,” in Proceedings IEEE International Conference on Computer Aided Design, Nov. 1997. Z.Chen and K.Roy, “A power macromodeling technique based on power sensitivity,“ in Proceedings 35th Design Automation Conference, June 1998. S. Gupta and F.N. Najm, “Power Macromodeling for High Level Power Estimation,” in Proceedings IEEE Transactions on VLSI, 1999. X. Liu and M. C. Papaefthymiou, “Incorporation of input glitches into power macromodeling,” in Proceedings IEEE Inter. Symp. On Circuits and Systems, May, 2002. M. Barocci, L. Benini, A. Bogliolo, B. Ricco, and G. De Micheli, “Lookup table power macro-models for behavioural library components,” in Proceedings IEEE Alessandro Volta Workshop on Low Power Design, March 1999. G. Bernacchia and M.C. Papaefthymiou, “Analytical macromodeling for high-level power estimation,” in Proceedings for IEEE International Conference on Computer Aided Design, Nov. 1999. X. Liu and M.C. Papaefthymiou, “HyPE: Hybrid power estimation for IP-Based Systems-on-Chip”, in Proceedings for IEEE Trans on CAD of integrated circuits and systems, July 2005, Vol. 24, No.7, pp. 1089-1103. Y. A. Durrani, T. Riesgo, F. Machado, “Power estimation for register transfer level by genetic algorithm”, in Proceedings for International Conference on Informatics in Control Automation and Robotics, August 2006. Y. A. Durrani, T. Riesgo, F. Machado “Statistical power estimation for register transfer level,” In Proceedings for International Conference for Mixed Design of Integrated Circuits and Systems, June 2006, pp. 522-527. L. Davis, “Handbook of Genetic Algorithm”, V. N. Reinhold, New York, 1991.

[22] M. J. O’Dare, T. Arslan, “Generating Test Patterns for VLSI Circuits Using a Genetic Algorithm”, In Proceeding IEE Electronics Letters, May 1994, Vol. 30, 10, pp. 778-779. [23] T. Arslan, D. H. Horrocks, E. Ozdemir, “Structural Cell-Based VLSI Circuit Design Using a Genetic Algorithm”, International Symposium on Circuits and Systems, Atlanta, USA, 1996.

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