System-level ESD Protection Design using On- Wafer ...

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static device information like it is obtained from TLP testing is not sufficient for a reliable ESD protection design. It is essential to add transient device information ...
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System-level ESD Protection Design using OnWafer Characterization and Transient Simulations Mirko Scholz, Shih-Hung Chen, Steven Thijs and Dimitri Linten, Member, IEEE, Geert Hellings, Student Member, IEEE, Gerd Vandersteen, Senior Member, IEEE, Masanori Sawada, Guido Groeseneken, Fellow, IEEE

Abstract - A methodology for the design of circuits reliable to system-level Electrostatic-Discharge (ESD) stress is presented and verified with two case studies. The combination of on-wafer characterization and transient simulations enables the ESD designer to study the behavior of the component-level ESD protection design during system-level ESD stress with and without adding off-chip protection devices. The design of a system-level ESD protection solutions can be verified long before IC packaging and even before the final system is built. Index Terms - ESD, IC reliability, reliability, system analysis and design

I. INTRODUCTION

T

HE application of system-level Electro Static Discharge (ESD) stress to discrete components and integrated circuits (IC) has received a lot of attention during the last years. The Industry Council on ESD target level already published one white paper on the topic [1] and prepares a second one. In the white paper the authors present a common problem for many IC suppliers. They face the difficulty to provide qualified products which are also reliable to systemlevel ESD stress without knowing the final application of their designs. This can lead to ICs which fulfill the component-level ESD robustness requirements, while failing the ESD systemlevel tests which are carried out by the system vendor. Additional design effort for the ESD protection is required to prevent any IC failure during system-level ESD qualification of the application board. Very often costly overdesigned ESD Manuscript received February, 22nd, 2012. M. Scholz is with imec vzw, Kapeldreef 75, 3001 Heverlee, Belgium and Dept. ELEC, Vrije Universitaet Brussel, Belgium; phone: +3216288950, fax: +3216288950; e-mail: [email protected]. S.H. Chen, S. Thijs, D. Linten and G. Hellings are with imec vzw, Heverlee, Belgium G. Vandersteen is with Dept. ELEC, Vrije Universitaet Brussel, Belgium M. Sawada is with HANWA Electronic Co. Ltd, Wakayama, Japan G. Groeseneken is with imec vzw, Heverlee and with Dept. ESAT, KU Leuven, Belgium © 2012 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained by sending a request to [email protected]

protection solutions are implemented to prevent these unwanted failures during system-level ESD testing. To enable the IC manufacturer to predict and validate the ESD performance of their products under system-level stress conditions, the ESD Association (ESDA) has proposed the Human Metal Model (HMM, [2]). In the HMM document the ESDA standards committee presents methods how systemlevel ESD stress should be applied to devices or circuits to obtain comparable results between different measurement setups and different ESD stress sources. Using a HMM tester for the testing of devices or circuits on wafer enables the study of ESD protection solutions under system-level ESD stress conditions already at an early stage during the design phase. In this paper we show that the combination of on-wafer ESD characterization and transient simulations with a SPICE simulator allows the design and verification of ESD protection solutions robust to system-level ESD stress even before IC packaging. Re- and overdesign is minimized or prevented. The IC-level ESD protection designer gets a tool which allows a good estimation of the transient behavior of the designed onchip ESD protection during system-level ESD stress with and without connected off-chip ESD protection devices. The proposed system-level ESD design methodology is introduced in section II. The required measurement setups and the test board are described in section III. The design methodology is discussed and verified with two case studies. Section IV demonstrates the protection against thermal failure whereas the protection against gate oxide failure is presented in section V. The key findings are summarized in the conclusions. II. DESIGN METHODOLOGY In white paper 3 [1] the Industry Council on ESD target levels proposed the System-Efficient ESD Design (SEED) methodology for the design of off-chip ESD protection solutions meeting system-level ESD specifications. The Transmission-Line Pulse (TLP I-V) curves of the on-chip protection and suitable off-chip ESD protection devices are captured and compared. If required additional off-chip devices are added to obtain the desired system-level protection level [3]. In previous work [4, 5] it has been shown that only quasi-

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static device information like it is obtained from TLP testing is not sufficient for a reliable ESD protection design. It is essential to add transient device information to the protection design process. Based on an improved SEED methodology a design flow for the co-design of system-level and component-level ESD protection is proposed. It is based on on-wafer measurements and transient simulations and allows an in-depth understanding of the transient behavior of on-chip and off-chip protection devices. Fig. 1 shows the proposed design flow. First the quasi-static and transient device parameters of the off-chip and on-chip protection devices are captured with HMM testing, TLP and optional very-fast (vf) TLP testing. The HMM failure level is also captured to obtain the robustness of the on-chip ESD protection to system-level ESD stress for later verification of the designed ESD protection solution. The obtained device data is used to build suitable device models for transient simulations. By adding equivalent model for the application board and IC package to the simulation setup the transient behavior of off-chip and on-chip protection devices during system-level ESD stress can be simulated in a realistic environment. Based on these results a protection solution is designed and verified by comparing the simulated current through the on-chip ESD protection device with the component-level ESD protection window and with the current at failure obtained from previous standalone HMM testing. on chip ESD protection

off chip ESD protection

on-wafer HMM testing

TLP/vfTLP, HMM testing

HMM failure current in time

IV curves, Vmax, Imax

transient simulations

III. TEST BOARD AND MEASUREMENT SETUP A. Test board The devices under test (DUT) in this work are measured onwafer. The probe needles and probe holder parasitic are extracted and included in the analysis to determine the influence of the needle parasitic in the setup during ESD stress. The parasitic inductances and resistances are extracted from HMM measurements on short load which is connected to the on-wafer setup as DUT. The required steps and algorithms are described in [6]. To connect off-chip components to the DUT a dedicated double layer test board (Fig. 2) is used. The test board has been manufactured using FR4 as board material. The top layer contains the PCB traces and the footprints for required offchip components. The bottom layer works as ground plane and is connected with plated via to the top layer. To emulate sufficiently a typical application board the board traces are not designed with specific impedances. The board with the offchip protection devices is connected via SMA connectors to the probe needle holder and probe needles to make the electrical connection to the DUT.

TVSx

Rx

Fig. 2: Photo of test board for system-level ESD experiments with off-chip components; TVSx : TVS diode, Rx: serial components, ESD_IN: input for ESD stress, OUTx: output to wafer prober (SMA)

IC package and board model

protection design

design verification

improved as unexpected transient device behavior is already detected during the design phase.

IC-level ESD design window

Fig. 1: Design flow for system-level ESD co-design using on-wafer measurements and transient simulations

The difference of the proposed design flow to the SEED methodology is the addition of transient device characteristic like maximum voltage and current to the design flow and the use of transient simulations. TLP testing is used to extract the quasi-static characteristic of the devices. HMM testing is used to extract transient information and to verify the designed protection solution. The overall protection design process is

B. ESD measurement setup Component-level ESD stress sources are a TLP and very-fast (vf) TLP tester HANWA T-5000 for extracting the I-V curves of the devices and to extract the robustness of gate oxides for different stress durations. Human Body Model (HBM) testing is carried out with an on-wafer HBM tester HANWA HEDW5000M. System-level ESD stress is applied with a HMM tester HANWA HED-W5000M. The HMM tester uses the same discharge circuit like ESD guns and produces stress waveforms according to the IEC6100-4-2 system-level ESD standard [7]. Next to inductive current probes a high impedance passive voltage probe is connected to the DUT in a KELVIN setup to capture the transient behavior of the on-wafer devices during different stress conditions and with different off-chip configurations (Fig. 3).

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3 about two times larger than the one of the TVS diode. Clamp 3 has the smallest on-resistance which is only about half of the one of the TVS diode.

IDUT

IHMM

HMM tester DUT

V VDUT

on wafer

test board

Table II: Quasi-static device parameter obtained with TLP testing (pulse width: 100 ns, rise time: 200 ps) Device

VT1 (V)

VH (V)

RON (Ω)

IT2 (A)

Fig. 3: Principle schematic of measurement setup with test board and device under test (DUT) on wafer; IHMM – system-level ESD stress current, IDUT – current through DUT, VDUT – voltage across DUT

Clamp 1

6.6

6.25

1.3

2.7

Clamp 2

5.7

1.6

2.2

2.7

Clamp 3

15.9

1.5

0.5

2.8

In the following sections we will demonstrate the use of the measurement setup and the presented design methodology with two case studies where the on-chip ESD protection devices require additional system-level ESD protection to pass the system-level ESD qualification test in an application board. This is typically the case for external IC pins. These IC pins have a direct contact to the port of a system and therefore require additional off-chip ESD protection if the on-chip ESD protection is not able to withstand system-level ESD stress applied to that pin.

TVS diode

5.5

n.a.

0.9

> 10

EXTERNAL PINS

In the first case study three ESD clamps are compared to select the most suitable device for the protection of an external IC pin. ESD clamp 1 is a grounded-gate NMOS (ggNMOS) device. ESD clamp 2 is a low-voltage trigger silicon-controlled rectifier (LVTSCR). Clamp 3 is an n-type lateral diffused MOS SCR (nLDMOS-SCR). All three devices have very similar component-level ESD robustness (Table I). Clamps 2 and 3 are layout with the same device width and manufactured in similar 90 nm CMOS technologies. The NMOS (clamp 1) is manufactured in an older technology node to achieve comparable ESD robustness. Table I: ESD testing results for the studied ESD clamps; TLP testing rise time: 200 ps HBM

HMM

TLP 100 ns

(kV)

(kV)

(A)

Device

Device type

Clamp 1

ggNMOS

5.8

1.5

2.7

Clamp 2

LVTSCR

5.6

1.7

2.7

Clamp 3

nLDMOS-SCR

5.8

1.8

2.8

A. Device characterization The TLP IV curves of the three ESD clamps are measured onwafer and compared with the I-V curve of a suitable off-chip protection device. The selected TVS diode has a DC breakdown voltage of 5 V, a junction capacitance of 105 pF and an IEC61000-4-2 robustness of ± 30 kV. From the TLP IV curves the quasi-static device parameters of on-chip and offchip protection devices are extracted and compared (Table II). The TLP I-V parameter show that Clamp 2 and 3 snap back to a very low holding voltage during ESD stress. The onresistance of Clamp 2 is the highest of the four devices and

At 5.5 kV the current through clamp 3 causes thermal failure of the device. In contrary HMM stress level above 8 kV can be applied to the clamp 1 and 2 with TVS diode in parallel without observing any device failure. 5 Clamp 1 Clamp 2 Clamp 3

4

Current (A)

IV. CASE 1: SELECTION OF ESD CLAMPS FOR PROTECTION OF

To study the transient behavior HMM testing is carried out until device failure on the three devices with TVS diode in parallel. Fig. 4 shows the maximum current during HMM stress through clamp 1 to 3 with the selected TVS diode in parallel. Clamp 3 turns-on at a stress level of about 1 kV due to its higher trigger voltage VT1. This is indicated by a strong increase of the current through clamp 3. The other two ESD clamps turn on already at low stress level as there trigger voltage is only slightly higher than the trigger voltage of the TVS diode.

3 2 1 0 0

1

2 3 4 5 6 HMM stress-level (kV)

7

8

Fig. 4: Maximum current through nLDMOS SCR and NMOS during HMM stress with TVS diode in parallel; maximum current vs stress level

The different behavior becomes more visible when comparing the current waveforms through the two ESD clamps for the same stress level (Fig. 5). Significant more current flows through clamp 3 in comparison to the other two clamps when the same HMM stress current is applied.

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4 V

4 Clamp 1 Clamp 2 Clamp 3 HMM source

Current (A)

3 2 1 0 0

50

100 Time (ns)

150

200

Fig. 5: Measured current in time through Clamp 1 to 3 with TVS diode in parallel in comparison to applied HMM stress current, HMM stress level: 1 kV

B. Transient Analysis - impact of on-wafer setup The unexpected lower failure level of the nLDMOS-SCR (Clamp 3) during HMM stress is further analyzed. After triggering most of the HMM stress current is conducted by Clamp 3 and not by the TVS diode. One explanation is found when looking at the voltages across the TVS diode during HMM testing of the ESD clamps with TVS diode in parallel. Fig. 6 compares the voltage across the TVS diode during HMM stress depending if clamp 1 or clamp 3 are connected. Clamp 3 triggers and snaps back to its low holding voltage thereby turning off the TVS diode. The moment of TVS turnoff occurs later with increasing HMM stress level. In contrary the TVS diode stays on when clamp 1 is connected. 25

Voltage (V)

15

TVS diode "on"

10

TVS diode "off"

0 100 Time (ns)

VBDTVS < Lsetup

dI Clamp

+ I clamp ( Rsetup + RON ,Clamp ) + Vhold ,Clamp (1) dt where VBDTVS is the TVS diode reverse breakdown voltage, Iclamp the current through the ESD clamp, Lsetup the parasitic inductance of the probe needle holder and probe needle, Rsetup the parasitic resistance of the probe needles, RON,Clamp the onresistance of the ESD clamp and Vhold,Clamp the on-state (holding) voltage of the ESD clamp.

Table III: Summary of the device on-resistances and parasitic impedances (20 ns to 35 ns); Lsetup = 40 nH

5

0

The voltage across the TVS diode during HMM stress is directly related to the parasitic in the setup. Consequently, the voltage across the parasitic and the on-chip device after triggering needs to be larger than the breakdown voltage of the TVS diode to keep it on:

The HMM current (Fig. 5) increases a second time after about 10 ns thereby causing a voltage drop across the parasitic inductance. For the time range from 20 ns to 35 ns and the used wafer prober an additional impedance of 2.7 Ω occurs in series to the on-wafer ESD clamp (Table III).

Clamp 1 Clamp 3

*

20

Fig. 7: Schematic of measurement setup with all parasitic and when the ESD clamp is triggered: Lsetup – inductance probe needle holder and probe needles, Rsetup – resistance probe needles; RON,Clamp – on-resistance ESD clamp; Vhold,Clamp – on-state (holding) voltage ESD clamp, VTVS – voltage across TVS diode, IHMM – ESD stress current, ITVS – current through TVS diode, IClamp – current through ESD clamp

200

Fig. 6: Measured voltage across TVS diode when stressed with the two ESD clamps in parallel; HMM stress level: 2 kV; * moment of TVS turn-off when clamp 3 is connected

When looking at the same voltage waveform for clamp 2 also the TVS diode turns off. However, the moment of TVS turnoff occurs later than when clamp 3 is stressed. Due to the transient nature of the system-level ESD stress current the parasitic of the on-wafer setup components like probe needles and probe needle holder significant contribute when testing devices on wafer together with off-chip components. Consequently the interaction of the TVS diode with the ESD Clamps on wafer is influenced by the setup parasitic. Fig. 7 shows the schematic during HMM stress when ESD Clamps and the TVS diode have triggered.

device

Ron(Ω)

Rprober (Ω)

Zprober (Ω)

Ztotal (Ω)

Clamp 1

1.3

0.8

2.7

4.8

Clamp 2

2.2

0.8

2.7

5.7

Clamp 3

0.5

0.8

2.7

4

TVS diode

0.9

-

-

0.9

The higher holding voltage of Clamp 1 and the parasitic voltage drop of the on-wafer setup keep the TVS diode always on during the HMM stress duration and at all HMM stress level. Consequently the TVS diode shunts more current. In case of clamp 2 the holding voltage is low. However the relatively high on-resistance causes enough voltage drops to keep the TVS diode on. When comparing the three clamps the lowest residual current flows into clamp 2 with connected TVS diode. From the on-wafer measurement results we can conclude that Clamp 1 and 2 are the more suitable ESD clamps for the onchip protection of an external IC pin. A device like clamp 3

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C. Transient simulations Transient simulations are carried out to estimate the clamps behavior during ESD stress and when the clamps are used in an IC package mounted in an application board. With the known parasitic of the measurements setup and using the modeling approach in [5] the behavior of the TVS diode on board and the ESD clamps on wafer are simulated in a SPICE simulator. The TVS diode is modeled with a standard SPICE diode model. The diode reverse breakdown voltage is obtained by using the TLP trigger voltage VT1. The diode series resistance is represented by the TLP on-resistance RON. The voltage overshoot during diode turn-on is modeled by an additional series inductance. This simplification may be used as the TVS diode is unidirectional and only used reversebiased during ESD stress. Therefore forward recovery cannot occur during normal use of the diode. The ggNMOS (Clamp 1) is modeled as a reverse-biased diode with its holding voltage as breakdown voltage and its onresistance as series resistance. The device snapback is neglected. Only the current conduction after device triggering is of interest. The SCR-based ESD clamps 2 and 3 are modeled with a behavioral model which is derived from the SPICE model of a discrete thyristor. It contains device parameters like the dV/dt factor, trigger voltage, holding voltage and holding current. The HMM tester is modeled with the equivalent model in [8].

The parasitic of the DIL package pin are extracted from an IBIS model [9] and implemented in the SPICE simulator (Fig. 9). Next to the IC package also the parasitic inductance of 5 mm board trace is added to include the connection between TVS diode and packaged IC in the simulation. VESD

simulation measurement

Current (A)

1.5

Ltrace

IClamp Lpckg Rpckg Cpckg

TVS

ESD clamp

Fig. 9: Simulation setup with IC package parasitic: IHMM – ESD stress current, ITVS – current through TVS diode, IClamp – current through ESD clamp, Ltrace – board trace inductance, Lpckg – package pin inductance, Rpckg – package pin resistance, Cpckg – package pin capacitance

Fig. 10 shows the simulated voltage and current for clamp 3 and when using the device in a DIL package. Like predicted with the on-wafer measurements the TVS diode turns-off during the HMM stress. The moment of TVS turn off occurs later when the HMM stress level is increased. 30 1 kV HMM 2 kV HMM

25

The described simulation setup is verified by simulating the current through clamp 3 in the on-wafer setup and at the trigger level. The results are compared to measurement data captured with the same condition (Fig. 8). A good agreement between measurement and simulation is obtained. 2

IHMM

ITVS

Voltage (V)

with low holding voltage and low on-resistance should not be used as unexpected failure during the system-level ESD test can occur.

20 15 10 V 5

BD TVS

0 0

50

100 150 Time (ns)

200

250

Fig. 10: Simulated voltage across TVS diode with clamp 3 connected, application case with DIL package; VBDTVS – breakdown voltage of TVS diode

The current through the ESD clamps is simulated with increasing HMM stress level to predict a failure level for the packaged devices with the TVS diode in parallel. Fig. 11 shows the simulated current at failure level in comparison to the measured failure current during standalone HMM testing of the ESD clamps.

1 0.5 0

5 0

50

100 Time (ns)

150

200

Current (A)

With the verified simulation setup the prediction of an application case is carried out. The on-wafer setups parasitic are replaced with the equivalent model of a DIL IC package pin (Table IV).

300

Lpckg (nH) 13.7

2

0 0

Cpckg (pF] 1.75

3

1

Table IV: Parasitic of a DIL IC package pin Rpckg (mΩ)

standalone 1.5 kV simulated, with TVS, 4.5 kV

4

Fig. 8: Current through Clamp 3 (nLDMOS SCR) with TVs diode in parallel: comparison of simulated and measured current; HMM stress level: 1000 V

a)

50

100 Time (ns)

150

200

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6

7

5 Current (A)

where RISO is the isolation resistance, GISO,ONclamp the conductance of the isolation resistor and ESD clamp in onstate, GTVS the conductance of the TVS diode in on-state, Isafe,clamp the safe current level through the ESD clamps and I30ns,HMM,8kV the current after 30 ns at a HMM stress level of 8 kV. With equations (2) and (3) the required isolation resistance value is calculated for all three clamps. Table V shows that the required isolation resistor for the LVTSCR (clamp 2) is the smallest. It is the highest when the nLDMOS SCR (clamp 3) is used as on-chip protection device. Although all three clamps have a similar ESD robustness the nLDMOS SCR is more sensitive to system-level ESD stress when a TVS diode is placed in parallel. This is due its strong snapback and low holding voltage which turns off the TVS diode during HMM stress.

standalone 1.8 kV simulated, with TVS, 5.2 kV

6

4 3 2 1 0 0

50

b)

100 Time (ns)

150

200

8 7

standalone 1.8 kV simulated, with TVS, 2.5 kV

Current (A)

6

Table V: Required isolation resistor and available resistance value in E24 row, comparison for the three on-chip ESD clamps

5 4 3 2 1 0 0

50

c)

100 Time (ns)

150

D. Designing the system-level ESD protection Looking at the current distribution between the TVS diode and the ESD clamps in the application case shows that the onwafer measurements do not predict correctly the failure level. Already at a stress level of about 2.5 kV the current through the clamp 3 reaches a level which causes failure of the device. For comparison the failure level obtained with the on-wafer setup and TVS diode in parallel was 5.5 kV. Also the high robustness of clamp 1 and 2 as predicted with the on-wafer measurements is different when the devices are used in an IC package. This is due to much less impedance of the IC package in comparison to the on-wafer setup. The current into the on-chip protection is limited by adding an isolation resistor [10]. A sufficient ESD protection level also under high system-level ESD stress is obtained. Kirchhoff’s laws are applied to calculate the correct isolation resistance value:

GISO ,ONclamp + GONTVS

RISO =

1 GISO ,ONclamp

I safe ,clamp

(2)

I 30 ns , HMM ,8 kV

− RONclamp

RISO in E24 (Ω)

Clamp 1

3.1

3.3

Clamp 2

2

2

Clamp 3

3.7

3.9

E. Conclusions for component-level ESD design

The difference in failure level is clearly visible. None of the three configurations passes 8 kV HMM stress level. Additional protection measures are required which will be demonstrated in the next paragraph.

=

RISO (Ω)

200

Fig. 11: Measured standalone and simulated failure current when stressed with TVS diode in parallel; Clamp 1 (ggNMOS, a), Clamp 2 (LVTSCR, b) and Clamp 3 (nLDMOS-SCR, c)

GISO ,ONClamp

ESD clamp

(3),

A component-level ESD protection designer designs an ESD clamp with a strong snapback and low on-resistance to limit the voltages across at the protected IC pin at high ESD stress levels. However these rules are not fully correct if an IC pin is connected to a system port and an off-chip ESD protection device is placed in front of it. In that case the use of ESD clamps with a strong snapback during ESD stress should be avoided when designing the on-chip ESD protection of external IC pins. Off-chip protection devices usually have a higher on-resistance than snapback clamps. To limit the current into the on-chip protection also at high system-level ESD stress level a higher on-resistance of the on-chip protection device is beneficial. This goes along with the goal of the Industry Council on ESD target level to lower the component-level protection level [11]. Lower on-chip protection levels allow for example a higher on-resistance of the on-chip protection which is also beneficial to the systemlevel ESD protection design. Higher on-resistance of the onchip protection allows smaller values for the eventually required off-chip current limiting isolation resistor and can even enable designs which do not require additional isolation resistors. In any case during HMM stress the voltage across the on-chip ESD protection with and without off-chip protection device must not exceed a safe value which is given by the componentlevel ESD protection design window. How to define and apply a component-level ESD design window to the system-level ESD protection design process is demonstrated with the second case study in the next section.

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V. CASE 2 – PROTECTION OF EXTERNAL PINS IN ADVANCED CMOS TECHNOLOGIES Recent work has shown that the component-level ESD protection targets also are met with FinFET technologies [12]. They are one of the options for the continuing scaling in advanced CMOS technologies. One of the main difficulties for the ESD protection design in advanced technologies is the usually thin gate oxide (GOX) which significantly shrinks the available ESD design window. However, with gated diodes as ESD protection device a sufficient high ESD protection level can be achieved even when GOX with small effective oxide thicknesses are protected [13]. A. Component-level ESD protection In this case study bulk-FinFET gated diodes are used to protect a gate monitor. The diodes are laid out with one single 80 μm wide fin which has been found as the best configuration [13]. The gate length of the diodes is 70 nm. The gate monitor is a 5 µm x 5 µm NMOS and represents the input gate of e.g. an inverter (Fig. 12). The gate stack consists of 5 nm high-k material. This gives an effective oxide thickness of 1.6 nm. IN

GM

VSS Fig. 12: Diode-based input protection (local clamping) with gate monitor (GM) in parallel

Fig. 13 shows the breakdown voltages of the gate monitor during different vfTLP and TLP stress durations.

5.5

device

4

RON (Ω)

VT1 (V)

2 diode + GM

0.8

1.5

3.0

4.9

TVS diode

1

2

n.a.

n.a.

On-wafer HMM testing on the two diodes with and without connected GM is carried out to test the robustness to systemlevel ESD stress. The HMM failure level decreases significant with GM in parallel indicating a gate oxide failure during system-level ESD stress (Table VI).

IT2 (A)

VT2 (V)

The selected device is a TVS diode with a very low breakdown voltage and a system-level ESD robustness of ± 8 kV IEC61000-4-2. The quasi-static device parameters show that the stress current is almost equally shared due to the similar on-resistance when the HMM stress current is applied to on-chip and off-chip protection and both devices have triggered. B. System-level ESD protection To design a suitable ESD protection against system-level ESD stress a design window is defined based on the componentlevel ESD testing results. It is defined by the GOX breakdown voltage during vfTLP stress minus a safety margin as an upper limit and the operating or signal voltage plus a safety margin as a lower limit. For this case study the design window is defined from 1.5 V to 4.5 V. The maximum currents during HMM stress on the TVS diode are plotted against the maximum voltages in Fig. 14. At low HMM stress level the voltage across the TVS diode exceeds the breakdown voltage of the GOX to be protected and the available design window. V

V

BD,GOX

max,TVS

design window

safe level

10 100 vfTLP/TLP pulse width (ns) Fig. 13: 5 μm x 5 μm NMOS gate oxide breakdown voltages depending on the duration of the applied vfTLP and TLP stress duration; vfTLP/TLP rise time: 200 ps

1.9 0.7

device

25

1

2 diode 2 diode + gate monitor

Table VII: Quasi-static device parameter obtained with TLP testing (pulse width: 100 ns, rise time: 200 ps); TVS diode: Vishay VESD01-02VG08

5 4.5

HMM (kV)

The quasi-static device parameter are extracted from TLP testing results on the two serial diodes and with the GM placed in parallel. The obtained data is compared to an off-chip ESD protection device (Table VII).

max. current (A)

Breakdown Voltage (V)

6

Table VI: Failure level during HMM testing on configuration of two diodes with and without connected gate monitor

20 15 10 5 0

0

10

20 30 40 max. voltage (V)

50

60

Fig. 14: HMM testing of standalone TVS diode (TVS diode: Vishay VESD01-02VG08): maximum current vs. maximum voltage; VBD,GOX – GOX breakdown voltage of gate monitor, Vmax,TVS – maximum voltage at HMM stress level of 8 kV

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Without further improvement of the ESD protection design the gate monitor fails at low HMM stress level. Additional measures are required to limit the current and the voltage in the on-chip ESD protection during system-level ESD stress. The required information is extracted from TLP testing on the two FinFET diodes with gate monitor in parallel. The safe current should be below the TLP failure current IT2. A current of 2.8 A is taken as a safe value. With this value and the I-V curve data in Fig. 14 the value of the current limiting isolation resistor is calculated:

RISO =

Vmax,TVS − VBD ,GOX I safe ,on−chip

(4),

where RISO is the value of the isolation resistor, Vmax,TVS the maximum voltage across the TVS diode at the target protection level, VBD,GOX the GOX breakdown voltage and Isafe,on-chip the safe current through the on-chip protection during ESD stress. With equation (4) an isolation resistance value of 17.3 Ω is obtained when using a safe value for the GOX breakdown voltage of 4.5 V and a safe on-chip current of 2.8 A. A resistance value of 18 Ω is selected from the E24 row of preferred numbers. C. Design verification With the calculated resistance value the designed ESD protection is simulated and verified. The TVS diode is implemented in SPICE using the previously used modeling approach. The on-chip protection is modeled as two diodes in series with the TLP on-resistance as series diode resistance. Gated diodes trigger faster than shallow-trench isolated (STI) diodes [14, 15]. Almost no overshoot occurs during triggering which allows the use of the simplified model in SPICE. The equivalent model of a ball grid array (BGA) package pin is placed between the on-chip protection and TVS diode to include the impact of a high bandwidth IC package in the simulation. Fig. 15 shows the simulated current through the two diodes in series with GM in parallel at an HMM stress level of 8 kV. It is compared to the current obtained from standalone HMM pass-fail testing. 2.5 measured standalone 0.7 kV simul. BGA pckg. and R , 8 kV

Current (A)

2

With the isolation resistor no gate oxide breakdown would occur even at a HMM stress level of 8 kV. Due to the lower ESD robustness of the on-chip protection with GM in parallel the calculated value for the isolation resistor is much higher in comparison to the other case study. A further optimization of the proposed protection design might be required which is out of the scope of this work. VI. CONCLUSIONS AND OUTLOOK With two case studies the methodology of combining on-wafer characterization and transient simulations for the system-level ESD protection design has been introduced and verified. Both the protection against thermal device failure and gate oxide failure during system-level ESD stress are evaluated and verified with application examples. The transient behavior of off-chip and on-chip ESD protection devices needs to be included in the design process to prevent unexpected IC failures during the system-level ESD qualification test of application boards. The presented simulation approach is sufficient for many applications to verify a system-level ESD protection design before IC packaging and before the final system is built. The presented design methodology is a contribution to the on-going discussion which device data should be exchanged between component-level and systemlevel ESD designer to enable the design of systems which are robust to system-level ESD stress. With the two case studies we have shown that the quasi-static device data obtained from TLP I-V curves, transient data like HMM failure current and the vfTLP failure voltages provide the data which is needed for the ESD designer to design robust and effective ESD protection solutions for IC pins subjected to system-level ESD stress in an application board. ACKNOWLEDGMENT The authors want to thank the imec 200 mm and 300 mm pilot line for processing the wafers used in the work. REFERENCES [1]

“White Paper 3 - System Level ESD, Part I”, Industry Council on ESD Target Levels, 2011

[2]

ANSI/ESD SP5.6-2009, standard practice, “Electrostatic Discharge Sensitivity Testing -Human Metal Model (HMM)”, ESD Association, 2009

[3]

D. Johnsson, H. Gossner, “Study of System ESD Codesign of a Realistic Mobile Board”, Proceedings EOS/ESD Symposium, 2011, pp. 359-368

[4]

M. Scholz, S. Thijs, S.-H. Chen, A. Griffoni, G. Vandersteen, D. Linten, M. Sawada, G. Groeseneken, “System-level ESD protection of highvoltage tolerant IC pins – A case study with nLDMOS SCR”, Proceedings of the 21st RCJ Reliability Symposium, 2011, pp. 39-45.

[5]

M. Scholz, S. Thijs, S.-H. Chen, A. Griffoni, D. Linten, M. Sawada, G. Vandersteen, G. Groeseneken,, “System-level ESD protection of highvoltage tolerant IC pins – A case study”, Tagungsband 12. ESD-Forum, 2011, pp. 87- 94.

[6]

M. Scholz, D. Linten, S. Thijs, S. Sangameswaran, M. Sawada, T. Nakaei, T. Hasebe, G. Groeseneken, “ESD on-wafer characterization: Is TLP still the right measurement tool?”, IEEE Transactions on

ISO

1.5 1 0.5 0 0

50

100 Time (ns)

150

Fig. 15: Comparison of simulated current through on-chip ESD protection with GM in parallel (with BGA IC package and isolation resistor of 18 Ω) and measured current through standalone on-chip protection with GM in parallel (on wafer).

TDMR-2012-02-0027

Instrumentation and Measurement, Vol.58, No. 10, 2009, pp. 34183426 [7]

IEC61000-4-2, “Electromagnetic Compatibility (EMC) – Part 4.2: Testing and Measurement Techniques – Electrostatic Discharge Immunity”, IEC, 2008

[8]

M. Scholz, D. Linten, S. Thijs, M. Sawada, T. Nakaei, T. Hasebe, D. Lafonteese, V. Vashchenko, G. Vandersteen, P. Hopper, G. Groeseneken, “On-wafer Human Metal Model measurements for systemlevel ESD analysis”, in Proceedings EOS/ESD Symposium, 2009, pp. 405–413

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IBIS: http://www.eda.org/ibis/

[10] S. Marum, C. Duvvury, J. Park, A. Chadwick, A. Jahanzeb, “Protecting circuits from the transient voltage suppressor's residual pulse during IEC 61000-4-2 stress”, Proc. EOS/ESD Symposium, 2009, pp. 377-386 [11] “White Paper 1 - A Case for Lowering Component Level HBM/MM ESD Specifications and Requirements”, Rev. 3, Industry Council on ESD Target Levels, 2011 [12] S. Thijs, C. Russ, D. Trémouilles, A. Griffoni, D. Linten, M. Scholz, N. Collaert, R. Rooyackers, M. Jurczak, M. Sawada, T. Nakaei, T. Hasebe, C. Duvvury, H. Gossner, G. Groeseneken, “Design Methodology of FinFET Devices that Meet IC-Level HBM ESD Targets”, Proc. EOS/ESD Symposium, 2008, pp. 295-303. [13] S. Thijs, A. Griffoni, D. Linten, S.-H. Chen, T. Hoffmann, G. Groeseneken, “On Gated Diodes for ESD Protection in Bulk FinFET CMOS Technology”, Proc. EOS/ESD Symposium, 2011, pp.27 – 34 [14] M. Scholz, S. Thijs, D. Linten, D. Trémouilles, M. Sawada, T. Nakaei, T. Hasebe, M.I. Natarajan, G. Groeseneken, “Calibrated Wafer-Level HBM Measurements for Quasi-Static and Transient Device Analysis”, Proc. EOS/ESD Symposium, 2007, pp. 89-94.

[15] J.R. Manouvrier, P. Fonteneau, C.-A. Legrand, P. Nouet, F. Azaïs, “Characterization of the Transient Behavior of Gated/STI Diodes and their Associated BJT in the CDM Time Domain”, Proc. EOS/ESD Symposium, 2007, pp.165-174.

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