Verilog `define & `undef. `define DSIZE 8. `define ASIZE 10. `define MDEPTH 1024 module ram1 ( inout [`DSIZE-1:0] da
DAC 2009 SystemVerilog-2009 Presentation by Sunburst Design, Beaverton, Oregon, © 2009
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SystemVerilog Is Getting Even Better! An Update on the Proposed 2009 SystemVerilog Standard Part 1 Presented by
Clifford E. Cummings
Stuart Sutherland
Sunburst Design, Inc.
Sutherland HDL, Inc.
[email protected] www.sunburst-design.com
sponsored by
[email protected] www.sutherland-hdl.com
© 2009, Sunburst Design, Inc.
50+ Major Enhancements in SystemVerilog-2009…
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• Part 1: Q
Cliff Cummings of Sunburst Design presents the details on the major new features in SystemVerilog-2009 that involve hardware models and testbench models Q
www.sunburst-design.com/papers/ DAC2009_SystemVerilog_Update_Part1_SunburstDesign.pdf
• Part 2: Q
Stu Sutherland of Sutherland HDL presents the details on the major new features in SystemVerilog-2009 that involve SystemVerilog Assertions Q
www.sutherland-hdl.com/papers/ DAC2009_SystemVerilog_Update_Part2_SutherlandHDL.pdf
© 2009, Sunburst Design, Inc.
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Cliff Cummings and Sunburst Design • Verilog/SystemVerilog/Synthesis Trainer & Contractor • Accellera & IEEE 1800 SystemVerilog Committees • IEEE 1364 Verilog Standards Groups (VSG) – Chair of the Behavioral Task Force (Enhancements & Synthesis)
• IEEE 1364.1 Verilog Synthesis Interoperability Group • Authored more than 40 technical papers – includes 17 "Best Paper" awards
• Verilog instructor for 17 years
www.sunburst-design.com/papers www.sunburst-design.com/papers
SystemVerilog SystemVerilog instructor instructor
for for 66 years years – Synthesis instructor for 15 years – Provides the absolute best Verilog and SystemVerilog training!
Stu Stu is is aa close close 2nd 2nd !! !!
• Tektronix, FPS, IBM - board, FPGA & ASIC design & Test Lab • MSEE-Oregon State Univ. / BSEE-BYU © 2009, Sunburst Design, Inc.
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Acknowledgement & Disclaimer • Acknowledgements – Our thanks to Shalom Bresticker and Brad Pierce (Emails) (Emails)SystemVerilog SystemVerilog&& Verilog VerilogLRM LRMexpert expert
......both bothcompiled compiledlists lists of ofenhancements enhancements
www.eda.org/sv-bc/hm/8983.html www.eda.org/sv-bc/hm/8983.html
• Disclaimer – Cliff & Stu have made every attempt to show legal SystemVerilog-2009 examples Not Notall allenhanced enhancedfeatures features can canbe betested testedat atthis thistime time No Noguarantees guarantees!!!!
© 2009, Sunburst Design, Inc.
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The SystemVerilog Mantis Database • The Mantis database contains corrections, clarifications & enhancement descriptions for SystemVerilog-2009 Current Currenterrata errata&&proposed proposedenhancements enhancements guest Login: guest Login: Password: Password: guest guest
• www.eda.org/svdb
• Mantis Item numbers are noted on appropriate slides • Mantis items details can be viewed in the Mantis database After After logging logging in in ... ... Enter Enter Issue Issue ## ... ...
... ... then then select select the the Jump Jump button button
890 © 2009, Sunburst Design, Inc.
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Scheduling of New SV Commands Mantis 890 From Fromprevious previous time timeslot slot #1step #1step
Preponed Preponed
Active Active Inactive Inactive
Used Usedfor forsampling sampling&& verifying verifyingDUT DUToutputs outputs
NBA NBA
(testbench (testbenchinputs) inputs)
Regions Regions for for new new SV SV commands commands
New Newevent eventscheduling scheduling (already (alreadyimplemented) implemented)
Active Active region region set set Evaluate Evaluate concurrent concurrent assertions assertions
Observed Observed
Trigger Trigger clocking clocking blocks blocks
Reactive Reactive
Reactive Reactive region region set set
Re-Inactive Re-Inactive Update to IEEE1800-2005 Standard
Region Region for for new new SV SV commands commands
Re-NBA Re-NBA
Postponed Postponed
© 2009, Sunburst Design, Inc.
Execute Execute pass/fail pass/fail assertion assertion code code program program block block code code
To Tonext next time timeslot slot Sunburst
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SystemVerilog-2009 Display Enhancements
© 2009, Sunburst Design, Inc.
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Field Widths in Print Formats Mantis 1175 program print; int a, b; initial repeat (8) begin ...
$display("a=%h end endprogram
Show Show all all leading leading 0's 0's
$display
("a=%h
b=%h", a, b);
randcase 3: a = 2: a = 2: a = 2: a = endcase randcase 1: b = 2: b = 2: b = 1: b = endcase
$display
b=%h" , a, b);
a=000071ec a=00000003 a=00000ed4 a=00008fbb a=00000003 a=000000b1 a=00000010 a=0000097a
b=000000fb b=00000048 b=000000f4 b=00000860 b=0000003a b=00004895 b=0000007c b=000000da
$urandom_range( 5'h10); $urandom_range( 9'h100); $urandom_range(13'h1000); $urandom_range(17'h10000);
$urandom_range( 5'h10); $urandom_range( 9'h100); $urandom_range(13'h1000); $urandom_range(17'h10000); $display
("a=%0h
b=%0h" , a, b);
a=71ec b=fb a=3 b=48 a=ed4 b=f4 a=8fbb b=860 a=3 b=3a a=b1 b=4895 a=10 b=7c a=97a b=da
("a=%4h
Remove Remove leading leading 0's (ragged display) display) 0's (ragged
4-character 4-character field field with with leading leading 0's 0's (orderly (orderly display) display)
b=%4h" , a, b); a=71ec a=0003 a=0ed4 a=8fbb a=0003 a=00b1 a=0010 a=097a
b=00fb b=0048 b=00f4 b=0860 b=003a b=4895 b=007c b=00da
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Print Format Specifier %x Mantis 1749 program print; int a, b;
%x %xisisaasynonym synonymfor for%h %h
initial repeat (8) begin ...
$display("a=%4x
b=%4x", a, b);
end endprogram
a=71ec a=0003 a=0ed4 a=8fbb a=0003 a=00b1 a=0010 a=097a
Same Sameorderly orderlyprintout printout
randcase 3: a = 2: a = 2: a = 2: a = endcase randcase 1: b = 2: b = 2: b = 1: b = endcase
b=00fb b=0048 b=00f4 b=0860 b=003a b=4895 b=007c b=00da
$urandom_range( 5'h10); $urandom_range( 9'h100); $urandom_range(13'h1000); $urandom_range(17'h10000);
$urandom_range( 5'h10); $urandom_range( 9'h100); $urandom_range(13'h1000); $urandom_range(17'h10000);
%x %xisisjust just"syntactic "syntacticsugar" sugar" (C-like (C-like- -not notreally reallyneeded) needed)
© 2009, Sunburst Design, Inc.
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Print Format Specifier %p (%4p) Mantis 331 package complex; typedef struct { logic [7:0] re; logic [7:0] im; } complex_s; ... endpackage
Sized Sizedformat format specifier specifier%4p %4pfor for orderly orderlyprinting printing
import complex::*; module structprint; complex_s a, b, sum; logic clk; initial begin clk
