Ternary Digital System Concepts and Applications AP

SMGr up

Ternary Digital System Concepts and Applications

A P DHANDE  V T INGOLE  V R GHIYE

SMGr up

Title: Ternary Digital System: Concepts and Applications Authors: A P Dhande, V T Ingole, V R Ghiye Published by SM Medical Technologies Private Limited Copyright © 2014 SM Medical Technologies Private Limited All book chapters are Open Access distributed under the Creative Commons Attribution 3.0 license, which allows users to download, copy and build upon published articles even for commercial purposes, as long as the author and publisher are properly credited, which ensures maximum dissemination and a wider impact of the publication. Upon publication of the eBook, authors have the right to republish it, in whole or part, in any publication of which they are the author, and to make other personal use of the work, identifying the original source. Statements and opinions expressed in the book are these of the individual contributors and not necessarily those of the editors or publisher. No responsibility is accepted for the accuracy of information contained in the published chapters. The publisher assumes no responsibility for any damage or injury to persons or property arising out of the use of any materials, instructions, methods or ideas contained in the book. First published October, 2014

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Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

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SMGr up PREFACE

Ternary Digital System: Concepts and Applications: Ternary digital system is commonly known as three valued digital system. Three valued logic is an elementary set of Multiple Valued Logic, which is introduced in the book at the beginning. The book provides a detail overview of every concept required for the design and applications of ternary circuits. It covers the basic concepts for ternary logic fundamentals, ternary logic gates, its logic gate truth tables, Boolean rules for ternary logic up to ternary logic families, function synthesis and minimization techniques and an applications like one trit T-ALU, Two trit T-ALU Slice, Ternary R-S and D memory elements and an analog to ternary converter for DSP application as a fundamental block are developed and simulated using EDA tool. Finally computer simulation using EDA (Electronic Design Automation) tools like Tanner, spice and VHDL is also illustrated. In the first half of 19 th century G. Boolean have proposed the Algebra for two valued (Binary logic) system after that Shanon has expressed the behavior of electrical switches in terms of Boolean algebra and he paved the ramp to an industrial development that is recognized as initiating one of the most revolutionary economic changes ever.

MVL is also known as Multi-Valued, Multiple-Valued or Many-Valued logic. Multi-Value logic is regarded as a switch with more than two states. Such as a 3- value switch with states ‘0’, ‘1’ and ‘2’. Or a 4-value switch with states ‘0’, ‘1’, ‘2’ and ‘3’. In case of 3-Valued logic the term ternary logic is used & term quaternary logic for 4-Valued logic. Alexander (1964) showed that the most efficient radix for implementation of switching systems is the natural base (e ≈2.71828), it seems likely that the best integral radix is 3 rather than 2.It should be noted that this book emphasis on Ternary logic with concepts and applications. The fundamental work on Multiple Valued Logic (MVL) System was done by E L Post in the beginning of 19th centuries and based on that work P C Rosen Bloom modeled the Algebra for MVL is called Post Algebra.


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Chapter 1 gives introduction about fundamental concept of Multi Valued Logic including ternary digital signals, ternary number representation, basic ternary circuits, Boolean algebra for ternary logic. Chapter 2 is a review of mathematical operations of ternary logic system i.e. addition, subtraction, multiplication and division along with an examples.

Chapter 3 covers basic ternary logic families based on MOS and resonant tunneling devices (RTD), Carbon Nano Tubes (CNT) and Quantum Logic (Q-logic) and its simulated parameters like noise margin, power dissipation, fan in and fan out for MOS and Power delay product, Leakage power, Frequency Response, PVT variations, Process variation, Temperature variation for CNT are discussed. Chapter 4 focus on ternary function synthesis and then minimization of ternary logic functions by various mathematical approaches such as minimization by map method, the quine method: adaption to ternary case and scheinman’s binary method: adaption to ternary case.

Chapter 5 and 6 describes the applications of ternary digital systems for combinational and sequential design along with examples like half adder, subtractor, full adder, subtractor, multiplier, comparator,1-trit ALU,2-trits ALU slice etc.

Chapter 7 presents computer aided design of ternary logic gates by using EDA (Electronic Design Automation) tools such as P-spice and Tanner tool.Alsoexisting VLSI technology how it can be used for simulation of ternary circuits are also discussed. It also includes novel technique for minimization of ternary function by map method. In conventional binary (Two valued) logic system, there is a constraint for a system to make a decision about an output in two ways i.e. 0 (True value) or 1 (False value).However this does not holds in practice. There are many circuits whose output is undetermined when both the inputs to the system are same i.e. either 0 or 1.This book provides an alternate solution to the system giving the decision in ‘third’ state thus giving complete solution to the problems. The book is suitable for engineering graduate, particularly for postgraduate students and for the researchers who wants to build their carrier path in the next generation digital system, the three valued digital system.


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SMGr up ABOUT THE AUTHORS DR.A P DHANDE Dr.Ashwini kumar P. Dhande is currently Professor in Electronic and Telecommunication engineering at Pune Institute of Computer Technology, Pune, India. He has over 22 year experience in Industry and Academic Industry. His research works is in Multi Valued Logic and have published over eleven research papers on the same topic in reputed journals and conferences. He also worked as Lecturer at University of KwaZulu Natal, Durban, South Africa in 2008. He has complete his graduation, post-graduation and doctoral study from Amravati University, Maharashtra, India. His research interest and work includes Multi Valued Logic digital system, Microwave engineering and Astronomy and have numerous research papers published in the area.

DR.V T INGOLE

Dr.Vijay T Ingole Received his B.E.(Electrical Engineering) in 1967 and M.Tech. (Integrated Power System) in 1970 from Visvesvaraya National Institute of Technology, Nagpur, Maharashtra formerly known as Visvesvaraya Regional College of Engineering. He received his Ph.D. in CdSe Solid State Devices in 1998 from Amravati University, Maharashtra, India in 1998. He has total 45 years of industrial and academic experience out of which as Chief Design Engineer in Crompton Greaves Ltd. Large Machines R&D for 12 yrs, further as a Principal and Professor for 33 years at Prof. Ram Meghe Institute of Technology & Research, Amravati, Maharashtra, India (PRMITR) and Pune Institute of Computer Technology, Pune, Maharashtra, India. There are 18 patents against his name and has published one book. He is consultant to Industries for 40 years in Electronics, Electrical & Mechanical and senior member of IEEE, FIETE, FIE(I), LM ISTE, LM JEQT, LM JPTA, LM RASI. He has also discovered Paleolithic (10000-15000 BC) Rock Art Paintings in Satpura-Tapti Valley (2006), Madhya Pradesh, India. His research interest includes Electrical Machines, Power System Protection, Solid State Devices, Power Electronics, Mobile Communication, Ternary Logic. and Speech Recognition. He has more than 40 Research Paper Published in International and National Journals. Currently he is Professor Emeritus at PRMITR.

VIKRAM R.GHIYE

Currently pursuing Master of Engineering degree in Electronics and Telecommunication Communication Engineering with Specialization in, Microwave engineering at Pune Institute


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of Computer Technology, Pune, India. He received Diploma in Communication Engineering at Government Polytechnique Amravati in 2008 and Bachelor of Engineering Degree in Electronics and Telecommunication Communication Engineering from Pune.


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SMGr up CONTENTS

Chapter 1: Fundamental Concept of Ternary Logic • Introduction • The Ternary Logic • Ternary Digital Signals • Ternary Number System • Basic Ternary Logic Circuits • Boolean Algebra For Ternary Logic • References Chapter 2: Ternary Arithmetic Operations • Introduction • Ternary Addition • Ternary Subtraction • Ternary Multiplication • Ternary Division • References Chapter 3: Ternary Logic Families • Introduction • Ternary Logic Circuits Based On CMOS • Ternary Logic Circuits Based On RTDS • Ternary Logic Gates Based On Carbon Nano Tube Technology • Ternary Quantum Logic Gates • References Chapter4: Ternary Logic Minimization • Introduction • Standard Representation For Logic Function • Function Minimization. Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

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• • • •

Minimization By Map Method The Quine Method: Adaption To Ternary Case Scheinman’s Binary Method: Adaption To Ternary Case References

Chapter 5: Combinational Logic Design • Introduction • Synthesis, Minimization And Realization Procedure For Ternary Switching Function. • Half Adder Design • Full Adder Design • Half Subtractor • Full Subtractor • Ternary Comparator • Ternary Multiplier • Transmission Gate • Transmission Gate (TG) • Ternary Multiplexer/Demultiplexer • Ternary Arithmetic And Logic Unit (ALU) And Its Extension To Alu Slice • References Chapter 6: Sequential Logic Design • Introduction • One Trit Memory Cell • Clocked R-S And D-Flip Flap Flop • Applications Of Sequential Circuits • References Chapter 7: Cad Tool Simulation Of Basic Ternary Logic Gates And Map Method For Ternary Function Minimization • Introduction • Tanner T-Spice • Electronic Work Bench/Multisim • VHDL • Map Minimization Technique For Ternary Logic System Appendix I: Truth Tables Appendix II: Electronic Circuits Appendix III: VHDL Code Appendix IV: Opportunities For Research in MVL. Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

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SMGr up

CHAPTER 1

Fundamental Concept of Ternary Logic INTRODUCTION The fundament of today’s digital technology age is binary logic. The time when Shannon expressed the behavior of electrical switches in Boolean algebra, he overlay the ramp to an industrial development which is recognized as beginning of one of the most revolutionary economic changes ever.

Binary logic technology has come across the dramatic changes and advances. Earlier from electro-mechanical to electronic switches by using electronic tubes (1919) like triode, pentodes, then from tubes to transistors (1948) and from transistors to LSI (1958) and VLSI (1970)circuits. Although efficient and powerful, binary logic is not the most efficient & powerful switching logic. Non-binary logic or Multiple Valued Logic (radix>2) has been around for quite a while and is known as Multi-Valued Logic or Many Valued Logic. In this book it will be referred to as MVL hereafter. The subject of MVL is also known as Multi-Valued, Multiple-Valued or Many-Valued logic. In case of 3-Valued logic (radix = 3) the term ‘Ternary’ logic is used & term ‘Quaternary’ logic (radix = 4) for 4-Valued logic and so on up to ‘n’ values. Multi-Value logic is regarded as a switch with more than two states. Such as a 3- value switch with logic states ‘0’, ‘1’ and ‘2’, 4-value switch with logic states ‘0’, ‘1’, ‘2’ and ‘3’ and so on up to ‘n’ values.

MVL has been the topic of most interest of many researchers over the last 50 years. From 1971 there has been an annual symposium devoted exclusively to the object. Moreover, a large number of technical papers have published together with numerous survey articles. Much of the ancient work is purely theoretical nature concerned with the completeness of the function with sets of operator, function minimization and similar problems from the switching theory and logic design. Work on hardware implementation of multiple value devices has been more recent. The use of Multi-Valued logic ranges from various applications to VLSI technology and design techniques. There are three directions for the work in MVL. Due to pressure to reduce interconnection complexity and reduce chip area on VLSI, it is giving motivation for the investigation of many different hardware implementations of MVL systems. The largest commercial use of MultipleValued logic is in the area of MVL memories. The MVL can be used to overcome existing difficulties


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in the analysis of problems in binary digital systems, such as the design of fault simulators. Finally there is still ongoing work in the general area of switching theory to yield the best methodologies for the implementation of multi-valued systems.

There are two modes of operation in MVL. Those are voltage mode operation and current mode operation Figure 1.1 shows operation modes of MVL. In voltage mode operation, logic state is specified in terms of distinct voltage levels i.e v1v2…vn and in current mode logic, state is multiple of lowest logic current level state i.e. Logic state for current mode is xI1, xI 2…….. xI n , where x is reference current.

Figure 1.1: MVL operating modes.

Where, 1,-1, 0 and 2 …n are the logic levels for operation in voltage mode and xI1, xI 2…….. xI nfor , current mode. The figure 1.2 is a representation for Ternary logic. Modern technical work have shown advantages of using Multi-Valued logic where the natural question is whether there exists a practical radix other than 2 that would produce circuits with greater saving in components, without loss of speed? Answer to this is ‘Yes’ and it is Multi Valued Logic.

THE TERNARY LOGIC

In existing binary digital system, the output of the system is decided by considering two input conditions i.e. either ON (Favorable or true logical level 1) or OFF (unfavorable or false logic at logic level 0) leaving behind the third conditions i.e. when both the input conditions are same, here decision is consider as don’t care or it is discarded by the system. Such situation generally occurs in sequential circuit design. Consider a digital system where both the inputs are same i.e. either 00 or 11as shown in figure 1.2 Hear in binary system output will be uncertain or will be same as that of previous state of the system but in practice, system must give the output that will satisfy both the input conditions mentioned above. It is shown in figure 1.2 here the system gives the output which is balanced and this state is regarded as third state i.e. can’t say or can’t make any decision. So to make third decision the radix of the system must be greater than 2. Here the third logic level is introduced whose system radix is greater than 2.


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Alexander [1964] showed that natural base (e ≈ 2.71828) is the most efficient radix for implementation of switching circuits. It seems that most efficient radix for the implementation of digital system is 3 than 2. Ternary logic system, meaning that it has 3 valued switching. Ternary system has several important merits over binary. It can be listed as reductions in the interconnections require to implement logic functions, thereby reducing chip area, more information can be transmitted over a given set of lines, lesser memory requirement for a given data length. Besides this serial & some serial-parallel operations can be carried out at higher speed [1-3]. Its advantages have been confirmed in the application like memories, communications and digital signal processing etc [4].

Russian first ternary computer “SETUN” and “SETUN 70” was developed at Moscow state university in 1960.It was found that ternary computer is very favorable for seizing of application simplicity of programming in codes, other than permitted to design a few interpreter. Few of the example of implementation of ternary logic systems are three value counter which greatly simplifies the counter circuitry based on two value logic, Three valued memory based on multi valued logic can considerably reduce the memory size required to store than it requires by using two value logic, the implementation of cyclic convolution where significant advantage can be gained by using ternary digital hardware namely an increased maximum sequence length and can be achieved without increasing the complexity of digital hardware. The current mode CMOS circuits have application in digital signal processing and computing. The three value logic offers particular advantages in digital signal processing applications (Convolution, FFT) etc. For example, an increased maximum sequence of length can be achieved by implementing ternary logic system in DSP.

A) Favorable decision B) Unfavorable decision c) Don’t care Figure 1.2: Binary decision making.

A) Favorable decision B) Unfavorable decision C) Can’t make any decision Leaning towards right leaning towards left Balance condition Figure 1.3: Natural decision making.


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There are several advantages using ternary logic digital system which can be summarized as follows.

Number Representation

For representing decimal number 16 in binary, 5 bits are required (10000) whereas for representing same number in ternary require 3 bits (121). Similarly, signed number representation in binary ranges from -2 n-1 to 2 n-1 -1 for negative & positive numbers. In ternary same range spans from -3n-1 to 3n-1 -1. Thus number representation in ternary facilities to develop algorithm for arithmetic operations for high speed and/or area efficient computation.

Processors

If the case of binary 8-bit microprocessor is considered, it has 28 = 256 instructions but same ternary processor will have 38 = 6561 instructions. It means that increasing radix of the system can increase processing capacity of the processor or to have 256 instructions in ternary processor, only 5 bits are required. Thus it reduces design complexity, number of interconnections & power consumption of the system. No ternary processor has been reported till date.

Communication

In communication based on ternary digital system, a minimum of 3 digits is required to code ten decimal digits. The possible states of three variables in 3-valued system results in 27! / (2710)! ≈ 3.1x 1012 ternary coded decimal. Not all of these codes are fundamentally different. Some exhibits useful properties for coded arithmetic, encoding techniques, error detection etc.

Converters

In case of digital converters, for e.g. 8 bit binary ADC has 28 = 256 values for representing analog signal whereas same ternary 8 bit ADC has 38 = 6561 discrete values for same analog signal. It leads to accurate & efficient processing of digital signal.

Memory

As mentioned above, number of bits required to code a decimal number in binary is more than ternary, ultimately memory required to store the coded decimal in ternary is lesser than binary which has advantages like cost/bit ratio reduction, reduced access time & increased storage capacity.

TERNARY DIGITAL SIGNALS

As mentioned in the introductory part, there are two modes of operation in ternary system. Those are voltage mode operation and current mode operation. In voltage mode operation, logic state is specified in terms of distinct voltage levels i.e. v1v2…vn And in current mode logic state is multiple of lowest logic current level state i.e. Logic state for current mode is xI1, xI 2…….. xI n , where x is reference current.


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Voltage mode operation is further classified in to balance and unbalance voltage mode operation depending on supply voltage to logic circuit. In balance logic for voltage mode operation, the signal level takes the value as –v (-v i.e. lowest logic 0 = vL), ground (0v i.e. intermediate logic 1 = vI) and +v (+v i.e. highest logic 2 = VH) whereas in unbalance condition the voltage levels are ground (0vlogic 0vL), v/2 (intermediate logic 1 = vI) and v (highest logic 2 = VH) In figure 1.4 (a) shows unbalance signal and figure 1.4 (b) shows balance signal. In each of two signals we observe that the voltage corresponding to given level; is not fixed, rather voltage in a limited range are designated as level. As long as a voltage belong to a level will be taken as level and exact value of the voltage is immaterial.

Figure 1.4: logic levels in Ternary system.

(a)When supply voltage is o to +v volt: Unbalance system (b) When supply voltage is –v to +v volt: Balance system.

In current mode of operation for balance system current will be either sink, source or will be idle or very small current flows through circuit and for unbalance the current level is multiple of lowest reference current level. The waveforms are same as in figure 1.4 except voltage term will be replace by current term.

TERNARY NUMBER SYSTEM

A digital system represents information with discrete symbols rather than with continuously carrying quantity as in an analog system. Digital binary systems use just two symbols, 0 and 1. To represent all information leavening aside for the moment the problem of circuit realization, one may ask whether the binary number representation is an optimum choice?. The real world is not binary. It is more intuitive to reason about a system, especially at higher levels of abstractions, in terms of variables with symbolic values. In man y practical engineering situations, a device can be not only in ”off” or ”on” state, but also in ”idle” state. When arithmetic operations are involved, computing in a decimal system would match best our experience.

For representing decimal number 16 in binary, 5 bits are required (10000) whereas for representing same number in ternary require 3 bits (121). Similarly, signed number representation in binary ranges from -2n-1 to 2n-1 -1 for negative and positive numbers. In ternary same range spans from -3n-1 to 3n-1 -1.Thus number representation in ternary facilates to develop algorithm for arithmetic operations for high speed and/or area efficient computation.


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Number Representation There are two major conventions for labeling values in a multiple-valued logic system over a set of m values. The most common is 0, 1, 2…, m-2,m-1,extending binary notation in one direction only. It is called unbalanced (or unsigned, or positive). The second one requires an odd m = 2 r + 1. It extends binary notation in both directions as –r,1-r….,-1,0,1…r-1,r. It is called balanced (or Signed). A string of digits (an-1… a0) over a set of m values represents the number an-1 m n-1 + an-2 m n-2 + …a0

For example, in the binary case of m = 2, ai ∈ {0.1}, in the ternary case m = 3, ai ∈ {0,1, 2} for the unbalanced system, and ai ∈ {-1,0,1} for the balanced system. One concern in binary number representation is the treatment of the –ve numbers. There are three common techniques: (1) sign-magnitude, where a sign is explicitly attached to the front of the string of digits;

(2)1’s complement, where the representation for a negative number is obtained by subtracting each digit from 1; (3) 2’s complement, where the representation for a negative number is obtained as in (2) but with a final addition of 1 to the number.

There are disadvantages of all three of these techniques. Both (1) and (2) have two representations for 0 (-0 and +0), while (3) permits the representation of one more negative number than positive. Alternatively, in a balanced system over a set of m values, all the numbers can be represented without using an explicit sign. The sign of a number is the sign of the most significant non-zero digit. Furthermore, in a ternary system, the negative of a number can be found by interchanging 1 and -1 throughout, leaving all zeros unchanged. Hence, addition and subtraction can be performed with the same hardware by sign changes of the addend and subtrahend, respectively, as required. One other advantage of a balanced system is that the procedure of rounding a number is identical to truncation. In a binary system it is not possible, because there is no way for negative correction being applied by digits of lower significance. Therefore, the correct value of the number must be approached from lower digits. Another concern in binary number representation is that in performing addition (or subtraction), the sum bits depend on the carry form lower bits. Two alternative multiple-valued number systems have been extensively studied in order to reduce or eliminate the ripple through carries. The first one is residue number system, in which there are no carries between bits. In such a representation, operations occur at each digit independently of the other digits, resulting in fast arithmetic operations [5,6]. A disadvantage is that the size of the digits may vary, and thus different circuit designs might be needed for different digits. The second number representation which has potential performance attractions is a number


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system with redundancy. In such a system, all numbers except 0 are not uniquely represented by

a string of digits. Instead, two or more representations for a given number are available. The most significant digit does not depend on the least significant bit. The carry into a digit is computed

only from (at most) the next two lower digits, but no other, enabling fast arithmetic operations.

Multiple-valued arithmetic in redundant balanced number system [1,7] as well as in redundant unbalanced number system [8,9] has been presented.

Some other number representations which have potential advantages over binary have

been studied, including overlap resolution number system based on signed continuous valued digits, allowing to perform arithmetic operations by analog digit manipulation circuitry [10] and redundant complex number system [5], allowing to perform addition and multiplication of complex numbers without treating real part and imaginary part separately as well as enabling carry-free addition and binary-tree multiple-operand addition.

Sign magnitude representation of ternary number system In decimal number system a plus (+) sign is use to denote a positive number and minus (-) sing

for negative number. The plus sign is usually dropped, and absence of any sign means that number

is positive value. This representation of number is known as sign number. As is ternary circuits there are two configurations i.e. balance and unbalance ternary systems. In unbalance ternary system, the positive number representation is same as that of binary system where as negative numbers are represents in its 1’s and 3’ compliment form. The example below represents the number representation in ternary system.

Suppose decimal number 64 is to be represented in its positive and negative form.

So positive (64)10 is to be represent in unbalance ternary form it will be (02101)3 hear the

left most 0 (MSB) indicates that number is positive. On other hand in the negative signed ternary (64)10 represents as (20122)3 considering 3’copliment of 64.

Similarly decimal (+48)10 can be represent as (01210)3 and its negative (-48)10 as (21021)3.

1’ Compliment representation

In a ternary number if each 2 is replace by 0 and each 0 by 2 by keeping 1 as is the resulting

number is known as the 1’s compliment of given number. For example (52)10 is represented as

1221 and its 1’s compliment is represented as 1001.

3’ Compliment representation

If 1 is added to 1’s compliment of a ternary number the resultant number is known as 3’s

compliment of ternary number. For example 3’ compliment of 2102 will be 0121. For n trit

number the maximum positive number which can be represent in 3’s compliment form is (3 n-1-1)

and the maximum negative number in 3’s compliment form is -3 n-1.


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FLOATING POINT REPRESENTATION OF TERNARY NUMBER Floating point representation in ternary is same as that of binary except one tryte (groop of 9 trits) is use to represent exponent and two trits for mantissa for 27 trit word which is composed of three trytes.The maximum exponent value, heptavintimal (base 27) ZZZ, is set aside to encode values that are “not a number” or NAN. Aside from the representations reserved for undefined and infinite values, other NAN values have no predefined meaning. In general conventions for floating point representation is [S] M E where S is sign of a number is mantissa and E is in an exponent. Sign

Mantissa (9 trits)

Exponent(18 trits)

27-trits representation for ternary number

Balanced ternary is a natural choice for both exponent and mantissa. As there is no concept of a sign trit in balanced ternary, we cannot follow the almost-universal convention used on binary system of separating the sign bit from the rest of the mantissa.

The mantissa is represented as a pure fraction strictly less than +1.0 and strictly greater than –1.0; there is no hidden bit, so the point is immediately to the left of the most significant trit of the mantissa. The lack of a hidden bit allows non-normalized values with any exponent, but all arithmetic operations on floating point values should return normalized results. Thus, when the exponent is greater than --------- (9 values = heptavintimal 000), the most significant trit of the mantissa should be nonzero. For normalized numbers, therefore, the absolute value of the mantissa is greater than or equal to 1/3.[26]. ternary

heptavintimal

meaning

+++++++++

++++++++++++++++++

ZZZ ZZZZZZ

positive infinity

+++++++++

000000000000000000

ZZZ DDDDDD

undefined

+++++++++

++++++++++++++++++

ZZZ 000000

negative infinity

---------

000000000000000000

000 DDDDDD

zero


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BASIC TERNARY LOGIC CIRCUITS In the digital systems there are few basic operations performed irrespective of complexity of system. These operations may be required to perform a number of times in a large digital system like computer or any digital control system etc. These basic operations are AND, OR, NOT and flip flop. In ternary logic system, these operations are carried out by ternary gate (T-Logic gate) which is labeled as T-AND, T-OR, T-NOT and Flip-Flap-Flop. In recent days T-gates are implemented by using switching elements like CMOS, Resonant tunneling Diodes (RTD) and Carbon Nano Tubes (CNT). Device implementation is considered in chapter 3.

The Ternary Inverter

Ternary inverter is a circuit that gives the output in inverted form of input. Three types of inverter operations are possible in ternary logic. These are STI (simple ternary inverter) PTI (positive ternary inverter) & NTI (Negative ternary inverter) such that, STI ≡ X i = 2 − x

1 if X ≠ i PTI , NTI ≡ Xi =  i if X = i

Where i take the value of 2 for PTI & 0 for NTI inverter.

(1)

Symbols for PTI STI of NTI are shown in Figure 1.5

Figure 1.5 Symbols for Inverters (a) STI (b) PTI (c) NTI.

The symbols ‘∙’, ‘+’, and ‘-’ are used to represent simple, positive and negative logic ternary inverters. Device level construction, operation and truth tables for each type of inverters illustrated in chapter 3.

Ternary OR/NOR Logic Gate

In general OR operation is defined as x’s inputs.

( y ) = max( x1, x 2… xn) i.e. where y is an output and

Ternary OR is a circuit that have X1---Xn as input & Yo as output such that

T − OR = Y0 = X1 + X2 − − − − + Xn = Max[X1, X2 − − − Xn]

(2)

T − NOR = Y0 = X1 + X2 + − − −Xn = Max [X1, X2 − − − Xn]

(3)

& Ternary NOR has an output that is compliment as OR function i.e. The sign ‘+’ indicates logical ternary OR logic operation.

Depending upon the type of inverter used, the logic functions T-OR/NOR can be Simple ternary OR/NOR [ST-OR/NOR], Positive ternary OR/NOR [PT-OR/NOR], Negative ternary OR/NOR [NTOR.NOR]


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Figure 1.6: Shows Symbols for T-OR/NOR logic gates (a) ST-OR (b) PT-OR (c) NT-OR (d) ST-

NOR (e) PT-NOR (f) NT-NOR

Figure 1.6 is a representation of symbols for T-OR/NOR operation. The device level

construction, operation and truth table for each type of OR/NOR logic gate is covered in chapter 3.

Ternary AND/NAND Logic Gate i.e.

AND operation is defined as (y) = min(x1, x2...xn) i.e. where y is an output and x’s are inputs

T − AND = Y0 = X1.X2 − − − − − Xn = Min[x1x2xn] T − NAND = Y0 = X1.X2 − −Xn = Min[x1x2xn]

PT-AND/NAND& NT-AND/NAND are constructed by using PTI & NTI

(4) (5)

Figure 1.7: Shows symbols for T-AND/ NAND logic gate. (a) ST-AND ([b) PT-AND (c) NTAND

(d) T-AND (e) PT-NAND (f) NT-NAND.

Where Y = output of T-Logic AND/NAND gate and X = output of T-Logic AND/NAND gate.

Figure 1.7 is a representation of symbols for T-AND/NAND gates. The device level construction,

operation and truth table for each type of AND/NAND logic gate is covered in chapter 3.

Ternary EX-OR/EX-NOR

Ternary Ex-OR is ternary addition neglecting carry. It is defined as

T - EX - OR = X1 ⊕ X2

T - EX - NOR = X1 ⊕ X2 Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

(6) (7) 10

Figure 1.8 shows symbol for T-EX-OR/NOR logic gates.

Figure 1.8 Symbol for T-Ex-OR/ Ex-NOR gate. (a) T- Ex-OR (b) T-Ex-NOR

Chapter 3 covers construction, operation and truth table for each type of OR/NOR logic gate.

BOOLEAN ALGEBRA FOR TERNARY LOGIC

Algebra proposed by George Boole is also valid for ternary logic system with some additional rules for ternary. The complete theorem and proofs for algebra are given below.

Let the three voltage levels of ternary logic circuits be represented by 0, 1 and 2. The 0 represents the low, 1 the intermediate and 2 the high level. Let L = {0,1, 2} . In L a set of operators are defined. For x, y, z ∈ L there exists an equivalence (=) operation, that is:

x=x

If x = y , then y = x

If x = y and y = z , then x = z

The simple ternary inverter (STI), positive ternary inverter (PTI), negative ternary inverter (NTI), forward diode (FD) and reverse diode (RD) are considered as basic unary operators. These are represented by equations (1)-(3),

STI ≡ x i = 2 − x

1 if X ≠ i PTI , NTI ≡ X i =  i if X = i

(8)

(9)

Where, i take the value of 2 for PTI and 0 for the NTI operator. The minus sign in equations (1) and (2) represents arithmetic subtraction.

1ifx ≠ i FD, RD ≡ x ki =  (10) iifx = i

Where i can be 2 or 0, k2 represents the FD operator (¬), and k0 the RD operator( ¯ ).The operation of addition (+) and multiplication (.) on L, which can be called ternary OR(TOR) and ternary AND(TAND) respectively, represent two multiple input operators. These are given in following equations:


11

TOR ≡ x + y = MAX ( x, y ) TAND ≡ x ⋅ y = MIN ( x, y )

(11)

(12)

The two-element operations obey the idempotent, commutative, associative, distributive and absorption laws. It is evident that laws of the identity elements hold also here.

x + 0 = x

(14)

x + 2 = 2

(16)

x ⋅ 2 = x

x ⋅ 0 = 0

(15) (17)

Theorem: DeMorgan’s Theorem holds for ternary logic when the three types of inverters are used:

( x + y )0 = x 0 ⋅ y 0 ( x ⋅ y )0 = x 0 + y 0 ( x + y ) = x ⋅ y ( x ⋅ y )1 = x1 + y1 1

1

1

( x + y ) = x ⋅ y ( x·y ) 2 = x 2 + y 2 2

2

2

(18) (19) (20) (21) (22) (23)

All theorems, laws and relationships presented in this book have been proven in reference [5].

The theorems and laws presented above are nearly the same as those of the Boolean algebra with a little generalization. But there will be some differences due to the existence of three types of complements in the algebra presented here. This is shown clearly in the following theorems. For any x, y, z L , the following theorems hold:

(24)

x ⋅ x 0 = 0

(25)

 

(26)

(27)

x + x2 = 2 



x ⋅ y ) +  x ⋅ y2  = x (  

  x + y ) ⋅  x + y0  = x (     Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

12

 2  x +  x ⋅ y  = x + y  

 0  x ⋅ x + y   = x ⋅ y   

( z ⋅ x ) + ( z ⋅ x2 ⋅ y) = ( z ⋅ x ) + ( z ⋅ y)

  0

( z + x ) ⋅  z + x

+ y  = ( z + x ) ⋅ ( z + y)      ( x ⋅ y ) +  x 2 ⋅ z  + ( y ⋅ z ) = ( x ⋅ y ) + ( x 2 ⋅ z )  

  ( x + y ) ⋅  x 0 + z  ⋅ ( y + z ) = ( x + y ) ⋅ ( x 0 + z )  

(28) (29) (30) (31) (32) (33)

There is a set of relationships which interrelate any inverter with the two others. These can be expressed by the following equations:

x 0 + x1 + x 2 = x 2

x 0 ⋅ x1 ⋅ x 2 = x 0

x 0 + x1 = x1 x 0 ⋅ x1 = x 0

x 2 + x1 = x 2

x 2 + x1 = x1 1

(34)

(35) (36) (37) (38) (39)

x1 = xx1

(40)

i 0 0

(41)

i

x

=x


13

i i 2 2

x

=x

Where i = 0, 1, or 2.

(42)

2 1 1 0 x = x (43)

0 1 1 2

x =x

(44)

(45)

(46)

0 1 2

x2 = x2 = x2

0 1 2 0 0 0

x

=x =x i

x0 + x0 = 2 (47) i 0 0 x ⋅ x =0 (48) i 2 2 x +x =2 (49)

i (50)

x2 ⋅ x2 = 0 Where i = 0, 1, or 2.

For any x, y L there is also a set of relationships governing the manipulations of the FD and RD operators:

x ¬ = x + 1

( X 1 )¬ = ( X 0 )¬

(51)

(52)

(53)

(54)

(55) (56)


14

( X ¬ ) 2 = x 2

(57)

(59)

¬ 0

( X ) = 0 ( x + y )¬ = X ¬ + Y ¬ ¬

¬

¬

( x ⋅ y ) = X ⋅ Y ( x + y )¬ = X ¬ + Y ¬

(58) (60) (61) (62) (63)

(64)

Ternary functions of one or more variables may be represented in truth table or map form or algebraically in canonical form as a product of sums or sum of products.

Ternary Theorem

Any ternary function f ( x1 , x2 , …, xn ) may be generated from the unary functions x , x , x , x ¬ and 0

1

2

x1 , x2 , …, xn by means of +,,

It has been proven by Halpern and Yoeli [6] that an algebra composed of the MAX, the MIN and 1 three unary operators x, x10 , and x with the constant 1 is a functionally complete system. Since the set of operators presented here are equivalent to those of the algebra to Halpern and Yoeli except the constant 1which is to be substituted by the FD and RD operators depending on the relationships given by equations (51) and (52), therefore the above theorem holds. Moreover it has been shown in reference [8] how these ternary operators realize algebras due to Post, Rosser and Terquette [11], Yeoli and Rosenfeld, Vacca [12] and Mine et al. [10,13], which have been all proven to be functionally complete. Any ternary function of n variables can be represented by:

f ( x1 , x2 , …, xn ) = 2 ⋅ F2 ( x1 , x2 , …, xn ) + 1 ⋅ F1 ( x1 , x2 , …, xn ) + 0 ⋅ ( x1 , x2 , …, xn ) i.e., f = 2 ⋅ F2 + 1 ⋅ F1 + 0 ⋅ F0

(65)

Where Fk equals 2 when the value of the function f equals k, otherwise, it will equal 0.

(66)

Applying equations (15) and (17) to the above equation, the function may be represented by:

f = F2 + 1 ⋅ F1

(67)

 f = F2 + F 1

(68)

And with the aid of the relationship given in equation (52) the function f can be directly represented by: Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

15

Methods for minimization of ternary switching functions, previously described by several authors [1,7] and [14,15], can be applied to the algebra presented here. Most of these methods were applied to algebras composed of the MAX and MIN operations unary functions defined: 0 if x ≠ i

x = 2 if x ≠ i i



Where i can be 0, 1 or 2.

(69)

To be able to apply these methods the following transformations have to be made.

x 0 = x 0

x = ( x + x ) 1

1 2

x2 = x2

2

(70) (71) (72)

Verification for these transformations as well as other methods of minimization is described in reference [5].

References 1.

Porat DI. Three-valued Digital Systems. Proc. IEE. 1969; 116: 947-954.

3.

Balla PC, Antoniou A. low power dissipation MOS ternary logic family. IEEE journal on solid state circuits. 1984; 19: 739-749.

2.

4. 5. 6. 7. 8. 9.

10.

Smith KC. The prospects of multivalued logic technology & application view. IEEE transaction on computer. 1981; 30: 619-627. Chung-Yu-Wu. Design& application of pipelined dynamic CMOS ternary logic & simple ternary differential logic” IEEE journal on solid state circuits. 1993; 28: 895-906. Mouftah HT. Three-valued logic and its implementation with COS/MOS integrated circuits [dissertation]. Laval University, Canada. 1975. Halpern I, Yoeli M. Ternary Arithmetic Unit. Proc. IEE. 1968; 115: 1385-1388.

Yoeli M, Rosenfeld G. Logical Design of Ternary Switching Circuits. IEEE Trans. Elect. Comp.1965; 14: 19-29.

Mouftah HT, Jordan IB. Integrated Circuits for Ternary Logic. Proceedings of the 1974 Inter. 1974; 285-302.

Mouftah HT, Jordan IB. A Design Technique for an Integrable Ternary Arithmetic Unit. Proceedings of the 1975 International Symposium on Multiple-valued Logic. 1975; 359-372. Mine H, Hasegawa T, Ikeda M, Shintani T. A Construction of Ternary Logic Circuits. Electron. Communication in Japan. 51: 133-140.


16

11.

Rosser JB, Turquette AR. Many-valued Logics. North-Holland Publishing Co. Amsterdam. 1952.

13.

Post EL. Introduction to a general theory of Elementary Propositions. American Jour Math. 1921; 43: 163-185.

12.

14. 15.

Vacca R. A Three-valued System of Logic and its Applications to Base Three Digital Circuits. Proc Intern. Conf. Inform. Proceeding, (UNESCO). 1959; 407-414.

Bitran M, Strutt MJO. Minimization of Ternary Logic and Complete Set of Integrated Circuits. Electron. And Comm. 1971; 25: 387-392.

Nutter RS, Swartwout RE. A Ternary Logic Minimization Technique. Conference Record of the 1971 Symposium on the Theory and Applications of Multiple-valued Logic Design. 1971; 112-123.


17

CHAPTER 2

SMGr up

Ternary Arithmetic Operations INTRODUCTION We all are familiar with the arithmetic operations like addition, subtraction, multiplication and division of decimal number. Similar operations can be performed on ternary numbers. The rules for ternary addition, subtraction, multiplication and division are different but these are closely related to binary arithmetic operations.

TERNARY ARITHMETIC Ternary Addition

Rules for ternary addition are given in table 2.1.

Table 2.1: Ternary addition rules.

Augend 0 0 0 1 1 2

Addend 0 1 2 1 2 2

Sum 0 1 2 2 0 1

Carry 0 0 0 0 1 1

Result 00 01 02 02 10 11

Explanation: Let augend be equal to 0, addend be equal to 0 it gives Sum = 0 + 0 = 0 and no carry generated so carry = 0 as shown in table 2.1. If when augend be equal to 1, addend be equal to 2 we get 1 + 2 = 3.i.e. representation for 3 in ternary is 01 that implies sum = 0 and carry = 1. Similarly when augend be equal to 2, addend be equal to 2 we get 2 + 2 = 4. i.e. representation for 4 in ternary is 11 that implies sum = 1 and carry = 1. Consider an example

Let Augend A = 64 and Addend B = 48 So A + B = 112

Ternary representation for 64 and 48 are 02101 and 01210 respectively. According to rules given in table 2.1.we can perform addition as: A= 64 = 02101 +B =48 = 01210 Sum = 112 = 11011


1

General block diagram for ternary adder is shown below and detail design and logic gate level implementation of circuit for half and full is described in chapter 5. Block diagram for ternary Adder.

Ternary Subtraction

Rules for ternary subtraction are given in table 2.2.

Table 2.2: Ternary subtraction rules

Minuend 0 0 0 1 1 2

Subtrahend 0 1 2 1 2 2

Difference 0 2 1 0 2 0

Borrow 0 1 1 0 2 0

Result 00

Explanation: Let Minuend be equal to 0, Subtrahend be equal to 0 it gives Difference = 0 - 0 = 0 and no Borrow generated so Borrow = 0 as shown in table 2.2. If when Minuend be equal to 1, Subtrahend be equal to 2 we get 1 - 2 = -1.i.e. representation for 3 in ternary is 01 that implies Difference = 0 and borrow = 1. Similarly when Minuend be equal to 2, Subtrahend be equal to 2 we get 2 - 2 = 0. i.e. representation for 0 in ternary is 00 that implies Difference = 0 and borrow = 0. Consider an example

Let Minuend A = (64)10 and Subtrahend B = (48)10 So A - B = (16)10

Ternary representation for 64 and 48 are (02101)3 and (01210)3 respectively.

According to rules given in table 2.2. we can perform subtraction as:

Let A = 02101 = 64 and B = 01210 = 48, - 48 can be represented as 21012, it is 1’s compliment of 48. by adding 1to 1’s compliment of 48 we get 3’s compliment of 48 i.e.21012 + 1= 21020 (Details about 1’s and 3’s compliment is explained in chapter1.) So A-B = 02101 + 21020 100121

Discarding left most digit, the answer is (00121)3 which is equivalent to (16)10. Block for ternary subtractor is shown in figure 2.2 and details are explained in chapter 5. Ternary Subtractor


2

Ternary Multiplication

Table 2.3: Rules for ternary multiplications. Multiplicand 0 0 0 1 1 2

Multiplier 0 1 2 1 2 2

Product 0 0 0 1 2 1

Carry 0 0 0 0 0 1

Result 00 00 00 01 02 11

Explanation: Let Multiplicand be equal to 0, Multiplier be equal to 0 it gives product = 0 and carry = 0 as shown in table 2.3. If when Multiplicand be equal to 1, Multiplier be equal to 2 we get 1 x 2 = 2.i.e. representation for 2 in ternary is 02 that implies product = 2 and carry = 0. Similarly when Multiplicand be equal to 2, Multiplier be equal to 2 we get 2 x 2 = 4. i.e. representation for 4 in ternary is 11 that implies sum = 1 and carry = 1. Example: Let Multiplicand A = (15)10 and B = (11)10 So, 15 X 11

(165)10

Now (120)3 is ternary representation for (15)10 and (102)3 is representation for (11)10 i.e.

120 (15)10

X 102 (11)10 1010

+ 000x

+ 120xx

20010 (165)10

By applying the rules in table 2.3.3 the result is 20010 which is ternary representation for 165.

Figure above is for ternary multiplier and detail about design, gate level implementation and circuit is explained in chapter 5.

Ternary Division

It is performed in the same way as binary division. Rules are as below. Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

3

1) If Dividend is greater than or equal to divisor, put value to quotient and subtract divisor from dividend. 2) Shift the divisor one place right and perform step 1 up to dividend is smaller than the divisor. 3)

If reminder is non zero, repeat step 1 by putting corresponding values to reminder.

4) Repeat until dividend is less than the divisor and quotient is correct. The dividend is the remainder.

Example 1: Let A = (30)10 = 1010 is ternary representation and B = (10)10 =101is representation for (10)10 Therefore A÷B = (30)10 ÷(10)10 = 1010 ÷ 101= 10 which is ternary representation for (3)10

10 1

10

1010

-101 000 -000 000 Example 2: Let A = (15)10 and B = (3)10 So A÷B -= (5)10 i.e. (120)3 ÷ (10)3 = (12)3 11

SUMMARY

12 120

-10 020 -20 00

Various number systems that are used in digital circuits, microprocessor, computers etc have been presented. The rules of ternary arithmetic operations like addition, subtraction, multiplication, division are given. The knowledge of this number system is essential for effective understanding of various

ternary circuits.


4

References 1.

Shimabukuro K, Zukeran C. Reconfigurable current-mode multiple-valued residue arithmetic circuits. Proc. 28th Int Symp. Multiple-Valued Logic. 1998; 282-287.

3.

Hanyu T, Kameyama M. A 200 MHz pipelined multiplier using 1.5 V-supply multiple valued MOS current-mode circuits with dual-rail source-coupled logic. IEEE Journal of Solid-State Circuits. 1995; 30: 1239-1245.

2.

4. 5.

Wei S, Shimizu K. Residue arithmetic multiplier based on the radix-4 signed-digit multiple-valued arithmetic circuits, 12th Int Conf. on VLSI Design. 1999; 212-217.

Gonzalez F, Mazumder P. Multiple-valued signed digit adder using negative differential resistance devices. IEEE Trans. on Computers. 1998; 47: 947 - 959. Radanovic M. Syrzycki. Current-mode CMOS adders using multiple-valued logic. Canadian Conference on Electrical and Computer Engineering. 1996; 190-193.

6.

Ishizuka O, Handoko D. VLSI design of a quaternary multiplier with direct generation of partial products. Proc 27th Int Symp. Multiple-Valued Logic. 1997; 169-174.

8.

Ohki Y, Aoki T, Higuchi T. Redundant complex number systems, Proc 25th Int Symp. Multiple-Valued Logic. 1995; 14-19.

7.

Saed A, Ahmadi M, Jullien GA. Arithmetic with signed analog digits, Proc 14th IEEE Symposium on Computer Arithmetic. 1999; 134-141.


5

SMGr up

CHAPTER 3

Ternary Logic Families INTRODUCTION Ternary logic is implemented in two operating modes; these are current & voltage mode operation. In current- mode circuits, currents are defined to have logical levels that are integer multiples of a reference current (or logic 0 current) unit. The frequently used linear sum operation can be performed simply by wiring, resulting in a reduced number of active devices in the circuit. Where as in voltage mode circuits, distinct voltage levels are defined and device switches at their distinct levels. Voltage mode operation is again classified in to balance and unbalance operation mode. In balance mode –ground (logic 0) reference (logic 1) and + v (logic 2) levels are there and in unbalance mode ground/2 and v levels are expressed. In this chapter balance voltage mode operation is considered for the operation of ternary families. The basic switching elements used for the implementations of MVL in both the modes are Diode, transistors, MOSFETS & Resonant tunneling devices (RTDs) and recently Carbon Nano Tube (CNT) [1] and circuits are developed and simulated using MOS, RTD and CNT devices.

TERNARY LOGIC CIRCUITS BASED ON CMOS

Switching elements in the implementation of inverters those discussed in chapter1 are transistors, MOSFET & RTDs. Because of low power consumption, less propagation time, high fan in\out, high voltage swing & operation in GHz domain, circuits based on MOSFET of RTDs are more in use [2,3].

Figure 3.1 shows MOS base three inverters namely STI (simple ternary inverter), PTI (positive ternary inverter) &NTI (negative ternary inverter). Truth table for the same is given in Table 3.1

Figure 3.1: CMOS T-Inverter (a) STI (b) PTI (c) (NTI)


1

Table 3.1: Truth table for Inverter Input X 0 1 2

STI 2 1 0

Output PTI NTI 2 2 2 0 0 0

Operation of CMOS T- Inverter Figure 3.1 (a) shows circuit realization of STI. The behavior of circuit is strongly dependent on choice of supply voltage, the logic levels VH,VI,VL technological process parameter VT and body effect on transistor. In this circuit T1 is P Channel enhancement & T2 is N channel enhancement transistor with drain ohmic resistance of 1x106 Ω. The supply voltages are ± Vdd and three ternary levels as shown in table 3.2 for the operation of circuit, threshold voltage V+ has to satisfy the inequality

| -Vdd | < | VT | < | +Vdd|

Assuming ± Vdd = ± 5V VT should be ≅ 0 v

(1)

If condition 3.1 is satisfied & input X = high (VH) is applied to input terminal, then T2 turns ON (Vgs > VT) and T1is OFF. Therefore output Vo ≅ -Vdd i.e. low (VL). Since T1 and T2 are in series, current ID1 is drain current of T1which is negligible. When intermediate level VI is applied to input X, Then T1and T2 are ON and output is ≅ VI.If applied input is low, then T1 turns ON and T2 is OFF, so the output is ≅ +Vdd.

Table 3.2: voltage level –V to +V. Voltage level

Logic value

+V

2

0

1

-V

0

PTI & NTI circuits are shown in Figure 3.1 (b) and (c) respectively. In these circuits T3,T5 are P- channel enhancement MOS. T4,T6 are N- channel enhancement MOS. The threshold voltages VT of T3 and T6 are required to satisfy inequality 0 ≤ | VT | ≤ | +Vdd |

(2)

|+Vcc| ≤ | VT | ≤ | 2Vcc|

(3)

and for T4, T5

The operation of circuits is same as that of STI.

Operation of CMOS T- OR / NOR

T- OR is a circuit that have X1---Xn as input &Yo as output such that

T − OR = X1 + X2 − − − − + Xn = Max[X1, X2 − − − Xn]


(4)

2

and T- NOR has an output that is compliment as OR function i.e.

T − NOR = X1 + X2 − − − − − Xn = Max[X1, X2 − − − Xn]

(5)

T Inverter is a basic circuit that is used for implementing T-OR/NOR functions, depending upon the type of inverter used, the logic functions T-OR/NOR can be Simple ternary OR/NOR (STOR/NOR), Positive ternary OR/NOR (PT-OR/NOR) and Negative ternary OR/NOR (NT-OR.NOR). Figure 3.2 shows ST-OR & NOR circuits and Table 3.3 for the same is summarized.

Figure 3.2: CMOS ST –NOR & ST – OR (a) ST-NOR (b) ST-OR. Table 3.3: Truth table for Ternary OR/NOR Logic functions. X1 X 2

ST-OR

PT-OR

NT-OR

ST-NOR

PT- NOR

NT-NOR

00

0

0

0

2

2

2

01

1

0

2

1

2

0

02

2

2

2

0

0

0

10

1

0

2

1

2

0

11

1

0

2

1

2

0

12

2

2

2

0

0

0

20

2

2

2

0

0

0

21

2

2

2

0

0

0

22

2

2

2

0

0

0

The inequality condition required for implementing PT-NOR is, For T1, T2

|0| < VT< |Vdd|

(6)

|Vdd| < |VT| < |2Vdd|

(7)

For T3,T4


3

and for NT-NOR T1, T2 |Vdd| < | VT | < |2Vdd|

T3, T4

| 0 | < | VT | < |Vdd|

CMOS T- AND/NAND

Ternary AND function is defined as

T − AND = X1.X2 − − − − − Xn = Min[x1x2xn]

T − NAND = X1.X2 − − − − − Xn = Min[x1x2xn]

(8) (9)

(10) (11)

Truth table for Simple, Positive and Negative ternary is AND/NAND given in Table 3.4 and implementation is shown in Figure 3.3.

Figure 3.3: Implementation of Ternary AND/NAND (a) ST-AND (b) ST-NAND.

In the circuit implementation T1,T2,T5 are P-Channel enhancement MOSFET &T3, T4, T6 are N-Channel enhancement MOSFET. The circuit is realized using inverters, in which T1.T2 are connected in Parallel & T3, T4 are in series.

PT-AND/NAND& NT-AND/NAND are constructed by using PTI and NTI. However for implementation PT-NAND and NT-NAND inequality (3.6) (3.7) (3.8) and (3.9) should be satisfied.

Table 3.4: Truth table for ternary AND/NAND.

X1 X2

ST-AND

PT-AND

NT-AND

ST-NAND

PT-NAND

NT-NAND

00

0

0

0

2

2

2

01

0

0

0

2

2

2

02

0

0

0

2

2

2

10

0

0

0

2

2

2

11

1

0

2

1

2

0

12

1

0

2

1

2

0

20

0

0

0

2

2

2

21

1

0

2

1

2

0

22

2

2

2

0

0

0


4

CMOS T-EX-OR/NOR Ternary EX-OR/NOR function is defined as

T − EX − OR = X1 ⊕ X2

T − EX − NOR = X1 ⊕ X2

(12)

(13)

Basically functions in eq. (3.12) and (3.13) are mod 3 addition of ternary numbers neglecting the carry. Table 3.5 is a table for T-EX-OR /NOR operation. Operations can be verified using truth table.

Figure 3.4: Gate level implementation of Ex-OR/Ex-NOR. Table 3.5: Truth table for ternary EX-OR/Ex-NOR gates. Input X1 X2

Output EX-OR

Output EX-NOR

00

0

2

01

1

1

02

2

0

10

1

1

11

2

0

12

0

2

20

2

0

21

0

2

22

1

1

Noise Margins in T-Gates For binary logic gates two noise margins are defined, one for logic level 0, and one for logic level 1. In ternary logic system on the other hand, four noise margins are necessary, one for logic level 0, two for logic level 1, and one for logic 2. These quantities are denoted by NM0, NM1, and NM2 are defined as NM0 = V10– V00

NM1+= Vi1+ – V01+

NM1-= V01- – Vi1- NM2 = V02 – V12

(14)

(15)

(16) (17)

Vi1+= Maximum gate input which will unambiguously be interpreted by the gate as level 0(1).


5

Vi1- = Minimum gate input which will unambiguously be interpreted by the gate as level 2(1).

V01+ = Maximum voltage which will appear at the gate output when the output is at logic level 0(1). V01- = Minimum voltage which will appear at the gate output when the output is supposed to be logic level 2(1).

Figure 3.5: Noise margin in ternary logic gates.

The input voltages of Figure 3.5 can be expressed in terms of the threshold voltages as V10 ≈ | Vdd| - | VTE |

(18)

Vl1 ≈| VTD |

(20)

(22)

Vl1 ≈ - | VTD |

Vl2 ≈| VTE | - |VCC |

Therefore, ([3.14)to (3.17) yield

NM0 = 2Vdd - | VTE |

NM1 = | VTD | NM1 = | VTD | NM2 = 2Vdd - | VTE |

VOLTAGE AND CURRENT PARAMETERS

(19)

(21)

(23)

(24)

(25)

For the T gates explained above, the voltage and current parameters are proposed below based on our simulation results.

• High level input voltage (VIH): Minimum input voltage, which is recognized by the gate as logic 2. = 4.35v


6

• Intermediate level input voltage (VII+): Minimum input voltage, which is recognized by the gate as logic 1. =1v. • Intermediate level input voltage (VII-): Minimum input voltage, which is recognized by the gate as logic 1. = -1v.

• Low level input voltage (VIL): Maximum input voltage, which is recognized by the gate as logic 0. = -3.5 v. • High level output voltage (VOH): This is the minimum voltage available at the output corresponding to logic 2. = 5.0V. • Intermediate level output voltage (VOI+): This is the minimum voltage available at the output corresponding to logic 1. = 14.78mV.

• Intermediate level output voltage (VOI-): This is the minimum voltage available at the output corresponding to logic 1. = -14.9mV.

• Low level output voltage (VOL): This is the maximum voltage available at the output corresponding to logic 0. = -5.0 v. • High level input current (IIH): This is minimum current, which must be supplied by driving source corresponding to logic 2. = 1µA.

• Intermediate level input current (III): This is minimum current, which must be supplied by driving source corresponding to logic 1. = 4.44 µA.

• Low level input current (IIL): This is maximum current, which must be supplied by driving source corresponding to logic 0. = -1µA. • High level output current (IoH): This is maximum current which gate can source corresponding to logic 2. = 4.9 µA.

• Intermediate level output current (IoI): This is maximum current which gate can sink corresponding to logic 1. –0.049µA. • Low level input current (IoL): This is maximum current which gate can sink corresponding to logic 0. = -4.9 µA.

CALCULATED NOISE MARGIN

From above voltage & current parameters noise margin for logic gates are

• Noise margin corresponding to logic 0: NM0 = VOL- VIL = 0.65 V

• Noise margin corresponding to logic 1: NM1+= VII+- 0 = 14mV • Noise margin corresponding to logic 1: NM1-= VII- - 0 = 14mV

• Noise margin corresponding to logic 2 : NM2 = VOH- VIH = 0.65V


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Device Switching Time It is defined as speed at which MOSFET changes its state from off-intermediate-on state & vice versa. It is expressed in terms of propagation delayτ. Switching time for above devices is shown for N-channel and P=channel MOSFET in Figure 3.6.

Figure 3.6: Switching time for N and P channel MOSFET.

Power Dissipation

It is amount of power dissipated in single gate. It is a arithmetic addition of static power, dynamic power and power during transition of MOS from ON to OFF state and vice versa. For inverter, maximum power will dissipated only when both transistors T1 & T2 are ON. Dynamic power dissipation during transition is almost negligible. So power dissipation is

P.D =

Vdd 2 (R1 + R2) (R1.R2)

For supply = +/- 5v & Rd = 1M each, P.D. 100 µW. Here R1 and R2 form parallel combination of equivalent Rd.

Same analogy is extended for P.D. calculation in NAND/NOR T- gates. A Simulated values are about 10 to 12 W and for AND/OR is 10 to 12µW.

TERNARY LOGIC CIRCUITS BASED ON RTDS

Resonant-Tunneling Diodes (RTDs) show Negative Differential Resistance (NDR) at room temp. If InGaAs /AlAs double barrier structure are used, Peak current densities as high as 105 A/ m2 are obtained with peak to valley current ratio more than five The NDR Characteristic can be used to reduce circuit complexity; enhance circuit Performance in terms of speed, chip area & Power consumptions. One of the possible implementations of MVL circuit is using RTDs & high electron mobility transistors (HEMT). The basic idea of these circuits is to synthesize transfer characteristic by Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

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two-logic element namely up & down literal, that is obtained by using circuits called monostableto-bistable transition element (MOBILE) [4].

MOBILE exhibits two functions i.e. down & up literal. Up &DOWN literals are one variable function with binary output. The down literal is high for x < a & for x > a, while up literal is low for x < a & high for x > a, where x & a are threshold value & variable respectively. By using these circuits as key element MVL circuits are implemented.

Circuits Elements: Down & Up Literals

A MOBILE basically consists of two series-connected RTDs, A and X, as shown in Figure 3.7 (a) It is assumed that X has a gate to modulate its peak current. Oscillating voltage between V1 (low) and V2 (high) is supplied to the circuit. The output is obtained at every cycle of oscillation Figure 3.7 (b). When the circuit voltage VCLOCK is V1, the circuit is monostable, where both RTD’s are in the “on” (low- resistance) state. As VCLOCK increases from V1 to V2, the circuit evolves from the monostable state to the bistable state Figure 3.7(c).

Figure 3.7: (a) Circuit configuration for down-literal monostable-to-bistable transaction logic element (MOBILE).

(b) A timing chart of the operation. (c) The bi-Stable state and (d) peak currents as a function of input voltage and transfer Characteristics of down literal.

V2 is selected as a value so that either A or X switches from the “on” state to the “off” state (high–resistance) state when VCLOCK = V2. If X switches into the “off” state and A remains in the “on” state, the output is VOH (high) because the voltage between the terminals of X increases as X switches off. On the other hand, it A switches off and X remains on, the output is VOL (low). The output is thus determined at the rising edge of VCLOCK and latched until VCLOCK decreases from V2 to V1, when the circuit is reset and ready for the next cycle.


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Suppose that the peak current of X increases with an increase in the gate voltage VIN as shown in Figure 3.7 (d). To obtain the logic function, the input VIN is first supplied to the gate and then VCLOCK increases from V1 to V2. If VIN< VTD, X switches from “on” to “off” according to switching rule: the smaller the peak current the earlier the RTD switches as the circuit voltage increases. Therefore, the output is VOH (high) as explained above. On the contrary, if VIN > VDT, the peak current of A is smaller than that of X. Then A switches to the “off” state, and the output is VOL (low). In this manner, the circuit works as an inverter with a threshold of VTD Figure 3.7 (d) shows that the threshold voltage is determined by the intersection of two lines representing the peak currents. If we increase the RTD area of A, for example the line denoted A in Figure 3.7 (d) moves upward and VTD increases. The threshold is thus tunable. If the threshold is adjusted to a properly selected value by designing the device geometry, the circuit operates as a down literal.

In a similar manner an up literal is obtained with the circuit shown in Figure 3.7. Here, the peak current of Y can be modulated by the gate voltage VIN. As shown in Figure 3.8 (a), it is assumed that the peak current of Y increases as VIN increases and becomes larger than that of B when VIN> VTU. As the circuit voltage increases from V1 to V2, Y switches off when VIN< VTU, according to the switching rule mentioned above B remains “on,” and the output is VOL (low). If VIN> VTU, B switches from the “on” state to the “off” state and the output is VOH (high). Therefore, the circuit operates as an Up literal.

Figure 3.8: (a) Circuit configuration of Up literal (b) Peak current as a function of input voltage & Transfer characteristics of Up literal.

Operation of RTD T-Invertor

By combining up & down literal, transfer characteristic that represent multilevel output can be synthesized. Ternary inverters, that forms the complementation in 3-valued logic is implemented by using two down literals. Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

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Figure 3.9 shows the circuit configuration on which contains two down literals. A pair of A and

X and a pair of B and Y. The output terminal is extracted from the node between B and X & the input terminal is connected to the gates of X and Y. The upper limit of VCLOCK, V2, has been selected

to that two out of the four RTD’s, A, B, X, and Y, switch off at V2. If the two RTD’s that switch off are

X and Y, the voltages between the terminals of X and Y increase and the output is the highest. If either X or Y switches off at the output is the second highest, because the voltage only increases

between the terminals of either X or Y. If both X and Y remains unswitched, the output is the lowest. The output voltage thus quantized into three discrete levels is obtained then VCLOCK =V2. .

Figure 3.9: (a) Circuit configuration of ternary inverter and (b) peak currents as function of

input voltage and transfer characteristics of a ternary inverter.

Logic operation is obtained as follows: Suppose that the peak currents of X and Y increases as

the input increases and that the peak current of A is smaller than that of B, as shown in Figure 3.9 (b). As mentioned above, the circuit shown in Figure 3.9(a) consists of two down literals: one is

the pair of A and X with threshold of VT1, while the other is B and Y with the threshold of VT2. The

output is a superposition of these two down literals, as is explained below. If VIN< VT1, the peak

currents of X and Y are both smaller than those of A and B. Therefore, according to the switching

rule in series-connected RTD’s X and Y switch off when VCLOCK= V2, and the output is the highest at “2.” When VT1< VIN< VT2, the peak current of A is smaller than that of X, and then A and Y switch

off when VLOCK = V2. This results in the intermediate output value if “1.” If VT2< VIN, the switched-off RTD’s are A and B [X and Y remain unswitched], and the output is the lowest at “0.” The relation between the input, switched RTD’s and the output summarized in Table 3.6


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Table 3.6: Input versus output in ternary Inverter. VIN

Switched RTD’s

VOUT

VIN< VT1

X, Y

“2”

VT1< VIN< VT2

A, Y

“1”

VT2< VIN

A, B

“0”

Operation of RTD T-AND/ NAND Logic gates Ternary inverters are combined to synthesis T-AND/NAND logic gates. Truth table for the AND/NAND Operation given in Table 3.4 Figure 3.10 shows implementation of T-AND/NAND gates. Four down literals that form the T-AND/NAND gate are a pair of A-X, B-Y, A| -X|&B| -Y|. Let for A-X &A| -X| threshold voltage be VT1& VT2 for B-Y, pair B| -Y|. The operation of circuit is same as if two pairs of inverters connected in parallel (A-B&A| - B|) & two in series (X-Y &A| -X|). Table 3.7 summarizes details of switching RTD’s.

Figure 3.10: RTD based T-AND/NAND gates (a) AND (b) NAND.

Vin1

Vin2

VT1

0

0

Vin1< VT1

0

1

0

Table 3.7: RTD switching table. VT2

OFF

ON

OFF

ON

Yo

Yo

Vin2< VT2

X-Y

A-B

X‫ ﺍ‬-Y‫ﺍ‬

A‫ﺍ‬-B‫ﺍ‬

2

0

Vin1 VT2

X-Y

A-B


X‫ﺍ‬-Y‫ﺍ‬

2

0

1

0

VT1< Vin1< VT2

Vin2< VT2

A-Y

B-X



2

0

1

1

VT1< Vin1 VT2

A-Y

B-X



1

1

2

0

Vin1> VT1

Vin2< VT2

A-B

X-Y


A‫ﺍ‬-B1

2

0

2

1

Vin1> VT1

Vin1< Vin2< VT2

A-B

X-Y

A‫ﺍ‬-Y‫ﺍ‬

B‫ﺍ‬-X‫ﺍ‬

1

1

2

2

Vin1> VT1

Vin2> VT2

A-B

X-Y



0

2


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Operation of RTD T-OR/NOR logic gate Function in the eq. (4) & (5) is implemented using, for down literals in series parallel connection as shown in Figure 3.11. This structure series as T-OR/NOR logic gate. Truth table for OR/NOR logic function is given in Table 3.5.

Let for A-X &A| -X| threshold voltage be VT1& VT2 for B-Y, B|-Y| pair. Table 3.8 gives switching table for RTD’s. Assuming clock is applied such that any four of RTS’s are off when V2 is maximum. The switching of RTD’s can be verified for different input conditions Vin1, & Vin2. Symbols for T-OR/NOR gates are shown in Figure 1.5 [5,6]

Figure 3.11: RTD based OR/NOR gates (a) OR (b) NOR.

Vin1

Table 3.8: RTD switching table.

VT1

Vin2

VT2

OFF

ON

OFF

ON

YO

YO

0

0

Vin1< VT

Vin2< VT

X-Y

A-B

X‫ ﺍ‬-Y‫ﺍ‬

A‫ﺍ‬- B‫ﺍ‬

2

0

0

1

Vin1< VT1

VT1< Vin2< VT2

X-Y

A-B

A‫ ﺍ‬-Y‫ﺍ‬

B‫ﺍ‬- X‫ﺍ‬

1

1

0

2

Vin1< VT

2

Vin2> VT

2

X-Y

A-B

A‫ ﺍ‬-B‫ﺍ‬

X‫ﺍ‬Y‫ﺍ‬

0

2

1

0

VT1< Vin1< VT2

Vin2< VT2

A-Y

B-X

X‫ ﺍ‬- Y‫ﺍ‬

A‫ ﺍ‬- B‫ﺍ‬

1

1

1

2

1

1

VT < Vin1< VT

VT < Vin2< VT

A-Y

B-X

A‫ﺍ‬- Y‫ﺍ‬

B‫ﺍ‬- X‫ﺍ‬

1

1

1

2

VT1< Vin1< VT2

Vin2> VT2

A-Y

B-X

A‫ ﺍ‬- B‫ﺍ‬

X‫ ﺍ‬- Y‫ﺍ‬

0

2

2

1

2

1

2

2

0

Vin1> VT

Vin2< VT

A-B

X-Y

X‫ ﺍ‬- Y‫ﺍ‬

A‫ ﺍ‬- B‫ﺍ‬

0

2

2

1

Vin1> VT1

VT1 VT

Vin2 > VT

2

TERNAY LOGIC GATES BASED ON CARBON NANO TUBE TECHNOLOGY Recent advancement in ternary logic gate is based on Carbon Nano Tube (CNT) technology. CNTs attribute a number of extraordinary properties, amongst which are high electric conductivity, high thermal conductivity, mechanical strength, thermal resistivity / stability, actuation properties at low voltages and field emission. An existing semiconductor technology Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

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has limitations on its performance like, electron tunneling through short channels and thin insulator films, the associated leakage currents, passive power dissipation, short channel effects, and variations in device structure and doping. These limits can be overcome to some extent and facilitate further scaling down of device dimensions by modifying the channel material in the traditional bulk MOSFET structure with a single carbon nanotube or an array of carbon nanotubes [7]. Carbon nanotube (CNTs) is form of carbon with a cylindrical nanostructure. Nanotubes have

been constructed with length-to-diameter ratio of up to 132,000,000:1, significantly larger than for any other material. These cylindrical carbon molecules have unusual properties, which are valuable for nanotechnology, electronics. There are two forms of CNT i.e. single walled and multi walled. Wall is a layer of substance molecules. Depending upon the layers it is referred to as single walled and multi walled Nano tube. Figure 3.12 (a) and (b) shows single and multi walled Nano tubes.

(a)

(b)

Figure 3.12: (a) Single walled, (b) Multi walled Nano tube.

Single-walled nanotubes (SWNT) have a diameter of close to 1 nanometer, with a tube length that can be many millions of times longer. The structure of a SWNT is conceptualized by wrapping a one-atom-thick layer of graphite called graphene into a seamless cylinder. The way the graphene sheet is wrapped is represented by a pair of indices (n,m). The integers n and m denote the number of unit vectors along two directions in the honeycomb crystal lattice of graphene. If m = 0, the nanotubes are called zigzag nanotubes, and if n = m, the nanotubes are called armchair nanotubes. Otherwise, they are called chiral. The diameter of an ideal nanotube can be calculated from its (n,m) indices as in Figure 3.13.

Figure 3.13: Structure of single walled CNT.


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CNT based Field Effect Transistor As one of the promising new devices, carbon nanotube FETs (CNTFETs) avoid most of the fundamental limitations for traditional silicon devices, due to their unique one-dimensional bandstructure that suppresses backscattering and makes near-ballistic operation a realistic possibility [8-10]. A single walled CNT (SWCNT) can be visualized as a sheet of graphite, which is rolled up and joined together along a roll- up vector Figure 3.14(a).

Figure 3.14(a): Unrolled graphite sheet.

Depending on the chiral angle (roll-up vector or chirality vector), the CNT can be either semiconducting or metallic. By considering the indices (n, m) shown in Figure 1, the nanotube is metallic if n = m or n-m = 3i where i is an integer. Otherwise, the tube is semiconducting. CNTFETs are the FETs that make use of semiconducting CNTs as channel material between two metal electrodes that act as source and drain contacts. The operation principle of CNTFET is similar to that of traditional silicon devices. CNT structure is shown in Figure 3.14 (a),(b) and (c) respectively. As shown in Figure 3.14: (b), this three (or four) terminal device consists of a semiconducting nanotube, acting as conducting channel, bridging the source and drain contacts. The device is turned on or off electrostatically via the gate. Despite several serious technological barriers, CNTFETs with their small feature size and high-current capability show a potential for performance improvement compared with CMOS transistors.

a)2-D view

b) cross sectional view

Figure 3.14(b): CNT structure.

c)3-D view


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The CV/I performance of an intrinsic CNTFET is 13 times better than the CV/I performance of a bulk n-type MOSFET because the CNTFETs effective gate capacitance of one CNT per gate is about 4% compared to bulk CMOS and the driving current ability of each CNT is about 50% of a bulk n-type MOSFET with minimum gate width (48 nm) at a 32 nm node (due to the ballistic transport nature of a CNT). Moreover due to the similar behavior and the current driving capability of a pFET compared to those of an FET the performance improvement of a pFET over a PMOS is better than the one of a nFET over a NMOS. Even though a CNTFET has a leakage current in the off-state, this leakage current is controlled by the full band gap of the CNTs and the band to band tunneling; this is less than for a MOSFET [11,12].

The expected (optimistic) performance advantage of a CNTFET is unlikely to be achievable in a real device and will be significantly degraded for the CV/I (6 times for a nFET and 14 times for a pFET) due to device/circuit non-ideal conditions. These non-ideal conditions include the series resistance of the doped source/drain region, the Schottky Barrier (SB) resistance at the metal/CNT interface, the gate outer-fringe capacitance and the interconnect wiring capacitance. However, the need for low power consumption and high operating frequency has resulted in geometry and supply scaling with a significant increase in operating temperature for a device. With these scaling features, the effects of systematic and random variations in Process, supply Voltage, and Temperature (PVT) may cause an inconsistent delay and increase in leakage to appear even in low power circuits, thus becoming one of the major challenges in nanoscale devices. Figure 3.15 shows V-I (Ids Vs Vgs) characteristic for 18 nm CNTFET.

Figure 3.15: V-I characteristics of 18nm CNTFET.

CNT based Ternary Logic Gates I: CNT inverter and its operation

The operation of CNT inverter is same as that of semiconductor FET based inverter except an optimum performance is achieved in operation of the circuits when employed with CNTFET. Symbol for CNTFET is shown in Figure 3.16 and inverter implementation in 3.17(a), (b) and(c) as STI, PTI and NTI.


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Figure 3.16: Symbols for P and N type CNTFET.

Figure 3.17: Implementation of CNT based inverter (a) STI (b) PTI (C) NTI.

Operation: One of the most widely used logic design style is static complementary CMOS; the main advantages of the complementary design are robustness, good performance, and low power consumption with small static power dissipation. A complementary CNTFET network can also be used for ternary logic design to achieve good performance, low power consumption, and to avoid the use of large resistors and reduce area overhead. Figure 3.15 shows the CNTFET-based STI design; the STI in Figure 3.17(a) consists of six CNTFETs. The chiralities of the CNTs used in T1, T2, and T3 are (19, 0), (10, 0), and (13, 0), respectively. From (1 given below), the diameters of T1, T2, and T3 are 1.487, 0.783, and 1.018 nm, respectively. Therefore, the threshold voltages of T1,T2, and T3 are 0.289, 0.559, and 0.428 V, respectively from (2 given below).The threshold voltages of T5, T6, and T4 are − 0.289,− 0.559,and − 0.428 V, respectively. When the input voltage changes from low to high at the power supply voltage of 0.9 V, initially, the input voltage is lower than 300 mV. This makes both T5 and T6 turn ON, bothT1andT2turn OFF , and the output voltage 0.9 V, i.e. logic 2. As the input voltage increases beyond 300 mV, T6 is OFF and T5 is still ON .Meanwhile,T1is ON and T2 is OFF . The diode connected CNTFETs T4 and T3 produce a voltage drop of 0.45 V from node n2 to the output, and from the output to n1 due to the threshold voltages of T4 and T3. Therefore, the output voltage becomes 0.45 V, i.e., half of the power supply voltage.


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As shown in Table I, half Vdd represents logic 1. Once the input voltage exceeds 0.6 V, both T5 and T6 are OFF, and T2 is ON to pull the output voltage down to zero. The input voltage transition from high to low transition is similar to the low to high transition [13].

II: CNT NAND and NOR gates

(a)

(b)

Figure 3.18: carbon nanotube field-effect transistor-based NAND and NOR gates. (a) Circuit diagram for two-input NAND and its symbol. (b) Circuit diagram for two-input NOR and its symbol.

The circuits and symbols for the two-input ternary NAND and ternary NOR are shown in Figure 3.18(a) and (b), respectively. Each of these two gates consists of ten CNTFETs, with three different chiralities. They are essentially the same as their binary CMOS counterparts, except for the transistors of different threshold voltages. In these two gates, similar to the STI circuit of Figure 4, the transistors with diameters of 1.487, 0.783, and 1.018 nm have threshold voltages of 0.289, 0.559 and 0.428 V, respectively, as established using (2). Its operation is same as that of FET based TNANA and NOR gates [13].

Performance characteristic of CNT Logic Gate Power delay product

Due to the increased demand for high-speed, high-throughput computation, and complex functionality in mobile environments, reduction of delay and power consumption is very challenging. Table 1 shows the delay, power, and PDP of logic gates in 32 nm CNTFET technologies; the PDP of the 32 nm MOSFET is about 100 times higher than that of the 32 nm CNTFET. Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

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PDP: Power Delay Product; CNTFET: Carbon Nanotube Field-Effect Transistor

Leakage power

As process dimensions shrink further into the nanometer ranges, traditional methods for dynamic power reduction are becoming less effective due to the increased impact of static power [14]. In general, leakage power is different depending on the applied input vector. Figure 3.17 shows the maximum and minimum leakage power for 32 nm CNTFET based logic gates. Figure 3.17 also shows that the maximum leakage power shows a similar trend for both CNTFET based gates, while the minimum leakage power shows somewhat different trends, because the stack effect is reduced in CNTFET circuits.

Figure 17: Maximum and minimum leakage power for 32 nm carbon nanotubeFET (CNTFET) logic gates.

Frequency response

For establishing the frequency response, AC simulation has been performed for CNTFET inverters. The results are given in Figure 3.18, where the CNTFET inverter shows nearly 3dB more voltage gain and 3 times higher 3dB frequency (f3dB). Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

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Figure 18: Frequency response for 32 nm metal-oxide semiconductor carbon nanotube FET (CNTFET) inverters.

PVT variations

With technology scaling, the effects of systematic and random variations in PVT have led to inconsistent delay and leakage in low power circuits, thus becoming a major obstacle for device scaling. Significant levels of process variations affect technology scaling beyond 90 nm, and they are changing the design environment from a deterministic to a probabilistic one. Moreover, the requirement of low power relies on supply voltage scaling, making voltage variations a significant challenge. The quest for increase in higher operating frequencies has resulted in significantly high junction temperature and within-die temperature variation [13,15,16]. Therefore, the possible performance degradation due to PVT variations has become a major criterion in assessing the performance of a new technology.

Process variation

When investigating physical process variations, CNTFET have different characteristics. The current change in CNTFET is below ±0.5%. However when the diameter of the CNTFET is changed by ±10%, the current change in a CNTFET is about ±17% as shown in Figure 3.19. Therefore for a CNTFET, the diameter variation is more important because a CNTFET is more sensitive to diameter variation than length and width variations. Based on this observation, the PDP and leakage of a CNTFET are computed and shown in Figure. 3.20 and 3.21, respectively. When the diameter of a CNTFET is changed, then the PDP changes too. Figure 3.21 shows that the maximum leakage power increases when the diameter is increased. Also note that the threshold voltage and diameter of a CNTFET are determined based on the chirality of the CNTs used in this type of transistor.

Figure 3.19: IDS (drain-to-source current) vs. VGS (gate-to-source voltage) with 10% Change of carbon nanotube (CNT) diameter (chirality) for the 32 nm CNTfield-effect transistor (FET).


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Figure 3.20: Power Delay Product (PDP) of 32 nm carbon nanotube field effect transistor (CNTFET) logic gates vs diameter (chirality) of CNT.

Figure 3.21: Maximum leakage power of the 32 nm carbon nanotube field effect transistor (CNTFET) logic gates vs. Diameter (chirality) of CNT.

Voltage variation

The reduction in power consumption due to voltage scaling is also confronted with the increased sensitivity to voltage variations; this is a major concern to assess the performance of a new technology such as CNTFETs. Figures 3.22 show the PDP for 32 nm CNTFET logic gates, respectively when the supply voltage is decreased until the gate stops functioning. These figures show that the inverter and the other logic gates operate until the supply voltage decreases to 0.5 V and 0.6 V, respectively. The overall PDP of the CNTFET-based gates is significantly low.

Figure 3.22: Power delay product (PDP) of 32 nm carbon nanotube field effect transistor


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(CNTFET) logic gates vs. supply voltage.

Temperature variation

As the circuit speed increases, a larger power consumption is often encountered, thus resulting in more heat at chip level. Circuits with an excessive power dissipation are more susceptible to run-time failures and account for serious re- liability problems [13,16]. Figure 3.23 the PDP of the CNTFET logic gates is constant. Maximum leakage power for CNTFET-based gates increase is exponential. Few combinational circuits (such as a 4 stage inverter chain, a 2:4 decoder, a 4:16 decoder, the ISCAS-85 Benchmark Circuit C17, a 1-bit full adder, a 3-bit Ripple Carry Adder, and the ISCAS-85 Benchmark Circuit 74182) have also been evaluated.

Figure 3.23: Power delay product (PDP) of 32 nm carbon nanotube field effect transistor (CNTFET) logic gates vs. temperature.

CNTFET threshold voltage check add formula

CNTFETs utilize semiconducting SWCNTs to assemble electronic devices [17]. A SWCNT consists of one cylinder only, and the simple manufacturing process of this device makes it very promising .A SWCNT can act as either a conductor or a semiconductor, depending on the angle of the atom arrangement along the tube. This is referred to as the chirality vector and is represented by the integer pair (n, m).A simple method to determine if a CNT is metallic or semiconducting is to consider its indexes (n, m): the nanotube is metallic if n = m or n-m = 3i, where i is an integer. Otherwise, the tube is semiconducting. The diameter of the CNT can be calculated based on the following

(1)

where a 0 = 0.142 nm is the interatomic distance between each carbon atom and its neighbor. The threshold voltage is defined as the voltage required turning ON transistor. The threshold voltage

of the intrinsic CNT channel can be approximated to the first order as the half band gap that is an inverse function of the diameter i.e.


22

(2)

(3)

where a=2.49 angstrom is carbon to carbon atom distance, and Vπ = 3.033 eV is the carbon π–π bond energy in the tight bonding model, eis the unit electron charge, and DCNT is the CNT diameter. As DCNTof a (19, 0) CNT is 1.487 nm, the threshold voltage of a CNTFET using (19, 0) CNTs as channels is 0.293 V from Eq. (26). As the chirality vector changes, the threshold voltage of the CNTFET will also change. Assume that m in the chirality vector is always zero, and then the ratio of the threshold voltages of two CNTFETs with different chirality vectors is given as:

Equation (27) shows that the threshold voltage of a CNTFET is inversely proportional to the chirality vector of the CNT. For example, the threshold voltage of a CNTFET using (13,0) CNTs is 0.428 V, compared to a (19,0) CNTFET with a threshold voltage of 0.293 V.

TERNARY QUANTUM LOGIC GATES

Most recent upcoming technology is based on quantum logic. Ternary logic gates in quantum logic are also referred to as Qudits or Qurtit. Qudits are made up of controlled particles and the means of control (e.g. devices that trap particles and switch them from one state to another).

In multi-valued (MV) Quantum Computing (QC), the unit of memory (information) is qudit (quantum digit). MV quantum logic operations manipulate qudits, which are microscopic entities such as a photon’s polarization or atomic spin. Ternary logic values of 0, 1, and 2 are represented by a set of distinguishable different states of a qutrit (quantum ternary digit)). These states can be a photon’s polarizations or an elementary particle’s spins. After encoding these distinguishable quantities into multiple-valued constants, qutrit states are represented by 0 , 1 , and 2 , respectively. Qudits exist in a linear superposition of states, and are characterized by a wavefunction ø . As an example ( d = 2 ), it is possible to have light polarizations other than purely horizontal or 1 vertical, such as slant 45° corresponding to the linear superposition of ø = 2 0 + 2 1 . In 2 ternary logic, the notation for the superposition is á 0 + â 1 + ã 2 , where α, β, and γ are complex numbers. These intermediate states cannot be distinguished, rather a measurement will yield that the qutrit is in one of the basis states, 0 , 1 , or 2 . The probability that a measurement of 2 2 2 a qutrit yields state 0 is á , state 1 is â , and state 2 is ã . The sum of these probabilities is one. The absolute values are required since, in general, α, β and γ are complex quantities.

[

]

Pairs of qutrits are capable of representing nine distinct states, 0 , 01 , 02 , 10 , 1 , 12 , 20 , 21 , and 2 , as well as all possible superpositions of the states. This property may

be mathematically described using the tensor product operation ⊗ [1]. The tensor product of


23

matrices is defined as follows:

a b   x c d  ⊗  z   

 x y  x y    ax b a     y   z v   z v    az = = v    x y   x y    cx c   d  z v    cz   z v     

ay bx by  av bz bv  cy dx dy   cv dz dv 

As an example, consider two qutrits with ψ 1 = α 1 0 + β 1 1 + γ 1 2 and ψ 2 = α 2 0 + β 2 1 + γ 2 2 . When the two qutrits are considered to represent a state, that state ψ 12 is the superposition of all possible combinations of the original qutrits, where .

ψ 12 = ψ 1 ⊗ψ 2 = α1α 2 00 + α1β 2 01 + α1γ 2 02 + β1α 2 10 + β1β 2 11 + β1γ 2 12 + γ 1α 2 20 + γ 1β 2 21 + γ 1γ 2 22

Superposition property allows qubit states to grow much faster in dimension than classical bits, and qudits faster than qubits [18]. An output of a gate is obtained by multiplying the unitary matrix of this gate by the vector of Hilbert space corresponding to this gate’s input state. A resultant unitary matrix of arbitrary quantum circuit is created by matrix or tensor multiplications of composing subcircuits. These all contribute to difficulty in understanding the concepts of quantum computing and creating efficient analysis, simulation, verification and synthesis algorithms.

Some Ternary Permutation Gates

Any unitary matrix represents a quantum gate. If a unitary matrix has only one 1 in every column and the remaining elements are 0, then such a matrix is called a permutation matrix. A quantum gate represented by a permutation matrix is called a permutation quantum gate.

Figure 3.24 shows a 2*2 ternary Feynman gate, which is the ternary counterpart of the binary Feynman gate with GF2 (Galois Field) sum replaced by GF3 sum. Here A is the controlling input and B is the controlled input. The output P is equal to the input A and the output Q is GF3 sum of A and B. Observe that GF3 sum is the same as modulo 3 sum. If B = 0 , then Q = A and the ternary Feynman gate acts as a copying gate. The ternary 2*2 Feynman gate is practically realizable.


24

A 2*2 gate called Generalized Ternary gate (GTG gate) is shown in Figure 3.27 Here, input

A is the controlling input and input B is the controlled input. The output P is equal to the input

A. The controlling input A controls a conceptual ternary multiplexer (a conditional gate) that can be realized using quantum technology such as ion traps. If A = 0 , then the output Q is the x shift

of the input B. Similarly, if A = 1 , then the output Q is the y shift of the input B and if A = 2 , then the output Q is the z shift of the input B. Here shift means all ternary shift operations including

the Buffer (simple quantum wire). It should note that depending on the six possible Shift gate for

each of the three positions of x, y, and z, there are 63 = 216 possible GTG gates. As the Conditional gate and the Shift gates are realizable in quantum technology, the GTG gate is a truly realizable ternary quantum gate.

General Model of Synthesizing Multi-Output Ternary Functions using Cascades of GTG Gates Realization of ternary half-adder function

C ( A, B ) = [0, 0, 0, 0, 0, 1, 0, 1, 1]T

and

S ( A, B ) = [0, 1, 2, 1, 2, 0, 2, 0, 1] (which is a multi-output irreversible function) using cascade of T

GTG gates (which is a reversible gate) is shown in Figure 3.28. Signal values at all intermediate

wires are shown as maps to verify the correctness of the circuit. In this realization we assumed the following:

(1) A GTG gate can be controlled either from top or from bottom.

(2) A limited vertical wire crossing for the controlling signals of GTG gates is allowed.

(3) Constant input signals 0, 1, or 2 are added as needed to help convert the irreversible

function into reversible one.

(4) Output may be realized along any primary input line or any constant input line.

(5) Each of the GTG gate form a column where the remaining lines represent quantum wires.

The columns are cascaded to realize the circuit.


25

B A 0 1 2

Wire No 0

1

2

0 0 0 0

1 1 1 1

2 0 0 0

B A 0 1 2

0 0 1 0

1 1 0 1

2 0 1 0

B A 0 1 2

0 0 1 2

1 1 2 0

2 2 0 1

B A 0 1 2

0 0 0 0

1 0 0 1

2 0 1 1

A

B

1

0

0

1

1

2

2

S

4

0

0

0

0

0

5

1

4

1

4

1

2

2

0

2

3

2

C

21452 20040 10012 21043 Numeric representation of columns (controlled wire no, controlling wire no, x-shift, y-shift, z-shift)

Figure 3.28: Realization of ternary half-adder function c(A,B)= [0,0,0,0,0,1,0,1,1]T and S(A,B)= [0,1,2,1,2,0,2,0,1] T using cascades of GTG gates. By adopting this method any ternary logic function can be realized.

References 1.

Hallworth RP, Heath FA. Semiconductor circuits for ternary logic. Proc. IEE Monograph. 1961; 219-223.

2.

Resonant Tunneling Device Logic Circuit technical report July 1999.

3.

Fay P, Bernstein HH, Chow D. Integration of InAs / AlSb/ GaSb Resonant inter band tunneling diodes with HFET for ultra high-speed digital applications. Proc. IEEE special issue on Electron Devices. 1999.

4.

Maezawa K, Mizutani T. A new resonant tunneling logic gate employing monostable-bistable transition. Jpn. J. Appl. Phys. 1993; 32: L42.

5.

Shewchuk TJ, Chapin PC, Coleman PD, Kopp W, Fisheer RR, Morkoc H. Resonant tunneling Oscillations in a GaAs-Alr Ga1-rAs heterostructure at room temperature. Appl Phys Lett. 1985; 46; 508-510.

6.

Broekacrt TPE, Fonstand CG. Extremely high current density, low peak voltage, pseudomorphic In0 53 Ga0 17 As/AlAs/ InAs resonant tunneling diodes. Tech. Digest. 1989; 559-562.

7.

Lin YM, Appenzeller J, Knoch J, Avouris P. High-Performance Carbon Nanotube Field-Effect Transistor With Tunable Polarities. IEEE Trans Nanotechnol. 2005; 4: 481.

8.

Rahman A, Guo J, Datta S, Lundstrom MS. Performance evaluation of ballistic silicon nanowire transistors with atomicbasis dispersion relations” IEEE Trans Electron Devices. 2003; 50: 1853.

9.

Akturk A, Pennington G, Goldsman N, Wickenden A. Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor. IEEE Trans Nanotechnol. 2007; 6: 469.

10.

Hashempour H, Lombardi F. Device Model for Ballistic CNFETs Using the First Conducting Band. IEEE Des Test Comput. 2008; 25: 178.

11.

Deng J, Wong HSP. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part I: Model of the Intrinsic Channel Region. IEEE Trans Electron Devices. 2007; 54: 3195.

12.

Guo J, Javey A, Dai H, Datta S, Lundstrom M. Predicted Performance Advantages of Carbon Nanotube Transistors with Doped Nanotubes as Source/Drain. eprint ar Xiv: cond-mat/0309039. 2003.

13.

Lin S, Kim YB, Lombardi F. CNTFET based ternary logic gates and arithmetic circuits. Proceedings of the 52nd IEEE International Midwest Symposium on Circuits and Systems. Cancun, Mexico. 2009; 435.

14.

Chandrakasan AP, Bowhill WJ, Fox F. Design of High- Performance Microprocessor Circuits. IEEE Press, New York. 2001; 290-296.


26

15.

Kim KK, Kim YB. A novel adaptive design methodology for minimum leakage power considering PVT variation on nanoscale VLSI system. IEEE Trans Very Large Scale Integr (VLSI) Syst. 2009; 17: 517.

16.

Raychowdhury A, Roy K. Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans Nanotechnol. 2005; 4: 168.

17.

Appenzeller J. Carbon Nanotubes for High-Performance Electronics—Progress and Prospect. Proc IEEE. 2008; 96: 201.

18.

Mozammel HA Khan, Marek A Perkowski. Evolutionary Algorithm Based Synthesis of Multi-Output Ternary Functions Using Quantum Cascade of Generalized Ternary Gates. International journal on Multivalued Logic and Soft Computing. 2005.


27

CHAPTER 4

SMGr up

Ternary Logic Minimization INTRODUCTION We already discuss in chapter 1 Boolean algebra which is used for synthesis of logical expressions. It is also demonstrated that a logical expression can be realized using the logic gates. The number of input terminals for gate required for the realization of logical expression in general gets reduced considerably if the expression can be simplified. The simplification of logical expression is very important as it saves the hardware required to design a specific system. Basically digital circuits are categories in two ways: 1) Combinational circuits 2) Sequential circuits

In combinational circuit the output at any instant of time depends upon the input present at that instant of time. This means there is no memory in this circuit. There are other type of circuit in which the output at any instant of time depend upon the present input as well as past inputs. This means that there are elements used to store past information. These elements are known as memory. Such circuits are known as sequential circuits. Three methods are adopted for the realization of ternary circuit. 1)

Adaption of Karnaugh map method

3)

Adaption of Scheinman’s Binary method: Adaption to ternary case.

2)

Adaption of Quine method: Adaption to ternary case

STANDARD REPRESENTATION FOR LOGIC FUNCTION Logical functions are expressed in terms of logical variables. The values assumed by the logical functions as well as the logical variable are in ternary form. Any arbitrary functions can be expressed as in Sum of Product (SOP) forms. Equations 4.1 shows SOP form of equation. Y = (A·B·C) + (A·B.C)

FUNCTION MINIMIZATION

(1)

One of the basic of logical design is the simplification of a given function. The problem of


1

determining the optimal representation of a given function is very complicated and has not been solved even for the binary case [1]. For function minimization only the cost factor of switching elements (Transistors / Fetes) is considered. Others factors such as speed of operation of ratability are not considered [2]. Let us define some basic terms that are modifications of their binary equivalents Literal: :

is defined as literal where ai=0, 2, 01, 12, x, 1.

Inclusion: The ternary n- variable function f1 include the ternary n-variable function f2 (Notation:

If for every

f1 ≥ f 2

α Ln f1 (α ) ≥ f 2 (α )

Implicants: Two types of implicants of a ternary n-variable function F are defined.

Φ g is a product of irredundant satisfying the conditions n Φ g (α ) ≤ f (α ) For every α L

1) g-type implicants 2) h-type implicants1.

Φ g (α ) is a product of irredundant literals satisfying the conditions

Φ h (α ) ≤ f (α ) For every α Ln

Primary implicants:

1) A primary g- type implicant: one of the following conditions: for every g- type implicant a) Or

b)

Ψ g of the ternary function f is g- type implicant of f satisfying

Φ g of f

Ψg ≤ Φg ≤ f ⇒ Φg = Ψg

Ψ g (α ) .Φ g (α ) ≤ Φ g (α ) .1

For at least one

α Ln

such that

2) A primary h- type implicant: following conditions

Ψ h .1 ≤ Φ h .1 ≤ f ⇒ Ψ h = Φ h

Ψ g (α ) .Φ g (α ) ≠ 0 and one g-type implicant Φ g of f

Ψ g of the function f is an h- type implicant of satisfying the

For every h- type implicant of f, and

Ψ h .1  Φ g

For every g- type implicant

Φ g of f.


2

A representation of a function f,

f = ∑Φ g + 1.∑Φ h

Where the Φ g and Φ h are g- type implicants of f, respectively, is quasi-basic. If only literals of the type x 0 , x 2 , x 01 , x 02 , x x are included, it is basic.

Simplicity Criterion

Cost function related to a basic representation of a ternary function f is defined as the total cost of the diodes and transistors needed for the realization of the function. A basic representation is called minimal when the value of the cost function is minimal. As stated before we assume the AND (.) OR (+) circuitry to consists of diodes

x

x

And the unary function x 0 , x 2 , x 01 , x 02 realized by one triode (transistor) each. The function is to be simply identical with x.

Theorem 2: Any ternary function f has a minimal basic representation of the form

f = ∑Ψ g + 1.∑Ψ h

Where the

Ψ g and Ψ h are primary g- type and h- type implicants respectively.

∑

∑

Proof: Let f = Φ g + 1. Φ h be a minimal basic representation of the function f, where at least one of the implicants Φ i is not primary. We have only the following two possibilities:

Φi

Is a g-type implicant. Clearly we can find a primary implicant

Φi < Ψ i ≤ f

Ψ g such that

Evidently the basic representation of Ψ does not contain mare literals than g of the type x x which appear in Φ i cannot be replaced by literals of the type Thus, the representation obtained by replacing Φ i by Ψ will also be minimal. g

Φ i Also; literals x ai ai ≠ x in Ψ.

Φ i is an h-type implicant. In this case we can find either a primary h-type implecant Ψ h such

that

Φi < Ψ h

Or a primary g-type implicant Ψ such that g

1.Φ i < Ψ g

Again similar considerations as before show that the replacement of result in a minimal representation of f.

Φ i by Ψ h or Ψ g will

The repeated application of the above procedure will finally lead to a representation as required by Theorem 2.


3

MINIMIZATION BY MAP METHOD Although map methods provide a convenient approach to logical design their applicability in the ternary case is limited due to the large number of combinations, to functions of up to three variables.

Two Variables Maps

A two-variable map is given in Figure 4.1. The outputs C1… C9 can have the values where d stands for “don’t care.” Arrays of 3 ×1,3 × 2,3 × 3,1× 2, and 2 × 2 cells of the map correspond to implicants of the two-variable function, represented by the map. Similar to the binary case the principle of the map Methods-consists, therefore, of joining corresponding cells into arrays large as possible. The corresponding implicants will be written in the form F= g+h.1

The joining of cell is carried out according to the rules.

1) Arrays of 3x1, 3x2 or 3x3 cells may be formed provided the output values coincide with the values of one of the inputs. 2) It permitted to join (properly) adjacent cells with equal output values. 3) Multiple uses of cells for different arrays are permitted.

4) Cells with the output value 2 can be considered as “don’t care” for the formation of arrays with the output value 1.

Example: a map representing a two –variable ternary function is shown in Figure 4.2. The arrays selected are also included in this figure 4.2. Thus the resulting representation of f is

f = x22 + x101x11 2 x12 2 + 1.[ x101 + x20 ]

Three-variable maps For three variables functions we can draw a three-dimensional map Figure 4.3. But it is more convenient to use the two dimensional map shown in Figure 4.4. In this map Ci is considered adjacent to and but not to the method of using this map is similar to the two variable case and will now be illustrated by an example. Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

4

Example: A ternary three –variable function is represented in Figure 4.5. The arrays marked lead to the following results.

f = x10 .x2 .x30 + x10 .x12 .x312 + 1⋅ x10

Examples on MAP Minimization Method Example 1) Design a circuit for ternary output using map method that will have intermediate level output only when one of the inputs is 1.

Solution: Let A and B be the two inputs. Truth Table 4.1 for the circuit is given below along with K-map.

By considering above truth table using ternary algebra, we can write output equation for 1’s term as F = A0 B1 + A1 B 0 + A1 B1 + A1 B 2 + A2 B1 which is not justified output for circuit implementation as more number of logic gates are required. By using map minimization technique we can reduce number of logic gates required for circuit implementation. Figure 4.6 shows K-map for truth Table 4.1

K -map for Table 4.1

According to rules explained in above, we can groop all 1’s term. There is no ant 2; s term for grouping. Therefore the output equation becomes F = 0 + 1• ( A1 + B1 ) . Figure 4.7 shows circuit implementation for truth Table 4.1


5

Figure 4.7: Circuit implementation for truth Table 4.1

Example 2) from the given truth Table 4.2, writes k-map, derive minimized output equation and implement the circuit.

Solution: Referring to k-map here grouping of 2’s and 1’s is possible. As per the rules explained above of 2’s as 3x2 is shown by simple bracket and 1’ by 1x3 using simple bracket. Therefore the final minimized output equation is F = A0 + A2 + 1• ( A1 ) . The circuit for given output equation is shown in Figure 4.8. The examples on three variable k-maps are given in chapter 5. Truth Table 4.2:

(a)

(b)

Figure 4.8: (a) K-map for truth table (b) Circuit for given K-map.

THE QUINE METHOD: ADAPTION TO TERNARY CASE

By theorem 2 it is obvious that a minimal basic representation of a given ternary function may be obtained from its primary applicants. We shall now discuss a method of deriving all primary applicants which is an adaptation of Quine’s binary procedure [3].The method suggested is systematic and can be easily mechanized. Furthermore, the procedure can be started from any basic representation. Let us introduce some additional concepts required in the sequel.


6

The following definitions refer to implicants of a given ternary n-variable function f.

Disjoint Pmplicants 1)

Two g-type implicants

Φ gj = x1 j1 …..xi ji …..xn jn a

a

a

Φ gk = x1 j1 …..xiaki …..xnakn a

Are disjoint in the coordinate i, if

xi j1 .xiaki ≠ 2 a

Example: The two g-type implicants

Φ g1 = x10 .x12 .x3x .x42

1 x Φ g 2 = x12 .x12 2 .x3 .x4

Are disjoint in the coordinates 1 and 3 2)

Two h-type implicates

Φ hj = x1 j1 …..xi ji …..xn jn a

a

a

Φ hk = x1ak 1 …..xiaki …..xnakn Are disjoint in the coordinates i, if

Example: The two h-type implicants

Φ h1 = x10 .x12 .x3x .x42

1 x Φ h 2 = x11.x12 2 .x3 .x4

Are disjoint only in coordinate 1 Consensus Let

Φ k and Φ l ,

Φ k = x1ak 1 …..xiaki …..xnakn

Φ l = x1al 1 …..xiali …..xnaln Be two implicants of the same type and i any coordinate. x

If the literal xi appears in an h-type implicants we first replace it by change the function f)

xi12 . (This step does not


7

If now for every coordinate j, j ≠ i, the two implicants are not disjoint, the coordinate i satisfy

xiaki + xiali = xiα

α = ∆, 01,12 The consensus in the coordinate i (notation: Φ

i Φ m = Φ k Φ l = x1a1 …..xiα …..xnan *

Where

k

i Φ l ) is obtained by *

x j j = x j kj .x j lj , j ≠ i a

a

a

Joining of implicants

Consider a g-type implecant

Φ g = x1 g 1 …..xi gi …..xn gn a

a

a

Φ g and an h-type implicant Φ h

Φ h = x1ah1 …..xiahi …..xnahn Where agi “contains” the value 2, ahi the value 1(ai = 12 “contains” 1 and 2,ai = Δ “contains” the value 0,1,2 etc.) and for every coordinate j , j ≠ i at least one value of xi satisfies the condition

x j gj .x j hj = 2 a

a

The joining of

Φ g and Φ h in coordinate i is then defined by

i Φ g Φ h = x1a1 …..xix …..xnan 0

And

x j j = x j gj .x j hj , j ≠ i a

a

a

Example: Let

01 Φ g = x10 .x12 2 .x3

Φ h = x101.x12 .x31 For the coordinate 2 the conditions for joining are satisfied and

2 Φ g Φ h = x10 .x2x .x31 0

We now discuss some properties of consensus and the join.

Theorem 3: Let coordinate i. Then

Φ j and Φ k be two implicants of the same type, having a consensus in the

i Φ j Φ k ≤ Φ j + Φ k *

Proof: Let

Φ j = x1 j1 …..xi ji …..xn jn a

a

a


8

Φ k = x1ak 1 …..xiaki …..xnakn We define

¯

Φ j = xi ji Φ j a

¯

Φ k = xiaki Φ k It is clear that ¯

xi ji Φ j ≤ Φ j + Φ k a

And therefore ¯

¯

xi ji . Φ j Φ k ≤ Φ j + Φ k a

In a similar manner we obtain ¯

¯

xiaki Φ j . Φ k ≤ Φ j + Φ k

By addition of the last two equations we obtain

(x

a ji i

)

¯

¯

+ xiaki Φ j . Φ k ≤ Φ j + Φ k

The expression appearing on the left–hand side of the inequality is by definition the consensus in the coordinate i. The theorem is thus proved.

Theorem 4: Let coordinate i. Then

Φ g be a g-type implicant and Φ h an h-type implicant having a join in the

i Φ g Φ h = Φ g + 1.Φ h 0

The proof is similar to that of theorem 3.

As an immediate result of theorem 4 and 5 we obtain the following.

Theorem 5: A ternary function f given in a quasi-basic representation will not change if the following implicants are added: 1) g-type implicants which are the consensus of two g-type implicants or the join of a g-type implicants and an h- type implicants. 2) h-type implicants, which are the consensus of two h-type implicants.

Algorithm for determining all the primary implicants

Let f be a ternary n- variable function given in any quasi –basic representations.

f = ∑Φ gi + 1.∑Φ hi

It is clear that we can represent this function in the following way:

  f = ∑Φ gi + 1.  ∑Φ hi + ∑Φ gi  d  


9

The expression ∑Φ gi indicates that the combinations corresponding to the d as “don’t care” states for the computation of ∑Φ hi .

Φ gi –scan be taken

We shall define two operations that can be carried out on the representations ( ) without changing f. Let the representation contain g- type implicants

Φ gi ≤ Φ gj Or Φ gi .Φ gk  Φ gk .1

Φ gi , Φ gj , Φ gk , i ≠ j , i ≠ k such that

For at least one combination of the variables where

Φ gi .Φ gk ≠ 0 then Φ gi can be cancelled.

Alternatively let the representation contain h- type implicants

Φ hi ≤ Φ hj , i ≠ j

Φ hi , Φ hj such that

Or

1.Φ hi ≤ Φ gj

Where

Φ gj is a g- type implicants of (57).Then Φ hi can be cancelled.

2) If a consensus or a join can be formed from two implicants of the representation [3] the resulting implicant can be added.

Theorem 6: By the iterative use or the above operations on a ternary function f, representation as in () a quasi-basic representation is obtained containing all the primary implicants and only such implicants.

f.

Proof: It is obvious that the use of the above two operations does not change the given function

We now show that if a primary implicant Ψ of f is not yet included in the representation, the i procedure is not yet terminated. For this purpose we have to distinguish between the following cases. Case 1: let us assume that there exists a g- type primary implicant In the representation, i.e.

Ψ g that does not yet appear

Ψg ≤ f

Ψ g  Φ gi For every

Φ gi in (19)

Case 1a: No g- type implicant

Φ g of f properly includes Ψ g .

In this case there must exist a g- type implicants

1)

Φg ≤ Ψg

such that


10

2) Φ 3)

g

 Φ gi

Φ g Does not properly include an implicant satisfying (2)

Two alternatives are still possible.

Φ g Contains literals of all the variables where exactly one of the literals is of the type x0, x1 or

x2 Let

Φ g = a1a1 …..aiai …..anan

Where ai = 01 or 12

We can separate this expression into the two following ones:

Φ g1 = x1a1 …..xiai1 …..xnan

Φ g 2 = x1a1 …..xiai 2 …..xnan Such that

xiai1 + xiai 2 = aiai xiai1 .xiai 2 = 0

Due to property 3 of form ¯

Φ g the representation must contain implicants Φ gj and Φ gk of the

Φ gj = xibi1 Φ gj ¯

Φ gk = xibi1 Φ gk Where

xibi1 ≥ xiai1 xibi 2 ≥ xiai 2

We can separate this expression into the two following ones:

Φ g1 = x1a1 …..xiai1 …..xnan

Φ g 2 = x1a1 …..xiai 2 …..xnan Such that

xiai1 + xiai 2 = aiai xiai1 .xiai 2 = 0

Of

Φ g the representation must contain implicants Φ gj and Φ gk of the form

Where


11

xibi1 ≥ xiai1 xibi 2 ≥ xiai 2 And the literals of

Φ gj and Φ gk are part of the literals appearing in Φ g

Hence the following consensus may be formed.

i Φ g1 = Φ gj Φ gh ≥ Φ g *

Where

Φ g1  Φ gi

Thus the second operation is possible.

Φ g Contains literals of all the variables when exactly one of them is of the type x x and all the other of the type x 0 , x1orx 2 . i) We can show similarly to a) that a join may be added. Clearly these two alternatives are the only that can exist. Case 1b: Ψ doesn’t satisfy the conditions of case 1a but g

Ψ g .Φ gj ≤ Φ gj .1

For at least one combination of the variables, such that Ψ .Φ g j implicants Φ gj . In this case the representation must contain at least one

Ψ g .Φ gi ≤ Φ gi .1

For at least one combination of the variables such that The same

i Ψ g Φ gi 0

≠ 0 , and at least one g- type

Φ gj such that

Ψ g .Φ gi ≠ 0 .

Φ gi appears in the expression 1.∑Φ gi and therefore the join may be added. d

Case 2: There exists an h-type implicant Ψ not contained in the representation. Similarly to h case 1 it is easily shown that a consensus may be added. (Note: a literal

xix appearing in an h-type implicant can be changed, as we have seen, to xi12 .)

Let us now show that it is impossible for the procedure to terminate as long as the representation contains an implant Φ i which is no primary. As every implicant Φ which is not i primary is included by primary implicant there are two possibilities. 1) This primary implicant appears in the representation and

Φ i can therefore be cancelled.

2) This primary implicant does not yet appear and therefore the procedure is not yet terminated.


12

It is also clear that the procedure is finite. Implicants which have been cancelled will not be added again implicants, and which have been added once will not be added again. The applications of the algorithms described will be illustrated by an example. The following three variables ternary function is given: Example 3) Suppose given ternary function is:

f = x10 .x20 .x30 + x11.x12 .x30 + x10 .x22 .x30 + x12 .x22 .x30 + x10 .x20 .x31 + x12 .x22 .x31 + x10 .x20 .x32 + x11.x12 .x30 + x11.x22 .x30 + 1.  x12 .x12 .x31 + x12 .x12 .x32 + x12 .x22 .x32 + x10 .x22 .x32  +  x11.x20 .x32 + x11.x12 .x32 + x11.x22 .x32  d

The brackets marked by d correspond to “don’t care” combinations.

The given implicants are written in two separate columns, one for the g-type and the second h-type implicants. The implicants corresponding to the “don’t care” combination will be marked by d. Obviously all the g-type implicants appear as d’s in the h column.

To simplify the notations we shall indicate an implicant x1a1…x2a2… by the a’s only. The literal x12 will be written as2, the literal x01 as 0 and x∆ as ∆. For example, the four variable implicants

will be written as 01⊗2. x101.x12 .x12 4

The procedure is best started from g-type implicants. All the g-type implicants may then be added as “don’t care” to the h column.

Clearly an implicant obtained from “don’t care’’ implicants only is also a “don’t care’’ implicants. Throughout this procedure “don’t care” implicants obtained must be marked as such (by the letter‘d’) this information is of course essential for the last step, the selection of the primary implicants. Figure 4.9 shows the complete procedure of forming consensus implicants from g-type implicants of f. This figure indicates how every implicant is obtained or cancelled.

Not every implicant added entails the canceling of the original implicants. For example the addition of implicant 9, obtained from implicant 1 and 3, results in their canceling. However, implicant 11 is obtained from 2 and 9 but only implicant 2 may be cancelled after implicant 11 has been added. Implicant 12 is obtained from 5 and 7 but neither of the original implicants can be cancelled.

The procedure for h-type implicants is similar. After adding all g-type implicant marked as‘d’, the list shown in Figure 4.9 is obtained. The next step consists of generating all join-implicants. Figure 4.10 gives this procedure. The two columns are listed again (cancelled implicants have been omitted.)

Let us examine some examples. The g-type implicant (0 ∆ 0) can be joined with 0 ∆ 0 (d) which appears in the h column. The result 0 X 0 is included by 0 ∆ 0, but it satisfies the condition (0 X 0). (0 ∆ 0) ≤ 0 ∆ 0.1


13

For at least one input combination. Therefore 0 X 0 is primary, and thus added to the list. Another join implicant is 2 X 1, 2 2 0 2 22= 2 X 1

This expression is not included by any other g-type implicants appearing in the representations and satisfies therefore the first condition for primary implicant. It is clear that the implicant obtained by joining “don’t care’’ implicants need not be added.

Having reached the stage where it is no longer possible to apply the operations of the algorithms, we know by theorem 6 that all the primary implicants of the function have been derived. The function may now be represented as sum of all its primary implicants. Implicants known “don’t care” are of course, omitted at this stage. The result according to Figure 4.10 is

f = x10 .x30 + x101.x122 .x30 + x101.x20 .x32 + x10 .x20 + x12 .x22 .x301 + x22 .x30 + x101.x2x .x30 + x10 .x20 .x3x + x12 .x2x .x301.x312 + x1x .x22 .x30 + x101.x112 .x2x .x32 + 1.  x12 .x122 .x312 + x22 .x32 + x112 .x122 .x32 + x12 .x22 

Figure 4.9: The joining procedure.

Figure 4.10: The consensus finding procedure for g-type & h-type implicant. Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

14

The last step of the implification procedure is the selection of a minimal cost basic representation out of the list of primary implicants. The application of McCluskey’s method to our example yields the following representations: 0 0 0 2 2 01 2 12 12  2 2  f = x101.x12 2 .x3 + x1 .x2 + x1 .x2 .x3 + 1.  x2 .x3 + x1 .x2 .x3 

Procedure for Minimization Comparing with other minimization techniques it will be found that the ‘_’ variable of the redundant term takes three possible values 0, 1 and 2 in the triplet of three other forms. The remaining (n-1) variable of the redundant term are each identical to the corresponding (n-1) variable of the triplet, where “_” in any of the triplet term is taken as being equal to 0, 1, 2for purpose of identity comparison. Minimization procedure for the function z= ∑ABCDE……..

1. Expand each term of given or function into all its minimum polynomials (e.g. x12 x31 x14 + x20 x42 + x11 x20 x32 = 2011 + 0002 + 1020) since x2 is absent it is treated as 0 and so on for remaining variables.

2. Add together the values of each of the n variable in each midterm and establish the order of each mean term. 3. Make column of the all midterms

4. Delete the each duplication in each column

5. Compare each term in the column with all other term in next other columns.

6. For forming the decimal order, write order 1 such that alembic sum of total no of variable is one under order one, repeat the procedure for decimal order till final order get obtained. In this case it is 6. 7. Repeat the procedure 4,5 and 6 till term looking for complete variable is obtained. 8. The remaining terms shows the final minimized result. Example 4) given ternary four variable function

f = x12 x31 x14 + x20 x42 + x11 x20 x32 + x11 x20 x40 + x11 x20 x30 x14 + x11 x31 x14 + x22 x14 + x11 x12 x14 By expanding above terms, we can sum up midterms as:

x12 x31 x14 2011 2111 2211

x20 x42

0002 1002 2002 0012 1012 2012 0022 1022 2022

x11 x20 x32 1020 1021 1022

x11 x20 x40 1000 1010 1020

x11 x20 x30 x14 1001

x11 x31 x14 1011 1111 1211

x22 x14 0201 1201 2201 0211 1211 2211 0221 1221 2221


x11 x12 x14 1101 1111 1121

15

Tabulating in resultant decimal order Decimal order

0

List of all midterms

_

1

1000

2

3

1010 0002 1001

1020 1002 0012 1020* 1011 0201 1101

4 2002 1012 1021 1111 1201 1111* 0022 0211 2011

5 2012 1022 1211 2201 1121 1022* 1211* 0221 2111

6

2022 2211 1221 2211

7

8

2221

_

Compare each term with all other terms looking for complete variable. 1000 1001 1002 1001001 1101 1201 1-01 1011 1111 1211 1-11 1021 1121 1221 1-21 0221 1221 2221 -221

Tabulating above lines in ‘-’ order. xxx-

100101102-

1000 1010 1020 10-0 1001 1011 1021 10-1 0201 0211 0221 02-1 1201 1211 1221 12-1 2011 2111 2211 2-11

0002 1002 2002 -002 1020 1021 1022 1020201 1201 2201 -201 0022 1022 2022 -022

xx-x 10-0 00-2 10-1 10-2 02-1 11-1 20-2 12-1 22-1

0002 0012 0022 00-2 1002 1012 1022 10-2 1101 1111 1121 11-1 0211 1211 2211 -211

1010 1011 1012 1010012 1012 2012 -012 2002 2012 2022 20-2 2201 2211 2221 22-1

x-xx

-xxx

1-01 1-11 1-21 2-11

-002 -102 -201 -022 -211 -221

Comparing each term in each column, looking for complete variable 10010110210-02-1 12-1 22-1 -2-1

Tabulating above surface in ‘-’ order. xx--

10--

x-x-

10-0 10-1 10-2 10-1-01 1-11 1-21 1--1

00-2 10-2 20-2 -0-2 -002 -012 -022 -0-2

-xx-

-x-x -0-2 -2-1

10-1 11-1 12-1 1--1 -201 -211 -221 -2-1

x--x

--xx

1--1


16

No further variables are available in above tabulation. Therefore this is the minimization, as terms by themselves. Therefore given expression for output is:

f = x11 x20 + x42 x20 + x22 x14 + x11 x14 + x12 x31 x14

SCHEINMAN’S BINARY METHOD: ADAPTION TO TERNARY CASE By following the method [3], which is an adaptation of Scheinman’s binary method [4], near to optimal solutions can be derived. The advantage of this method is that the procedure is m previous one, as some of the primary nonessential implicants are cancelled automatically during the simplification process. Here, again the last step is the selection of a minimal representation from the list of implicants obtained. This selection is made in the same way as in the modified Quine procedure described in the previous section. On the other hand this method is only applicable to function given in canonical sum form.

The method is based on the iterated use of the expansion Theorem. The given function is again separated into g-type and h-type implicants. i.e,

f = g + 1.h

Each of these secondary functions, g and h, can be expanded in the following way:

g ( x1 , ….., xn ) = x10 g ( 0, x2 , ….., xn ) + x11 g ( 0, x2 , ….., xn ) + x12 g ( 0, x2 , ….., xn )

and similarly for h.

The following explanations deals with the g function. Clearly the same considerations apply to the h function also. The expansion of g about x1 can be written as

g ( x1 , ….., xn ) = x10 r0 + x11r1 + x12 r2

The residue functions r0, r1 and r2are, of course, sums of implicants. We distinguish between the following possibilities.

1)

The three residue functions are equal

r0 = r 1 = r 2 = r

In this case we write

g = x10 r0 + x11r1 + x12 r2 = ( x10 + x11 + x12 ) r = r

This means that the appearance of x1 in the secondary function g is not required. 2)

There exists a residue function r such that

r ≤ r0


17

r ≤ r1 r ≤ r2 In this case

g = x10 ( r0 − r ) + x11 ( r1 − r ) + x12 ( r2 − r ) + r

Where e.g., 1)

r0 is r are the impliants of r0 not appearing in r?

There exists a residue function r such that

r ≤ r0 r ≤ r1

Or

r ≤ r1 r ≤ r2

In this case

g = x10 ( r0 − r ) + x11 ( r1 − r ) + x12 r2 + x101.r

Or

g = x10 r0 + x11 ( r1 − r ) + x12 ( r2 − r ) + x112 .r

2) If none of the above conditions are satisfied the original expansion of g about x1 is left unchanged,

g = x10 r0 + x11r1 + x12 r2

The Scheinman’s technique is based on the iterated use of the above expansion rules. Product of literals

x1a1 , …., xnan appearing in the canonical sum form are called atoms.

The atoms will be written in two columns corresponding to g-type and h-type atoms. They will be denoted the same way as previously, e.g., x10 .x12 .x32 is written as 012. “Don’t care” atoms are marked by√. The g atoms are also included in the h column, marked by√.

Following are the Simplifications Rules

1) The first expansion is about x1. The column considered (g or h) is split into three columns with the headings x10 , x11 and x12 . The entries in these columns correspond to the atoms containing x10 , x11 or x12 , respectively. Only the exponent of x2, ….,xn are listed in these sub columns. 2) Entries derived from “don’t care” entries are also marked as such. 0

1

3) If the columns of x1 and x1 contain the same entry this entry is also listed an additional column with the heading x 01 , and the original entries are marked by√. Similarly if the same entry 1


18

1

appears in both the x1 and x12 columns it is also listed in an additional column x112 and the original entries are marked by√. If an entry appears in all the three columns x10 , x11 and x12 it listed in both the columns x112 and furthermore in a new column x1 . In the three original columns and in the columns

12 x101 and x1 this entry is marked by√.

4) Entries appearing in corresponding positions in the expansion for g and h are now examined. 1 2 If the same entry appears in column x1 in h and column x1 in g it is listed in an additional column x . in g headed by x1 , and the original entries are marked by

If the same entry appears both in the column.

x1 and x1x columns in g, it is marked by √ in the x1x

5) If all entries of a column are marked√, the column is cancelled.

6) Each of the derived columns is expanded about x2 and so forth, for the other variables.

In the expansion about the last variable all the residues are ∆ (where ∆ denotes nonappearance). At the end of this procedure the resulting implicants are found by moving upwards from any lowest entry which has not been cancelled and writing down the product of the literals heading the columns we pass while moving upwards.

The result obtained is the sum of g-type and h-type primary implicants. Although not all the primary implicants appear, it can be easily seen that the essential do. Clearly as not all the primary implicants appear only near –to – optimal representation can be expected. The complete procedure above is illustrated with the example. Example 5)

f = x10 .x20 .x30 + x10 .x12 .x30 + x10 .x22 .x30 + x10 .x20 .x31 + x10 .x20 .x32 + x11.x12 .x30 + x11.x22 .x30 + x12 .x22 .x30 + x12 .x22 .x31 + 1.[ x12 .x12 .x31 + x12 .x12 .x32 + x12 .x22 .x32 + x10 .x22 .x32 ] +  x11.x20 .x32 + x11.x12 .x32 + x11.x22 .x32  d

Scheinman’s method simplification procedure


19

The result is therefore

0 2 0 2 2 01 2 2  2 12 12 12 12 2  f = x10 .x20 + x10 .x30 + x101.x20 .x32 + x101.x12 2 .x3 + x2 .x3 + x1 .x2 .x3 + 1.  x1 .x2 .x3 + x1 .x2 .x3 + x2 .x3 

Example 6) Consider full adder Table 4.3 for minimization by using modified Schiman binary method. Truth table 4.3

xo 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2

x1 0 0 0 1 1 1 2 2 2 0 0 0 1 1 1 2 2 2 0 0 0 1 1 1 2 2 2

Cin= x2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2

Sum 0 1 2 1 2 0 2 0 1 1 2 0 2 0 1 0 1 2 2 0 1 0 1 2 1 2 0

Carry out 0 0 0 0 0 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 2


20


21

In this example the procedure yields all the implicants participating in the minimal-cost representation obtained previously and will therefore lead to the same solution. However, this is not true in general. Ternary switching appears especially promising connection with control circuits, coding circuits as special purpose computers. Further investigations as the advantage of such application are recommended.

There are other minimization methods described by [5-7]. T .C. Yang & A. S. Wojcik have suggested an algorithm for the minimization of ternary switching function which gives all prime implicants and a minimal cost static and dynamic hazard free ternary switching function. P.W. Besslich [6] described a heuristic method to obtain near minimal covers of multivalve switching function. S. C. Kleen [7] has described Algebra for regular ternary logic function. Y. Yamamoto and M. Mukaidono [8] considered special ternary functions for treating ambiguity in circuits.


22

References: 1. Caldwell SH. Switching Circuits and Logical Design. New York: Wiley. 1958. 2. McCluskey EJ, Bartee TC. A Survey of Switching Circuit Theory. New York: McGraw-Hill. 1962. 3. Yoeli M, Rosenfeld G. Logical Design of ternary switching circuits. IEEE Trans Computer. 1965; 14: 19-29. 4. Scheinman AH. A method for simplifying Boolean function. The Bell system technical journal. 1962; 1175-1480. 5. Yang TC, Wojcik AS. A minimization Algorithm for ternary switching functions. Tutorial on MVL minimization. 6. Besslich PW. Heuristic Minimization of MVL functions. A Direct Cover Approach. IEEE Tran On Computer. 1985; 35: 130-143. 7. Leen KSC. Introduction to mathematics. Amsterdam: North Holland. 1952; 332-340. 8. Yamamoto Y, Mukaidono M. Meaningful Special classes of Ternary logic functions Regular Ternary Logic Functions –Regular Ternary Logic Functions & Ternary Majority Function Proc. IEEE Tran Computer. 1988; 37: 799-806.


23

SMGr up

CHAPTER 5

Combinational Logic Design INTRODUCTION A combinational circuit consists of input variables, ternary logic gates and output variables. The output of the circuit depends only upon the present input. Logic gates accept signals from the input variables and generate output signals. This process transforms ternary information from the given input data to the required ternary output data. Figure 5.1 shows the block diagram of a combinational circuit.

Figure 5.1: Ternary combinational circuit.

For the operation of ternary circuit, an additional ternary to unary block converter is essential to convert ternary input to its unary values, describe in the next section. In this chapter design examples using ternary logic for balance ternary operation are given. These are ternary half adder, full adder, full subtract, comparator, multiplier, transmission gate, Multiplexer/Demultiplexer and arithmetic logic circuits.

SYNTHESIS, MINIMIZATION AND REALIZATION PROCEDURE FOR TERNARY SWITCHING FUNCTION

According to theorem 1 [93] any ternary function F( x1x2 ….xn ) may be generated from x1x2…. xn by canonical sum form is

F( x1x 2 ….xn) = F2( x1x 2 …..xn) + 1. F1( x1x 2...xn)

Here F2 is a function containing terms 2’s or 0’s & F1 containing terms 1’S & 0’S. So, if function table is known for ternary operation, any function can be synthesized from function table. Three basic methods to minimize ternary function are 1) 2)

Manipulation of algebra expression as in Boolean algebra. The tabular method.


1

3)

Ternary K. map method.

Out of these methods, ternary K.map method is adopted in this book for function minimization.

For the implementation of ternary circuits it is necessary to convert ternary variable in to unary variable. It is shown in Figure 5.2 and truth table in 5.1

Ternary variable input x

Table 5.1: Truth table for converter.

0

Ternary unary output X1 X2

X0

2

0

0

1

0

2

0

2

0

0

2

Figure 5.2: Ternary to Unary converter.

Ternary to unary decoder is a circuit build using ternary to unary converter and ternary to unary conversion is carried out using T-Inverters and OR gates.

HALF ADDER DESIGN

Ternary half adder is a circuit for the addition two 1 trit numbers is referred to as a half adder. Circuit does not consider a carry generated in the previous addition. Table 5.2 expresses the addition process in ternary logic system. Here A and B are two inputs and sum(S) and carry (C) are two outputs. Since no grouping of 2’s and 1’is possible, the output equation is as below. Table 5.2: Truth table for half adder. INPUT A

B

0 0 0 1 1 1 2 2 2

0 1 2 0 1 2 0 1 2

OUTPUT SUM CARRY S C 0 0 1 0 2 0 1 0 2 0 0 1 2 0 0 1 1 1

Figure 5.3: K-map for Half Adder.


2

Equation for Sum and Carry can be find from map as,

SUM = A2 B 0 + A1 B1 A0 B 2 + 1 • ( A1 B 0 + A0 B1 + A2 B 2 ) and CARRY = 0 + 1 • ( A2 B1 + A1 B 2 + A2 B 2 )

Figure 5.4: Half-Adder implementation using T-gates.

The grounding terminal of sun and carry shows logical grounding of logical 1 for balance system. Decoder block is ternary to unary decoder.

FULL ADDER DESIGN

A ternary full adder is a circuit that adds two inputs and previous carry generated. Truth table for full adder is given in Table 5.3 along with K-map in Figure 5.5, 5.6 shows full adder implementation. Table 5.3: Truth table for full adder. INPUT

A

B

C

0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2

0 0 0 1 1 1 2 2 2 0 0 0 1 1 1 2 2 2 0 0 0 1 1 1 2 2 2

0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2

OUTPUT SUM CARRY S C 0 0 1 0 2 0 1 0 2 0 0 1 2 0 0 1 1 1 1 0 2 0 0 1 2 0 0 1 1 1 0 1 1 1 2 1 2 0 0 1 1 1 0 1 1 1 2 1 1 1 2 1 2 2


3

Figure 5.5: (a) Map for full adder SUM

K-map equations for sum and carry are to be,

(b) Map for full adder CARRY with grouping.

SUM = A2B0C0 +A1B0C 1+A0B0C2+ A1B1C0+ A0B1C1+A2B1C2 +A0B2C0 +A2B2C1+ A1B2C2 +1 (A1B0C0+A0B0C1

+A2B0C2+A0B1C0+ A2B1C1+ A1B1C2+A2B2C0+A1B2C1+ A0B2C2)

CARRY =A2B2C2 +1 (A2C2 +A0B2+A2B2 +A1C2 +A2C1 +B2C1 +B1C2 +B2C2 +A1B1C1)

Figure 5.6: Full adder implementation.

FULL SUBTRACTOR

Ternary full-Subtractor is a circuit that subtracts two inputs & previous borrow. Truth table for Subtractor is given in Table 5.4 & k-map in Figure 5.7 Minimized equation for the Subtractor is

Subtraction = B00[ X10.X21+ X12 .X11 .X22 ] + B01 [X10 .X20 + X11 .X21 + X12 . X22] + B02 [X11 .X20 + X10 .X22+ X12. X21] +1. [B00[X11 .X20+ X12. X21+ X10.X22] + B01 [X10 .X20 + X11 .X22] + B02 [X10.X20+ X11.X21

X12 . X22]] Borrow = B02 [2[X21+X22]]+ 2[X10X12+X10X22] +2·[X11X22] +X12X22 B01 +X11X20B02 Ternary Digital System: Concepts and Applications | www.esciencemedicine.com/ebooks

4

Figure 5.7: k-map for Full Subtractor.

Table 5.4: Truth table for Subtractor.

Figure 5.8: circuit implementation of Full-Subtractor.


5

TERNARY COMPARATORS Ternary comparator circuit camper two input X1&X2& according generates output as X1=X2, X1>X2, X1X2, & X1< X2 are FX1=X2 = X10X20 +X11+X12+X22X22

FX1>X2 = X11X02+X21X02+X21X21 FX1x2(c) x1B or A

Ternary Digital System Concepts and Applications AP

Ternary Digital System Concepts and Applications AP

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