ISSN 1292-862
TIMA Lab. Research Reports Generation of Electrically Induced Stimuli for MEMS self-test
B. CHARLOT*, S. MIR*, F. PARRAIN* and B. COURTOIS
* TIMA Laboratory, 46 avenue Félix Viallet 38000 Grenoble France
ISRN TIMA-RR--02/02-1--FR
TIMA Laboratory, 46 avenue Félix Viallet, 38000 Grenoble France
Generation of Electrically Induced Stimuli for MEMS self-test Benoît Charlot, Salvador Mir, Fabien Parrain and Bernard Courtois
TIMA laboratory 46 Avenue Felix VIALLET 38031 GRENOBLE, France Fax +33 4 76 47 38 14 http://tima.imag.fr
[email protected] [email protected] [email protected] [email protected]
Tel +33 4 76 57 46 12 Tel +33 4 76 57 48 95 Tel +33 4 76 57 49 23 Tel +33 4 76 57 45 00
Abstract A major task for the implementation of Built-In-Self-Test (BIST) strategies for MEMS is the generation of the test stimuli. These devices can work in different energy domains and are thus designed to sense signals which are generally not electrical. In this work, we describe, for different types of MEMS, how the required non-electrical test stimuli can be induced on-chip by means of electrical signals. This provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems. The on-chip test signal generation is illustrated for the case of MEMS transducers which exploit such physical principles as time-varying electrostatic capacitance, piezo-resistivity effect and Seebeck effect. These principles are used in devices such as accelerometers, infrared imagers, pressure sensors or tactile sensors. For implementation, we have used two major MEMS technologies including CMOS-compatible bulk micromachining and surface micromachining. We illustrate the ability to generate on-chip test stimuli and to implement a self-test strategy for the case of a complete application. This corresponds to an infrared imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a suspended membrane that contains several thermopiles along the different support arms. The on-chip test signal generation proposed requires only slight modifications and allows a production test of the imager with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The test function can also be activated off-line in the field for validation and maintenance purposes.
Keywords : self-test, BIST, MEMS test case-studies, MEMS failure mechanisms. 1
Introduction
Micro-Electro-Mechanical-Systems (MEMS) are sensors and actuators made by means of either microelectronic technologies or technologies that have evolved from Microelectronics. In the first case, a standard microelectronic process is followed by a specific micromachining post-process. This is the case for example of CMOS bulk micromachining technologies. In the second case, MEMS are built using dedicated MEMS processes that also use thin layer deposition techniques and specific etching steps. As for Microelectronics, the fabrication of devices embedding MEMS takes advantage of collective fabrication techniques on semiconductor wafers, giving not only the cost reduction typical of scale economies but also the increased sensing accuracy of micron scale devices [1]. The beginning of the MEMS age occurs in the early 80s, when the first micro components fabricated by means of micromachining techniques are developed. It took a full decade before the consumer
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markets saw the first large scale industrial applications, mostly for automotive applications, such as accelerometers, gyroscopes, vibration and pressure sensors, in addition to ink-jet printer heads (which yet today represent the largest share of the MEMS market). At that time, many potential applications were already envisioned in different domains such as micro-surgery, drug-delivery, fluid-monitoring, DNA chips for biomedicine, or many different types of environment monitoring systems for space ships and low weight satellites. With the emergence of stable MEMS technologies in the recent years, most of these devices may today reach large volume markets [2]. Figure 1 illustrates the technologies that we have used for implementation of the MEMS devices in this paper. Figure 1(a) shows a technological cross section for CMOS-compatible bulk micromachining. This technique can be applied directly to processed wafers allowing integration of MEMS and electronics. After the fabrication of the microelectronic layers, an anisotropic wet etching post-process allows suspending a microstructure by creating a cavity on the silicon substrate, without any additional lithographic step. This type of technology is made available, for example, by the CMP MEMS prototyping service [3]. Figure 1(b) shows a technological cross section for surface micromachining. In this case, sacrificial layers are removed after fabrication leaving suspended and anchored microstructures. Examples of this type of technology include the Multi-Users MEMS Processes (MUMPS) from CRONOS/MCNC [4], the SUMMIT technology from SANDIA National Laboratories [5] and an Analog Devices technology [6]. CMOS electronics
MEMS suspended parts
Polysilicon structural layers
Sacrificial oxide layers
SI bulk Anisotropically etched cavity
(a) (b) Figure 1. Technological cross section of main MEMS fabrication procedures: (a) front-side bulk micromachining, and (b) surface micromachining The use of stable MEMS technologies, and the integration of new MEMS layers in standard microelectronic fabrication processes, is making possible the development of complex applications integrating MEMS parts (sensors and actuators) and signal conditioning analog interfaces (such as amplifiers, demodulators, filters or converters) together with large digital cores. This very high level of integration provides many advantages such as miniaturization, reproducibility and improved performance. However, increased levels of integration always raise major test concerns. This is specially true for the case of devices embedding MEMS parts. All techniques developed in the past for the self-test of microelectronic parts will only find their optimal exploitation in the coming generation of highly heterogeneous devices if the self-test of the MEMS parts is also adequately addressed. MEMS are essentially analog and mixed-signal devices. However, they differ from typical analog devices in the fact that they use signals in other energy domains, such as mechanical, thermal or radiant. In order to provide BIST for MEMS, it is then necessary to generate on-chip these stimuli. In this paper, we describe how non-electrical stimuli can be induced on-chip by means of electrical signals. First, Section 2 describes current works in the field of MEMS testing. The on-chip test signal generation is illustrated in Section 3 for the case of MEMS devices which exploit transducer principles such as time-varying electrostatic capacitance, piezo-resistivity effect and Seebeck effect. These principles are used in devices such as accelerometers, infrared imagers, pressure sensors or tactile sensors. The ability of generating on-chip the test stimuli and the implementation of a self-test strategy is illustrated for the case of a complete application in Section 4. This corresponds to an infrared imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking
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for satellite positioning. The on-chip test signal generation proposed requires only slight modifications and allows a production test with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The self-test function can also be activated off-line in the field for validation and maintenance purposes. Finally, Section 5 concludes this paper.
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MEMS testing
As for digital and analog circuits, the test of an integrated MEMS device is a compulsory step for verifying the quality and reliability of a fabricated industrial product. Testing of analog devices typically aims at validating the functionality of the product, verifying that the data sheet specifications are met. In addition, testing is crucial for proving that a product achieves the required level of reliability. In most applications MEMS are used as sensors and the testing phase verifies that data measurement is correct. Testing must be performed in different moments along the life cycle of a product, not only after manufacturing (production testing) but also when the product is used in an actual field application (maintenance testing), in particular just before a critical measurement. This can be specially important for MEMS sensors, for example in the case of devices containing mobile mechanical parts whose long term reliability is not well known. The development of testing methodologies for MEMS is following a similar strategy as has been done in the past for microelectronic circuits [7,18]. The understanding of the different failure mechanisms and manufacturing defects that impact the quality of the integrated products comes obviously first in the efforts in this field [7,8]. Techniques of failure analysis for inspecting MEMS devices have been borrowed from Microelectronics, such as optical microscopy, scanning electron microscopy, focused ion beam or infrared microscopy [9]. Other techniques have been derived specifically for MEMS such as vibration tables for shock testing or nano-indenters for cantilever deflections. Much work is yet to be done for adequate characterization of MEMS components, including in particular ageing effects. The analysis of defects and failure mechanisms leads to the understanding of the device failure modes [10,11] and to the modeling of faulty devices. This is essential for the development and validation of a test strategy. The extreme complexity of the functionality of highly integrated devices has encouraged the use of structural testing approaches as opposed to functional testing. In this approach, potential defects are first identified and next modeled by means of suitable fault models allowing the representation of the faulty behavior. The development of fault models for MEMS devices is yet in its infancy, and researchers have tried to use circuit-level descriptions of MEMS devices to which they can apply similar fault modeling techniques as done in the past for electrical circuits [12,13,14,16]. Fault models are then used in fault simulation using advanced Hardware Description Languages (HDLs) such as HDL-A/Verilog-A [15,17] for describing the faulty behavior. From here, it is possible to obtain by simulation fault coverage figures that validate the quality of the input test vectors [12,15]. The use of self-test techniques for MEMS devices has already been considered in some of the first successful sensors such as airbag accelerometers [19]. Sensors are often required for high safety operation and located in places often difficult to access for periodic maintenance. Adding a self-test function provides an adequate mechanism for improving device reliability and ensuring its correct performance. It can also be used for device calibration. For the case of accelerometers, an electrostatic force is used to displace the suspended mass during self-test [19,20]. In the case of self-testing pressure sensors, displacement of a sensing membrane has been achieved by means of thermomechanical actuation taking advantage of the bimetallic effect [21]. In this paper, we are concerned with the on-chip generation of self-test stimuli for sensors as a first step toward the development of a full BIST strategy in the future. For BIST, all input test vectors and output test signatures are produced and analysed on-chip, typically delivering a go/no-go signal. The BIST approach can be implemented for MEMS parts embedded into the System-on-a-Chip (SoC) devices of the near future, allowing high level test strategies that circumvent the classical problems of accessibility and testability [22]. 3
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Generation of electrically induced stimuli
Most MEMS sense physical signals (acceleration, force, pressure, radiation, … ) and convert them into electrical signals processed by the associated electronics. For self-test, these signals must be generated on-chip during a test phase that must be as short as possible using the most standard test equipment that has only electrical input and output. The goal is thus to find a way to generate on-chip the required physical stimuli under electrical control avoiding the use of specific signal sources. This reduces the requirements in test equipment during manufacturing test and provides the means for the implementation of a self-test function that can be used for field testing. In this section, we will describe for different types of MEMS how to replace the original physical stimuli by an electrically induced stimuli. In this way, it is possible to send electrical test vectors while expecting an electrical signature of the MEMS behavior. The examples shown in this paper make use of parallel plate capacitors for capacitive accelerometers, piezo-resistive components for accelerometers, pressure sensors and tactile sensors, and finally thermopiles for infrared sensors.
3.1 Parallel plate capacitor Parallel plate capacitors are used in different MEMS devices such as capacitive accelerometers or gyroscopes. Figure 2(a) shows an example of a fabricated accelerometer and Figure 2(b) shows a schematic view of the different parts of an open loop capacitive accelerometer. The seismic mass is free to move in the y direction and is attached to the substrate by springs and anchors. When an acceleration is applied to the system the mass will move accordingly and will unbalance the capacitive bridge formed by the movable electrode and the two fixed electrodes, as shown in the equivalent electromechanical circuit of Figure 2(c). For improved measurement of the displacement of the mass, the two fixed electrodes are fed with AC signals in phase opposition that modulate the mass displacement. The voltage in the movable electrode is at analogue ground when the mass is in its central position, and this voltage varies proportionally to the mass displacement. The analog interface electronics performs the amplification, demodulation and analog-to-digital conversion of the measurement voltage. The suspended mass will find its equilibrium position with a response typical of a second-order system. The simulation results of Figure 2(d) show the displacement of the mass and the modulated analog voltage signal. This signal is next amplified and demodulated as shown in the schematic circuit of Figure 2(e). An example of self-test implementation is found in the ADXL Analog Devices series of closed-loop capacitive accelerometers. The activation of a self-test pin sends a voltage impulse to additional interdigitated fingers of the accelerometer, thus inducing an electrostatic force which mimics an acceleration force. The dynamic response at the output is shown in Figure 2(f). The analysis of this response allows the extraction of parameters such as oscillation amplitude, natural frequency and damping coefficient that characterize the system. Faulty behavior caused by catastrophic or parametric faults can then be detected by analysis of this output. Such self-test function is not sufficient for a complete on-chip test since the output must be analyzed outside the chip. However, this function allows verifying the chip without having to use an acceleration bench and using standard analog or mixed-signal testers.
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(e) (f) Figure 2. SEM (a) and schematic (b) views of an open-loop capacitive accelerometer, (c) HDL-based circuit-level description of the accelerometer, (d) simulation results of the electrical and mechanical output for a 50µN square impulse on the mobile mass, (e) signal conditioning circuit for the capacitive open-loop accelerometer, and (f) measurement of the analog output resulting of a logic impulse on the self test pin of a closed-loop Analog Devices accelerometer.
3.2 Piezo-resistive micro-beam A lot of applications of CMOS bulk micromachining technologies are based on piezo-resistive components. The piezo-resistivity is the property of a material to change its electrical resistivity with a mechanical stress. This is represented by different coefficients for the longitudinal and transversal directions. This is similar to the case of a poly crystalline material such as poly Si which is present on
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most CMOS technologies. This property is exploited to sense, by means of a resistance bridge, stresses in a material caused by the bending of a micro-beam under acceleration, pressure or direct mechanical contact. Most integrated MEMS pressure sensors use this technique. More comprehensive systems may contain multiple gauges for acceleration-movement, movement-stress, and stress-resistivity transduction. Figure 3 represents the use of the piezoresistive effect in different types of devices including tactile sensors, accelerometers and pressure sensors. In all of them, the deflection of a suspended part (cantilever or membrane) is detected by means of a resistivity change. For implementing a self-test, there are multiple possibilities to actuate the suspended part: inertial force, electrostatic force, magnetic force, bimetallic deformation, air pressure and direct mechanical contact. But the only one that is easy to implement and electrically induced is the heat induced mechanical deformation of a sandwich of materials with different thermal expansion coefficients. The transduction chain is then: electrical-thermal-mechanical-electric signals. For example, in a piezoresistive micro-beam, we can implement a heating resistor at its suspended end to heat up the sandwich of different dielectric and metallic layers as shown in Figure 4. The difference between thermal expansion coefficients of nitride passivation and other layers will create a stress inside the material. The beam will then bend and the value of the piezo-resistance coefficient will change with the stress. Such a phenomenon is quite complex to model because of the amount of technological coefficients to be taken into account and the fact that they are not normally characterised by the CMOS foundry, in particular the thermal expansion coefficients of the SiO2 and Si3N4 layers. As shown in Figure 5(a), we have performed thermomechanical Finite Element Modeling (FEM) simulations to compare the change of electrical resistance due to both the piezo-resistivity effect and the temperature rise on the piezo-resistor. On one hand, by integration of the longitudinal stresses, obtained by the FEM simulation, along the piezo-resistor we have calculated a resistance increase of 3.73 % due to the piezo-resistance effect. On the other hand, by integration of the temperature values, obtained by the FEM simulation, along the piezo-resistor we have calculated a 2.52 % resistance increase. We can notice that both effects have an impact on the resistance of same sign and similar order of magnitude. Experimental measurements in the same test conditions have been made on the test structures. Figure 5(b) shows the electrical test set up. Figure 5(c) shows the input pulse test signal applied to the heating resistor and the voltage in the resistive bridge used for measurement. A resistance variation of 2.95 % is obtained from this voltage measurement. The downwards bending of the beam is easily seen in the optical microscope, with a frequency that is imposed by the electrical signal in the heating resistor (typically around 10 Hz for observation by a naked eye). This result shows a ∆R/R lower than by simulation, but acceptable due to the lack of precision on thermal expansion coefficients. The thermally actuated micro-beam can be seen as a first-order system with a time constant imposed by the thermal time constant of the microbeam which acts like a heat transmission line with conduction, convection and radiation losses. In our experiments, thermal equilibrium is reached at about 3 ms. The large time constant implies that this test method cannot characterize the dynamic behaviour of the beam which can easily be of several hundreds of kHz. In the case of the piezoresistive accelerometer of Figure 3(b) the micro-beam supports a seismic mass at its end. The presence of this mass will result in a much lower resonance frequency. In this case, thermal actuation with a frequency close to its natural resonance is possible, allowing the characterization of dynamic parameters such as oscillation period. Stresses due to thermal actuation could cause damage in the beam by for example electromigration (in metal or poly layers and vias), creation of voids and cracks in oxide layers, delamination of layers and so on. However, the test conditions we used were quite extreme and close to burn-in. The system worked fine during 6 hours of measurements without any noticeable problem. Thus, a self-test approach based on this method is practical without requiring an excessive power consumption.
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Piezo resistor
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Figure 3. Schematic representation of MEMS applications based on piezo-resistors: (a) piezo-resistive cantilever for tactile sensors, (b) piezo-resistive cantilever with suspended mass for accelerometers, and (c) piezo-resistive membrane (back side etching) for pressure sensors. Cavity edge
Oxide layers micro beam
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Figure 4. SEM photo (a) and schematic view (b) of a micro-cantilever containing a piezo and a heating resistor
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(a) (b) (c) Figure 5. Simulation and experimental test of the thermal actuation: (a) thermo-mechanical FEM simulation showing the temperature distribution in the resistors and the downwards deflection of the beam, (b) oscilloscope snapshot of the voltage variation, (c) schematic of the test set up.
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3.3 Thermopile based sensors Many applications of CMOS-compatible bulk micromachining are based on the use of thermopiles on suspended structures. This is the case of, for example, gas flow sensors, vacuum sensors, infrared sensors and imagers, electro-thermal converters for the measure of AC values, and thermal breakers. A thermopile is a temperature sensor based on the Seebeck effect. This effect results in the generation of a voltage between the ends of two joint materials (thermocouple) that have different Seebeck coefficients and are placed on a temperature gradient. To increase sensitivity a number of thermocouples are connected in series to form a thermopile. Suspended structures are quite thermally isolated from the bulk. Maximum thermal isolation is achieved by means of a high vacuum in the microstructure. The low thermal conductance is then exploited for measuring an incoming heat flux (infrared radiation) that warms up the suspended structure. The temperature rise is detected by means of thermopiles placed between the hot points in the suspended part and the substrate that acts as a heat sink and remains at ambient temperature. Figure 6 shows some examples of infrared detectors. Figure 6(a) shows a microstructure containing several micro-bridges. In each of them, there are two thermopiles placed between the middle of the bridge (maximum temperature rise) and the bulk. Figure 6(b) shows an infrared detector that uses a membrane. Here, thermopiles are situated on the four thin support arms connecting the membrane to the substrate. The advantage is the large surface of the membrane and the low heat conductivity of the long and narrow arms (as few metal lines as possible must be used in the thermopile to achieve the lowest thermal conductivity in the arms). The Seebeck coefficient of a poly1/metal1 thermocouple in the CMOS technology we have used is about 248 µV.K-1. This is a very high sensitivity that can be well exploited in thermal devices placed in a high vacuum, resulting in no convection losses which can be very important due to the large membrane surface. In order to implement self-test functions in thermopile based infrared sensors, we have to electrically induce a heat generation on the membrane. This function is easily made with a heating resistor placed on the centre of the membrane and electrically connected through the suspension arms. We illustrate this for the infrared sensor shown in schematic form in Figure 6(c). As shown by the FEM simulations of Figure 7, the temperature map obtained with the heating resistor in Figure 7(b) is not the same as the one obtained with a light irradiation in Figure 7(a) for the same heating power. However, since the thermopiles sense only the temperature gradient between the bulk and the hot junction between an arm and the membrane, it is possible to reproduce the same output signal in the thermopiles created by a distributed heat generation by controlling the electrical power in the heating resistor. A simulation of the device using a Hardware Description Language is shown in Figure 8. The device is decomposed in Figure 8(a) into several components for the support arms and the suspended membrane, and a power source connected to the membrane center. Each component is modeled as an one-dimensional or two-dimensional heat transmission line composed of thermal resistances representing the heat conduction through the beam and losses through convection in the air and by radiation. The heat stored in the material is model by thermal capacitances. Figure 8(b) shows the transient thermal behavior of the device in two different points : the membrane center and the warm junction. A temperature rise of 4.42°C is measured in the membrane center for an input power of 0.1 mW which gives a Seebeck voltage of 13.8 mV on the thermopile output. In order to mimic the effect of an incoming radiation we have to adjust the value of the nominal resistance to have the same temperature gradient in the support arms.
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membrane
thermopiles Heating resistor
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Figure 6. Examples of infrared detectors: (a) SEM of a bridge based detector, (b) SEM of membrane based detector, and (c) schematics of a membrane based detector containing a heating resistor.
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Figure 7. FEM thermal simulation of a membrane based infrared detector: (a) with surface distributed incoming power, and (b) with heating power generated in the central point.
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Figure 8. HDL simulation of the infrared detector: (a) schematics of the detector, and (b) simulation results of the temperature increase on two different points corresponding to the center of the membrane and the junction between arm and membrane.
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Example of a complete application: self-testing infrared imager
4.1
Principle of operation
The thermopile-based infrared imager is a device composed of a matrix of pixels of the type shown in Figure 6(c). The device pictured in Figure 9(a) is made by means of CMOS-compatible front-side bulk micro-machining via the CMP Service [3], using an Austrian Mikro Systeme (AMS) 0.6 µm microelectronic process. The infrared radiation absorbed on the Si3Nx membrane passivation layer will heat up the suspended micro-structure. The thermopiles placed on the support arms will sense the temperature gradient between the membrane and the substrate. The chip also contains scanning electronics that activate the pixels one by one row by row and connect the selected thermopile to the signal conditioning electronics. Figure 9(b) shows the electrical circuit for each pixel. In order to reach an optimal sensitivity the device is encapsulated in vacuum to avoid heat losses by convection. The chip shown in Figure 9(a) uses a 8x8 pixel matrix and occupies 4 mm2. This prototype has been used for validation purposes and large pixel matrices are required for industrial applications. This type of infrared imager can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning.
(a) (b) Figure 9. Infrared imager: (a) layout in fabrication, and (b) schematics of one pixel.
4.2
Analog interface
The thermopile delivers a voltage proportional to the temperature gradient between its hot and cold ends. The hot end of the thermopile corresponds to the junction of a support arm and the membrane, while the cold end corresponds to the junction of a support arm and the substrate. With an irradiation intensity of 10 µW the temperature on the membrane is about 0.44 K. Each pixel contains 10 polysilicon-aluminum thermocouples. Each thermocouple has a sensitivity of 248 µV K-1 and the overall sensitivity of a thermopile is 2.48 mV K-1 . The analog part must typically amplify a DC or low frequency signal with an amplitude below 1 mV. The circuit used is shown in Figure 10. The input signal is first modulated before being amplified in two consecutive stages. The output of both amplification stages uses correlated double sampling to cancel amplifier offset and noise. Each amplification stage has a gain around 40 and this allows us to obtain a total gain of 1600 (64dB). The output of the second stage is buffered and fed into a demodulator.
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4.3
Scanning logic and pixel control
The scanning circuit is composed of two shift-registers each made with a first JK flip-flop followed by 7 D flip-flops. The first shift-register scans the columns and the second the rows. Each pixel is then addressed by a row and column signal as shown in Figure 9(b). The chip has two control signals for two possible reading modes. In the first mode, the matrix is read continuously. In the second mode, a single frame is read (i.e. the matrix is read just once). For the pixel control, the two address signals (active by low level) are NORed. The output of this gate enables to pass the thermopile voltage into the global lines Thermopile+ and Thermopile- which are monitored by the analog interface. The chip works with two external clocks, one for the analog interface for modulation and correlated double sampling (from 10 to 100 kHz, well above the frequency of the thermally induced signals) with two non-overlapping phases φ1 and φ2 and their complemented signals generated on-chip. The second clock is used for the scanning system and determines the time length for the reading of a pixel and a frame. The upper limit for this clock frequency is limited by the other clock, and must allow the reading of several samples of a pixel signal before switching to the next pixel.
Figure 10. Schematics of the analog interface.
4.4
Self-test implementation
The self-test implementation consists of placing a heating resistor on the middle of the membrane with its wiring passing along the suspension arms as shown in Figure 9(b). The heating resistor will heat up the membrane and produce an electrical signal on the thermopile output under the control of a single signal (Test). The heat generation induced by an infrared radiation in a typical application is then replaced during self-test by an electrically induced heat. The implementation of the self-test function requires only a few modifications. In each pixel, an AND gate is driven by the signal Test and the output of the NOR gate which indicates when the pixel has been selected. The output of the NAND gate enables a very large PMOS (Ron
